l TEXAS
INSTRUMENTS
26
DDC264
SBAS368D –MAY 2006–REVISED DECEMBER 2016
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Typical Application (continued)
9.2.1 Design Requirements
For the following example, assume the user wants to measure the current coming from 128 photodiodes every
500 µs, and the maximum current per photodiode is 250 nA.
9.2.2 Detailed Design Procedure
9.2.2.1 Input Connection
Figure 31 represents a top level schematic of a solution for this case. 2 DDC264 are used. Inputs are
represented on the top schematic by the two connectors on the left and right sides.
The photodiodes must be connected to the inputs in such a way that the current flows into the device. To
achieve that, usually the anode of the photodiode is connected to the input of the device (see Figure 20) and the
cathode to a node with the same or higher voltage, in such a way that the photodiode is reverse biased or not
biased at all. The application usually determines the choice. No bias minimizes dark current in the photodiode;
therefore, minimizing errors during the integration or measurement of small signal currents. Nevertheless, the
parasitic junction capacitance of the photodiode decreases with the reverse bias voltage. The lower the input
capacitance, the lower the input noise (see Table 1). As such, applying a reverse bias reduces the noise of the
measurement while increasing the dark current. The user must choose depending on their application. In
applications with small signal currents, usually no bias is applied. In that case, the cathodes can be connected to
AGND.
Notice that although only positive currents (in the direction towards the inside of the device) can be measured,
the device has around 0.4% margin towards the negative excursion. In this way, small offsets and negative
currents do not saturate the device in the bottom rail and can be detected and measured.
9.2.2.2 Selecting Integration Time, Device Clock, and Range
The second step is to select the right integration time. There may be system level constraints that set this. For
instance, to get at least a given number of readings per second. Going faster than that may not be helpful,
degrade performance and increase power unnecessarily. In this case, the user wants to, at least, get 2 KSPS
(integration time = 500 µs). With 500 µs, the maximum integrated charge would be 250 nA × 500 µs = 125 pC.
This is too much for Range 2 (100 pC full scale) but falls comfortably in Range 3 (150 pC). As such, the likely
preferred option is to use Range 3 by setting bits 9 and 10 to one. Another potential option is to run the device
slightly faster such that Range 2 can be used. In this case, 100 pC/250 nA = 400 µs, or 2.5 KSPS. Notice that
this frequency (the frequency at which input currents are sampled) is actually 2× the frequency of the CONV
signal. That is, 400 µs is half the period of the CONV signal, i.e. the time between two consecutive edges of the
CONV signal.
The user must check the specification and performance curves to see the differences between both ranges for
the specific conditions. Normally, performance may be close in both cases and operating the device slower may
give some extra advantage on power and help relax practical system constraints.
For this particular case, both choices can be supported with the lower speed version device (DDC264C version),
which supports up to 3 KSPS. As such, to benefit from this, the user must set bit 7 to zero. In this mode, the
maximum internal clock is 5 MHz, so the user can choose to drive the CLK pin of the device with a 5-MHz clock
maximum or with a 20-MHz clock maximum and the internal divide by 4 (setting register bit 13 to one).
Notice that using a slower external clock is also possible, but the ADC conversion lasts longer (see tDR in
Table 2). This affects the time left to capture data after DVALID and before CONV edge (see Reading the
Measurement)
9.2.2.3 Voltage Reference
It is critical that VREF be stable during the different modes of operation (see Figure 22). The A/D converter
measures the voltage on the integrator with respect to VREF. Because the integrator capacitors are initially reset
to VREF, any drop in VREF from the time the capacitors are reset to the time when the converter measures the
integrator output introduces an offset. It is also important that VREF be stable over longer periods of time because
changes in VREF correspond directly to changes in the full-scale range. Finally, VREF must introduce as little
additional noise as possible.