USBLC6-2 Datasheet by STMicroelectronics

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116

I/O1 I/O1

GND VBUS

I/O2 I/O2

Functional diagram (top view)

Features

• 2 data-line protection

• Protects VBUS

• Very low capacitance: 3.5 pF max.

• Very low leakage current: 150 nA max.

• SOT-666 and SOT23-6L packages

• RoHS compliant

Benefits

• Very low capacitance between lines to GND for optimized data integrity and

speed

• Low PCB space consumption: 2.9 mm² max for SOT-666 and 9 mm² max for

SOT23-6L

• Enhanced ESD protection: IEC 61000-4-2 level 4 compliance guaranteed at

device level, hence greater immunity at system level

• ESD protection of VBUS

• High reliability offered by monolithic integration

• Low leakage current for longer operation of battery powered devices

• Fast response time

• Consistent D+ / D- signal balance:

– Very low capacitance matching tolerance I/O to GND = 0.015 pF

– Compliant with USB 2.0 requirements

Complies with the following standards:

• IEC 61000-4-2 level 4:

– 15 kV (air discharge)

– 8 kV (contact discharge)

Applications

• USB 2.0 ports up to 480 Mb/s (high speed)

• Compatible with USB 1.1 low and full speed

• Ethernet port: 10/100 Mb/s

• SIM card protection

• Video line protection

• Portable electronics

Description

The USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devices

dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet

links and video lines.

The very low line capacitance secures a high level of signal integrity without

compromising in protecting sensitive chips against the most stringently characterized

ESD strikes.

Product status link

USBLC6-2

Very low capacitance ESD protection

USBLC6-2

Datasheet

DS4260 - Rev 6 - October 2020

For further information contact your local STMicroelectronics sales office.

www.st.com

1Characteristics

Table 1. Absolute ratings (Tamb = 25 °C)

Symbol Parameter Value Unit

VPP Peak pulse voltage

IEC 61000-4-2 level 4 standard:

Air discharge

Contact discharge

MIL STD883G-Method 3015-7

Tstg Storage temperature range -55 to +150 °C

TjOperating junction temperature range -40 to +125 °C

TLMaximum lead temperature for soldering during 10 s at 5 mm 260 °C

Table 2. Electrical characteristics (Tamb = 25 °C)

Symbol Parameter Test conditions

Value

Unit

Min. Typ. Max.

IRM Leakage current VRM = 5.25 V 10 150 nA

VBR

Breakdown voltage

between

VBUS and GND

IR = 1 mA 6 V

VFForward voltage IF = 10 mA 1.1 V

VCL Clamping voltage

IPP = 1 A, 8/20 μs

Any I/O pin to GND

IPP = 5 A, 8/20 μs

Any I/O pin to GND

Ci/o-GND

Capacitance

between I/O and

GND

VR = 1.65 V 2.5 3.5

ΔCi/o-GND 0.015

Ci/o-i/o Capacitance

between I/O VR = 1.65 V 1.2 1.7

ΔCi/o-i/o 0.04

USBLC6-2

Characteristics

DS4260 - Rev 6 page 2/21

1.1 Characteristics (curves)

Figure 1. Capacitance versus voltage (typical values)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

C(pF)

F=1MHz

V =30mV

T =25°C

OSC RMS

C =I/O-I/O

C =I/O-GND

Data line voltage (V)

Figure 2. Line capacitance versus frequency (typical

values)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

0001001011

C(pF)

V =30mV

T =25°C

OSC RMS

V =0V to 3.3V

LINE

F(MHz)

Figure 3. Relative variation of leakage current versus

junction temperature (typical values)

100

25 50 75 100 125

T (°C)

V =5V

BUS

I [T

RM j] / I [T

RM j = 25 °C]

Figure 4. Frequency response

100.0k 1.0M 10.0M 100.0M 1.0G

-20.00

-15.00

-10.00

-5.00

0.00 S21(dB)

F(Hz)

USBLC6-2

Characteristics (curves)

DS4260 - Rev 6 page 3/21

2Technical information

2.1 Surge protection

The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.

The clamping voltage VCL can be calculated as follow:

VCL+ = VTRANSIL + VF for positive surges

VCL- = - VF for negative surges

with: VF = VT + Rd.Ip

(VF forward drop voltage) / (VT forward drop threshold voltage)

and VTRANSIL = VBR + Rd_TRANSIL.IP

Calculation example

We assume that the value of the dynamic resistance of the clamping diode is typically:

Rd = 0.5 Ω and VT = 1.1 V

We assume that the value of the dynamic resistance of the transil diode is typically:

Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V For an IEC 61000-4-2 surge level 4 (Contact Discharge: Vg = 8 kV, Rg = 330

Ω), VBUS = +5 V, and if in first approximation, we assume that:

Ip = Vg / Rg = 24 A.

So, we find:

VCL+ = +31.2 V

VCL- = -13 V

Note: The calculations do not take into account phenomena due to parasitic inductances.

2.2 Surge protection application example

If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from GND to PCB GND

plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances LVBUS, LI/O

and LGND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise

time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to LI/O.dl/dt + LGND.dI/dt.

The dI/dt is calculated as:

dI/dt = Ip/tr = 24 A/ns

The overvoltage due to the parasitic inductances is:

LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will

be:

VCL+ = +31.2 + 144 + 144 = 319.2 V

VCL- = -13.1 - 144 - 144 = -301.1 V

We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some

recommendations have to be followed (see ).

USBLC6-2

Technical information

DS4260 - Rev 6 page 4/21

Figure 5. ESD behavior: parasitic phenomena due to unsuitable layout

VBUS

LI/O LVBUS

LGND

LI/O

LGND

V pin

VCL

I/O pin

VTRANSIL V + V

TRANSIL F

- VF

VCL-

t = 1 ns

VCL+

GND pin

Data line

Positive

Surge

Negative

Surge

ESD surge on data line

dt LI/O + LGND

-LI/O - LGND

V+= V + V + L + L surge > 0

CL TRANSIL F I/O GND

V = -V - L - L surge > 0

CL- F I/O GND

Rd.IpVV BR

TRANSIL + =

USBLC6-2

Surge protection application example

DS4260 - Rev 6 page 5/21

nsunable layout TE nrm uuu Vin Vuul Vin Voul

2.3 How to ensure good ESD protection

While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the

board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin

and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena

(see Figure 6. ESD behavior: layout optimization and Figure 5. ESD behavior: parasitic phenomena due to

unsuitable layout for layout consideration).

Figure 6. ESD behavior: layout optimization

Unsuitable layout

Optimized layout

116

Figure 7. ESD behavior: measurement conditions

+5 V

IN OUT

TEST BOARD

ESD SURGE

USBLC6-2SC6

Figure 8. ESD response to IEC 61000-4-2 (+15 kV air

discharge)

Figure 9. ESD response to IEC 61000-4-2 (-15 kV air

discharge)

Note: Important: A good precaution to take is to put the protection device as close as possible to the disturbance

source (generally the connector).

USBLC6-2

How to ensure good ESD protection

DS4260 - Rev 6 page 6/21

2.4 Crosstalk behavior

2.4.1 Crosstalk phenomenon

Figure 10. Crosstalk phenomenon

Line 1

Line 2

VG1

VG2

RG1

RG2

DRIVERS

RL1

RL2

RECEIVERS

αβ

112

VG1 VG2

αβ

221

VG2 VG1

The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases

when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on

load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal

represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken

into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The

perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ).

Figure 11. Analog crosstalk measurements

NETWORK ANALYSER

PORT 2

NETWORK ANALYSER

PORT 1

TEST BOARD

Vbus

USBLC6-2SC6

Figure 11. Analog crosstalk measurements shows the measurement circuit for the analog application. In usual

frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see

Figure 12. Analog crosstalk results).

USBLC6-2

Crosstalk behavior

DS4260 - Rev 6 page 7/21

Figure 12. Analog crosstalk results

100.0k 1.0M 10.0M 100.0M 1.0G

- 120.00

- 90.00

- 60.00

- 30.00

0.00

F (Hz)

As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating

signals. The frequency response (Figure 4. Frequency response) gives attenuation information and shows that

the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable

signals like GSM (900 MHz) frequencies, for instance.

USBLC6-2

Crosstalk behavior

DS4260 - Rev 6 page 8/21

2.5 Application examples

Figure 13. USB 2.0 port application diagram using USBLC6-2

HUB-

DOWNSTREAM

TRANSCEIVER

+ 5V

RPD

Protecting

Bus Switch

DEVICE-

UPSTREAM

TRANSCEIVER

+ 3.3V

SW1

RPU

VBUS

D+

D-

GND

VBUS VBUS

VBUS

RX LS/FS +RX LS/FS +

RX LS/FS +

RX HS +RX HS +

RX HS +

TX HS +TX HS +

TX HS +

TX LS/FS +TX LS/FS +

TX LS/FS +

USB

connector

TX LS/FS - TX LS/FS -

TX LS/FS -

RX LS/FS - RX LS/FS -

RX LS/FS -

RX HS - RX HS -

RX HS -

TX HS - TX HS -

TX HS -

GND GND

GND

SW2

DEVICE-

UPSTREAM

TRANSCEIVER

USBLC6-4SC6

USBLC6-2P6

USBLC6-2SC6

+ 3.3V

SW1

RPU

VBUS

D+

D-

GND

USB

connector

SW2

OpenClosed then openHigh Speed HS

OpenClosedFull Speed FS

ClosedOpenLow Speed LS

SW2

SW1

Mode

USBLC6-2

Application examples

DS4260 - Rev 6 page 9/21

z : Mm NW Nu Nu

Figure 14. T1/E1/Ethernet protection

DATA

TRANSCEIVER

SMP75-8

+VCC

100nF

USBLC6-2SC6USBLC6-2SC6

2.6 PSpice model

Figure 15. PSpice model shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by

the PSpice parameters given in Figure 16. PSpice parameters.

Figure 15. PSpice model

MODEL = Dlow MODEL = Dhigh

VBUS

LI/O

LGND

GND

D+in

MODEL = Dzener

RI/O

LI/O

D-in

RI/O

LI/O

RGND RI/O

D-out

RI/O

MODEL = Dlow MODEL = Dhigh

LI/O

D+out

RI/O

Note: This simulation model is available only for an ambient temperature of 27 °C.

USBLC6-2

PSpice model

DS4260 - Rev 6 page 10/21

H Li

Figure 16. PSpice parameters

Dlow Dhigh Dzener

BV 50 50 7.3

CJ0 0.9p 2.0p 40p

IBV 1m 1m 1m

M 0.3333 0.3333 0.3333

RS 0.2 0.52 0.84

VJ 0.6 0.6 0.6

TT 0.1u 0.1u 0.1u

LI/O 750p

RI/O 110m

LGND 550p

RGND 60m

Figure 17. USBLC6-2 PCB layout considerations

D+in D+out

D-out

GND

USBLC6-2

D-in

VBUS

C = 100nF

BUS

USBLC6-2

PSpice model

DS4260 - Rev 6 page 11/21

Wm} EH +

3Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,

depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product

status are available at: www.st.com. ECOPACK is an ST trademark.

3.1 SOT23-6L package information

Figure 18. SOT23-6L package outline

Table 3. SOT23-6L package mechanical data

Ref.

Dimensions

Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A0.9 1.45 0.0354 0.0571

A1 0 0.15 0 0.0059

A2 0.9 1.3 0.0354 0.0512

b 0.30 0.5 0.0118 0.0197

c 0.09 0.2 0.0035 0.0079

D 2.8 3.05 0.1102 0.1201

E 1.5 1.75 0.0591 0.0689

e 0.95 0.0374

H 2.6 3 0.1024 0.1181

L 0.3 0.6 0.0118 0.0236

θ 0 10 0 0.3937

1. Value in inches are converted from mm and rounded to 4 decimal digits

USBLC6-2

Package information

DS4260 - Rev 6 page 12/21

Figure 19. Footprint recommendations, dimensions in mm (inches)

0.60

(0.024)

1.20

(0.047)

1.10

(0.043)

0.95

(0.037)

3.50

(0.138)

2.30

(0.091)

USBLC6-2

SOT23-6L package information

DS4260 - Rev 6 page 13/21

ngg ‘ +<><—t>

3.2 SOT-666 package information

Figure 20. SOT-666 package outline

USBLC6-2

SOT-666 package information

DS4260 - Rev 6 page 14/21

Table 4. SOT-666 package mechanical data

Ref.

Dimensions

Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A0.45 0.62 0.018 0.025

A3 0.08 0.18 0.003 0.007

b 0.17 0.34 0.007 0.013

D 1.50 1.70 0.059 0.067

E 1.50 1.70 0.059 0.067

E1 1.10 1.30 0.043 0.051

e 0.50 0.020

L1 0.19 0.007

L2 0.10 0.30 0.004 0.012

1. Value in inches are converted from mm and rounded to 4 decimal digits

Figure 21. Footprint recommendations, dimensions in mm

0.50

2.60

0.62

0.30

0.99

USBLC6-2

SOT-666 package information

DS4260 - Rev 6 page 15/21

Maximum cover (ape thickness 0.1 mm / / Sprocket hole Pin 1 \ocated according to EIA-481 Note: Pocket dimensions are not on sca‘e Pocket shape may vary dependmg on package 25180 max 1414

3.3 Packing information

Figure 22. Marking layout (refer to ordering information

table for marking)

X X X X

Figure 23. Package orientation in reel

Figure 24. Tape and reel orientation Figure 25. Reel dimensions (mm)

USBLC6-2

Packing information

DS4260 - Rev 6 page 16/21

25 205 205 .PD‘ raDo H o o o (i) O (:3 0’ 0.0.4 ______________ _ F w i . I - Q Q : (iv. ___._._.__ i=> — — : . I ‘ . l 1 P1 5 a D1 User direction of unreeling Note: Pocket dimensions are not on scale Pocket shape may vary depending on package

Figure 26. Inner box dimensions (mm)

Figure 27. Tape and reel outline

USBLC6-2

Packing information

DS4260 - Rev 6 page 17/21

Table 5. Tape and reel mechanical data

Ref.

Dimensions

Millimeters

Min. Typ. Max.

P1 3.9 4 4.1

P0 3.9 4 4.1

D0 1.45 1.5 1.6

D1 1

F 3.45 3.5 3.55

K0 1.3 1.4 1.6

P2 1.95 2 2.05

W 7.9 8 8.3

USBLC6-2

Packing information

DS4260 - Rev 6 page 18/21

6 = 6 Volts 2 = 2 lines 806 = SOT23—6L

4Ordering information

Figure 28. Ordering information scheme

USB LC 6 - 2 xxx

Product Designation

Low capacitance

Breakdown Voltage

Packages

6 = 6 Volts

2 = 2 lines

SC6 = SOT23-6L

P6 = SOT-666

Number of lines protected

Table 6. Ordering information

Order code Marking Package Weight Base qty. Delivery mode

USBLC6-2SC6 (1) UL26 SOT23-6L 16.7 mg 3000 Tape and reel

USBLC6-2P6(1) F SOT-666 2.9 mg 3000 Tape and reel

1. The marking code can be rotated by 90° to differentiate assembly location.

USBLC6-2

Ordering information

DS4260 - Rev 6 page 19/21

Revision history

Table 7. Document revision history

Date Version Changes

14-Mar-2005 1 Initial release.

07-Jun-2005 2 Format change to figure 3; no content changed.

20-Mar-2008 3

Added marking illustrations - Figures 21 and 23. Added ECOPACK statement.

Updated operating junction temperature range in absolute ratings, page 2.

Technical information section updated. Reformatted to current standards.

27-Jun-2011 4 Updated leakage current for VRM = 5.25 V as specified in USB standard.

Updated marking illustrations Figure 21 and Figure 23.

24-Oct-2011 5 Updated legal statement.

16-Oct-2020 6 Minor text changes.

USBLC6-2

DS4260 - Rev 6 page 20/21

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of

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names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

USBLC6-2

DS4260 - Rev 6 page 21/21

USBLC6-2 Datasheet by STMicroelectronics

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