TCA9539 Datasheet by Texas Instruments

V'.‘ 3!. B X E I TEXAS INSTRUMENTS
TCA9539
Peripheral Devices
I2C or SMBus
Master
(e.g. Processor)
SDA
SCL
INT P00
P01
RESET
P17
VCC
A1
GND
A0
x /RESET,
ENABLE,
or control
inputs
x /INT or
status
outputs
x LEDs
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9539
SCPS202C –OCTOBER 2009–REVISED MAY 2016
TCA9539 Low Voltage 16-Bit I
2
C and SMBus Low-Power I/O Expander with Interrupt
Output, Reset Pin, and Configuration Registers
1
1 Features
1• I2C to Parallel Port Expander
• Low Standby-Current Consumption
• Open-Drain Active-Low Interrupt Output
• Active-Low Reset Input
• 5-V Tolerant I/O Ports
• Compatible With Most Microcontrollers
• 400-kHz Fast I2C Bus
• Input and Output Configuration Register
• Polarity Inversion Register
• Internal Power-on Reset
• No Glitch on Power Up
• Noise Filter on SCL and SDA Inputs
• Address by Two Hardware Address Pins for Use
of up to Four Devices
• Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• Servers
• Routers (Telecom Switching Equipment)
• Personal Computers, smartphones
• Industrial Automation
• I2C GPIO Expansion
3 Description
The TCA9539 is a 24-pin device that provides 16 bits
of general purpose parallel input and output (I/O)
expansion for the two-line bidirectional I2C bus (or
SMBus protocol). The device can operate with a
power supply voltage (VCC) range from 1.65 V to 5.5
V. The device supports 100-kHz (I2C Standard mode)
and 400-kHz (I2C Fast mode) clock frequencies. I/O
expanders such as the TCA9539 provide a simple
solution when additional I/Os are needed for
switches, sensors, push-buttons, LEDs, fans, and
other similar devices.
The features of the TCA9539 include an interrupt that
is generated on the INT pin whenever an input port
changes state. The A0 and A1 hardware selectable
address pins allow up to four TCA9539 devices on
the same I2C bus. The device can be reset to its
default state by cycling the power supply and causing
a power-on-reset. Also, the TCA9539 has a hardware
RESET pin that can be used to reset the device to its
default state.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TCA9539
TSSOP (24) 7.80 mm × 4.40 mm
WQFN (24) 4.00 mm × 4.00 mm
VQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 I2C Interface Timing Requirements.......................... 7
6.7 RESET Timing Requirements................................... 8
6.8 Switching Characteristics.......................................... 8
6.9 Typical Characteristics.............................................. 9
7 Parameter Measurement Information ................ 12
8 Detailed Description............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 19
8.5 Programming .......................................................... 19
8.6 Register Maps ........................................................ 21
9 Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application ................................................. 26
10 Power Supply Recommendations ..................... 29
10.1 Power-On Reset Requirements ........................... 29
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1 Documentation Support ........................................ 33
12.2 Community Resources.......................................... 33
12.3 Trademarks........................................................... 33
12.4 Electrostatic Discharge Caution............................ 33
12.5 Glossary................................................................ 33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2015) to Revision C Page
• Made changes to Interrupt (INT) Output and Reads section ................................................................................................. 1
• Made changes to Recommended Operating Conditions........................................................................................................ 1
• Made changes to Electrical Characteristics............................................................................................................................ 1
• Added IOL for different Tj........................................................................................................................................................ 5
• Removed ΔICC spec from the Electrical Characteristics table, added ΔICC typical characteristics graph ............................. 6
• Changed ICC standby into different input states, with increased maximums ......................................................................... 7
• Changed Cio maximum .......................................................................................................................................................... 7
• Removed ΔICC spec from the Electrical Characteristics table, added ΔICC typical characteristics graph ............................. 7
• Clarified interrupt reset time (tir) with respect to falling edge of ACK related SCL pulse. ................................................... 13
• Updated Figure 33 and Figure 34 ........................................................................................................................................ 25
• Power on reset requirements relaxed ................................................................................................................................. 29
Changes from Revision A (September 2009) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Added RGE package.............................................................................................................................................................. 1
• Added Thermal Information table .......................................................................................................................................... 6
• Added "Time to reset; VCC = 1.65 V - 2.3 V" parameter to RESET Timing Requirements table. ......................................... 8
• Added "Output data valid; VCC = 1.65 V - 2.3 V to Switching Characteristics table. ............................................................. 8
‘5‘ TEXAS INSTRUMENTS CCCCCC 333333 PPPPPP .I:|:|:|:|:|:|:|:|:|:|:|. .L.|:|:L.|:|:|:|:|:|:|:L
A0
P17
P16
P15
P14
P13
24 22 21 20 19
SDA
RESET
A1
SCL
23
7 9 10 11 128
P00
P01
P02
P03
P04
P05
1
2
3
4
5
6
18
17
16
15
14
13
P10
P11
P06
P07
P12
GND
VCC
INT
Exposed
Center
Pad
INT
A1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
GND
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
3
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5 Pin Configuration and Functions
PW Package
24-Pins TSSOP
Top View
RTW, RGE Package
24-Pins WQFN, VQFN
Top View
Pin Functions
NAME
NO.
I/O DESCRIPTION
TSSOP
(PW) QFN
(RTW, RGE)
A0 21 18 I Address input. Connect directly to VCC or ground
A1 2 23 I Address input. Connect directly to VCC or ground
GND 12 9 — Ground
INT 1 22 O Interrupt open-drain output. Connect to VCC through a pull-up resistor
RESET 3 24 I Active-low reset input. Connect to VCC through a pull-up resistor if no active
connection is used
P00 4 1 I/O P-port input-output. Push-pull design structure. At power on, P00 is
configured as an input
P01 5 2 I/O P-port input-output. Push-pull design structure. At power on, P01 is
configured as an input
P02 6 3 I/O P-port input-output. Push-pull design structure. At power on, P02 is
configured as an input
P03 7 4 I/O P-port input-output. Push-pull design structure. At power on, P03 is
configured as an input
P04 8 5 I/O P-port input-output. Push-pull design structure. At power on, P04 is
configured as an input
P05 9 6 I/O P-port input-output. Push-pull design structure. At power on, P05 is
configured as an input
P06 10 7 I/O P-port input-output. Push-pull design structure. At power on, P06 is
configured as an input
P07 11 8 I/O P-port input-output. Push-pull design structure. At power on, P07 is
configured as an input
P10 13 10 I/O P-port input-output. Push-pull design structure. At power on, P10 is
configured as an input
P11 14 11 I/O P-port input-output. Push-pull design structure. At power on, P11 is
configured as an input
P12 15 12 I/O P-port input-output. Push-pull design structure. At power on, P12 is
configured as an input
P13 16 13 I/O P-port input-output. Push-pull design structure. At power on, P13 is
configured as an input
P14 17 14 I/O P-port input-output. Push-pull design structure. At power on, P14 is
configured as an input
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Pin Functions (continued)
NAME
NO.
I/O DESCRIPTION
TSSOP
(PW) QFN
(RTW, RGE)
P15 18 15 I/O P-port input-output. Push-pull design structure. At power on, P15 is
configured as an input
P16 19 16 I/O P-port input-output. Push-pull design structure. At power on, P16 is
configured as an input
P17 20 17 I/O P-port input-output. Push-pull design structure. At power on, P17 is
configured as an input
SCL 22 19 I Serial clock bus. Connect to VCC through a pull-up resistor
SDA 23 20 I/O Serial data bus. Connect to VCC through a pull-up resistor
VCC 24 21 — Supply voltage
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6 V
VIInput voltage(2) –0.5 6 V
VOOutput voltage (2) –0.5 6 V
IIK Input clamp current VI< 0 –20 mA
IOK Output clamp current VO< 0 –20 mA
IIOK Input-output clamp current VO< 0 or VO> VCC ±20 mA
IOL Continuous output low current VO= 0 to VCC 50 mA
IOH Continuous output high current VO= 0 to VCC –50 mA
ICC Continuous current through GND –250 mA
Continuous current through VCC 160
Tj(MAX) Maximum junction temperature 100 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2) ±1000
(1) For voltages applied above VCC, an increase in ICC will result.
(2) The values shown apply to specific junction temperatures, which depend on the RθJA of the package used. See the Calculating Junction
Temperature and Power Dissipation section on how to calculate the junction temperature.
6.3 Recommended Operating Conditions
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VIH High-level input voltage SCL, SDA 0.7 × VCC VCC (1) V
A0, A1, RESET, P07–P00, P10–P17 0.7 × VCC 5.5
VIL Low-level input voltage SCL, SDA, A0, A1, RESET, P07–P00, P10–P17 –0.5 0.3 × VCC V
IOH High-level output current P07–P00, P17–P10 –10 mA
IOL Low-level output current(2) P00–P07, P10–P17
Tj≤65°C 25
mATj≤85°C 18
Tj≤100°C 11
IOL Low-level output current(2) INT, SDA Tj≤85°C 6 mA
Tj≤100°C 3.5
TAOperating free-air temperature –40 85 °C
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC (1)
TCA9539
UNITPW (TSSOP) RTW (WQFN) RGE (VQFN)
24 PINS 24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 108.8 43.6 48.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54. 46.2 58.1 °C/W
RθJB Junction-to-board thermal resistance 62.8 22.1 27.1 °C/W
ψJT Junction-to-top characterization parameter 11.1 1.5 3.3 °C/W
ψJB Junction-to-board characterization parameter 62.3 22.2 27.2 °C/W
RθJC(bottom) Junction-to-case (bottom) thermal resistance — 10.7 15.3 °C/W
(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA= 25°C.
(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
VIK Input diode clamp voltage II= –18 mA 1.65 V to 5.5 V –1.2 V
VPOR
R
Power-on reset voltage, VCC
rising VI= VCC or GND, IO= 0
1.65 V to 5.5 V 1.2 1.5
V
VPOR
F
Power-on reset voltage, VCC
falling 1.65 V to 5.5 V 0.75 1
VOH P-port high-level output
voltage (2)
IOH = –8 mA
1.65 V 1.2
V
2.3 V 1.8
3 V 2.6
4.75 V 4.1
IOH = –10 mA
1.65 V 1
2.3 V 1.7
3 V 2.5
4.75 V 4
IOL
SDA VOL = 0.4 V 1.65 V to 5.5 V 3
mAP port (3) VOL = 0.5 V 1.65 V to 5.5 V 8
VOL = 0.7 V 1.65 V to 5.5 V 10
INT VOL = 0.4 V 3
IISCL, SDA VI= VCC or GND 1.65 V to 5.5 V ±1 μA
A0, A1, RESET ±1
IIH P port VI= VCC 1.65 V to 5.5 V 1 μA
IIL P port VI= GND 1.65 V to 5.5 V –1 μA
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
ICC
Operating mode VI= VCC or GND, IO= 0,
I/O = inputs, fSCL = 400 kHz, no load
5.5 V 22 40
μA
3.6 V 11 30
2.7 V 8 19
1.95 V 5 11
Standby mode VI= VCC or GND, IO= 0, I/O
= inputs,
fSCL = 0 kHz, no load
VI= VCC
5.5 V 1.5 3.9
3.6 V 0.9 2.2
2.7 V 0.6 1.8
1.95 V 0.4 1.5
VI= GND
5.5 V 1.5 8.7
3.6 V 0.9 4
2.7 V 0.6 3
1.95 V 0.4 2.2
CiSCL VI= VCC or GND 1.65 V to 5.5 V 3 8 pF
Cio SDA VIO = VCC or GND 1.65 V to 5.5 V 3 9.5 pF
P port 3.7 9.5
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)
MIN MAX UNIT
I2C BUS—STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 µs
tscl I2C clock low time 4.7 µs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0 ns
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 300 ns
tbuf I2C bus free time between stop and start 4.7 µs
tsts I2C start or repeated start condition setup 4.7 µs
tsth I2C start or repeated start condition hold 4 µs
tsps I2C stop condition setup 4 µs
tvd(data) Valid data time SCL low to SDA output valid 3.45 µs
tvd(ack) Valid data time of ACK condition ACK signal from SCL low to
SDA (out) low 3.45 µs
CbI2C bus capacitive load 400 pF
MIN MAX UNIT
I2C BUS—FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 µs
tscl I2C clock low time 1.3 µs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0 ns
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MIN MAX UNIT
ticr I2C input rise time 20 300 ns
ticf I2C input fall time 20 × (VCC /
5.5 V) 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 20 × (VCC /
5.5 V) 300 ns
tbuf I2C bus free time between stop and start 1.3 µs
tsts I2C start or repeated start condition setup 0.6 µs
tsth I2C start or repeated start condition hold 0.6 µs
tsps I2C stop condition setup 0.6 µs
tvd(data) Valid data time SCL low to SDA output valid 0.9 µs
tvd(ack) Valid data time of ACK condition ACK signal from SCL low to
SDA (out) low 0.9 µs
CbI2C bus capacitive load 400 pF
6.7 RESET Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 22)
MIN MAX UNIT
tWReset pulse duration 6 ns
tREC Reset recovery time 0 ns
tRESET Time to reset; for VCC = 2.3 V - 5.5 V 400 ns
Time to reset; for VCC = 1.65 V - 2.3 V 550 ns
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 20 and Figure 21)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN MAX UNIT
tiv Interrupt valid time P port INT 4 μs
tir Interrupt reset delay time SCL INT 4 μs
tpv Output data valid; For VCC = 2.3 V - 5.5 V SCL P port 200 ns
Output data valid; For VCC = 1.65 V - 2.3 V 300 ns
tps Input data setup time P port SCL 150 ns
tph Input data hold time P port SCL 1 μs
TEXAS INSTRUMENTS an an 35 so \\
VOL - Output Low Voltage (V)
IOL - Sink Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
5
10
15
20
25
30
35
D005
VCC = 1.8 V
-40 °C
25 °C
85 °C
VOL - Output Low Voltage (V)
IOL - Sink Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
D006
VCC = 2.5 V
-40 °C
25 °C
85 °C
VOL - Output Low Voltage (V)
IOL - Sink Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
5
10
15
20
25
30
D004
VCC = 1.65 V
-40 °C
25 °C
85 °C
TA - Temperature (°C)
ICC - Supply Current (µA)
-40 -15 10 35 60 85
0
4
8
12
16
20
24
28
32
36
40
D001
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
Vcc = 5.5V
TA - Temperature (°C)
ICC - Supply Current (µA)
-40 -15 10 35 60 85
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
D002
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
Vcc = 5.5V
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6.9 Typical Characteristics
TA= 25°C (unless otherwise noted)
Figure 1. Supply Current vs Temperature for Different
Supply Voltage (VCC)Figure 2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC)
Figure 3. Supply Current vs Supply Voltage for Different
Temperature (TA)Figure 4. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 1.65 V
Figure 5. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 1.8 V Figure 6. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 2.5 V
l TEXAS INSTRUMENTS 7o sou 20 25 \ \ | \ \ \\ \\ \\
VCC-VOH - Output High Voltage (V)
IOH - Source Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
5
10
15
20
D001D012
VCC = 1.65 V
-40 °C
25 °C
85 °C
VCC-VOH - Output High Voltage (V)
IOH - Source Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
5
10
15
20
25
D001D013
VCC = 1.8 V
-40 °C
25 °C
85 °C
VOL - Output Low Voltage (V)
IOL - Sink Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
70
80
90
D010
VCC = 5.5 V
-40 °C
25 °C
85 °C
TA - Temperature (°C)
VOL - Output Low Voltage (V)
-40 -15 10 35 60 85
0
50
100
150
200
250
300
D011
1.8 V, 1 mA
1.8 V, 10 mA
3.3 V, 1mA
3.3 V, 10 mA
5 V, 1 mA
5 V, 10 mA
VOL - Output Low Voltage (V)
IOL - Sink Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
70
D007
VCC = 3.3 V
-40 °C
25 °C
85 °C
VOL - Output Low Voltage (V)
IOL - Sink Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
70
80
D009
VCC = 5 V
-40 °C
25 °C
85 °C
10
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Typical Characteristics (continued)
TA= 25°C (unless otherwise noted)
Figure 7. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 3.3 V Figure 8. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 5 V
Figure 9. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 5.5 V Figure 10. II/O Low Voltage vs Temperature for Different VCC
and IOL
Figure 11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V Figure 12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
l TEXAS INSTRUMENTS 400 18
TA - Temperature (°C)
VCC-VOH - I/O High Voltage (mV)
-40 -15 10 35 60 85
50
100
150
200
250
300
350
400
D018
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
5 V, 10 mA
5.5 V, 10 mA
TA - Temperature (°C)
Delta ICC (µA)
-40 -15 10 35 60 85
0
3
6
9
12
15
18
D019
1.65 V
1.8 V
2.5 V
3.3 V
5 V
5.5 V
VCC-VOH - Output High Voltage (V)
IOH - Source Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
70
D016
VCC = 5 V
-40 °C
25 °C
85 °C
VCC-VOH - Output High Voltage (V)
IOH - Source Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
70
80
D017
VCC = 5.5 V
-40 °C
25 °C
85 °C
VCC-VOH - Output High Voltage (V)
IOH - Source Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
5
10
15
20
25
30
35
40
D001D014
VCC = 2.5 V
-40 °C
25 °C
85 °C
VCC-VOH - Output High Voltage (V)
IOH - Source Current (mA)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
10
20
30
40
50
60
D015
VCC = 3.3 V
-40 °C
25 °C
85 °C
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Typical Characteristics (continued)
TA= 25°C (unless otherwise noted)
Figure 13. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V Figure 14. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
Figure 15. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5 V Figure 16. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5.5 V
Figure 17. VCC – VOH Voltage vs Temperature for Different
VCC
Figure 18. ΔICC vs Temperature for Different VCC (VI= VCC –
0.6 V)
{L} TEXAS INSTRUMENTS
Voltage Waveforms
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tvd(ack)
tvd(data)
0.3 ×VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
SDA Load Configuration
ticf
Stop
Condition
(P)
tsp
0.7 ×VCC
0.3 ×VCC
0.7 ×VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
RL= 1 kΩ
VCC
CL= 50 pF
(see Note A)
DUT SDA
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7 Parameter Measurement Information
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 19. I2C Interface Load Circuit and Voltage Waveforms
i TEXAS INSTRUMENTS iTT
INT
R/W A
tir
0.7 ×VCC
0.3 ×VCC
0.7 ×VCC
0.3 ×VCC
0.7 ×VCC
0.3 ×VCC
0.7 ×VCC
0.3 ×VCC
INT SCL
tiv
Interupt Load Configuration
RL= 4.7 kΩ
VCC
CL= 100 pF
(see Note A)
DUT INT
SCL
SDA
INT
Start
Condition
R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
8765432
1AData 1 Data 4
A NA P
Data 2 Data 3 Data 4
tiv
tph tps
tir
Data 5
S1 1 1 01 A1 A0
1
Data Into
Port ( )Pn
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Parameter Measurement Information (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 20. Interrupt Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS
Write Mode (R/ = 0)W
P-Port Load Configuration
DUT
CL= 50 pF
(see Note A)
Pn
2×VCC
500
500 Ω
Read Mode (R/ = 1)W
Pn
P0 A
0.7 ×VCC
0.3 ×VCC
SCL P3
0.7 ×VCC
0.3 ×VCC
tps
tph
P0 A
0.7 ×VCC
0.3 ×VCC
SCL P3
tpv
(see Note B)
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
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Parameter Measurement Information (continued)
A. CLincludes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 21. P-Port Load Circuit and Voltage Waveforms
‘5‘ TEXAS INSTRUMENTS
SDA
SCL
Start
ACK or Read Cycle
tw
tREC
RESET
0.3 V CC
-V
CC/2
Px
SDA Load Configuration P-Port Load Configuration
VCC/2
tRESET
RL= 1 kΩ
VCC
CL= 50 pF
(see Note 1)
DUT SDA
DUT
CL= 50 pF
(see Note 1)
Pn
2 × VCC
500 Ω
500
(see Note 4)
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Parameter Measurement Information (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. I/Os are configured as inputs.
E. All parameters and waveforms are not applicable to all devices.
Figure 22. Reset Load Circuits and Voltage Waveforms
l TEXAS INSTRUMENTS
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8 Detailed Description
8.1 Overview
The TCA9539 is a 16-bit Input-Output expander for the two-line bidirectional bus (I2C) designed for 1.65-V to 5.5-
V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C
interface ,serial clock (SCL) and serial data (SDA).
The TCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The
data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the TCA9539 in the event of a time-out or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C-SMBus
state machine. Asserting RESET causes the same reset-initialization to occur without depowering the part.
The TCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA9539 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption.
The TCA9539 is similar to the PCA9555, except for the removal of the internal I/O pull-up resistor, which greatly
reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different address
range. The TCA9539 is equivalent to the PCA9539 with lower voltage support (down to VCC = 1.65 V), and also
improved power-on-reset circuitry for different application scenarios.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices
to share the same I2C bus or SMBus.
l TEXAS INSTRUMENTS 0 V *3 L 0 Copyrlgm @ 2016. Texas \nslmmems \ncorporamd
22
I/O
Port
P17−P10
Shift
Register 16 Bits
Interrupt
Logic
LP Filter
Input
Filter
23
Power-On
Reset
Read Pulse
Write Pulse
TCA9539
2
21
1
12
GND
24
VCC
3
RESET
SDA
SCL
A1
A0
INT
I2C Bus
Control
P07−P00
Copyright © 2016, Texas Instruments Incorporated
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8.2 Functional Block Diagram
A. Pin numbers shown are for PW package.
B. All I/Os are set to inputs at reset.
Figure 23. Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS Data From Data + a}? ’ agfi) Data 4‘ Data
VCC
CLK
D Q
FF
Configuration
Register
Data From
Shift Register
Data From
Shift Register
Q
Write Configuration
Pulse
CLK
D Q
FF
Q
Write Pulse
Output Port
Register
Q1
Q2
GND
I/O Pin
Output Port
Register Data
CLK
D Q
FF
Q
Input Port
Register
Read Pulse
CLK
D Q
FF
Q
Polarity Inversion
Register
Write Polarity
Pulse
Input Port
Register Data
Polarity
Register Data
To INT
Data From
Shift Register
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Functional Block Diagram (continued)
(1) At power-on reset, all registers return to default values.
Figure 24. Simplified Schematic of P-Port I/Os
8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
8.3.2 RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA9539 registers and
I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pull-up resistor to VCC, if no active connection is used.
l TEXAS INSTRUMENTS
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Feature Description (continued)
8.3.3 Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge
(ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of
changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of
the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is
transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pull-up resistor to VCC.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9539 in a reset condition until
VCC has reached VPOR R. At that point, the reset condition is released and the TCA9539 registers and I2C-SMBus
state machine initialize to their default states. After that, VCC must be lowered to below VPORF and then back up
to the operating voltage for a power-reset cycle.
8.5 Programming
8.5.1 I2C Interface
The TCA9539 has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read. For more information see Understanding the I2C Bus,SLVA704.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. For further details, see I2C Pull-up Resistor Calculation, SLVA689. Data transfer
may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a
STOP condition. See Table 1.
Figure 25 and Figure 26 show the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
‘5‘ TEXAS INSTRUMENTS ‘5 high able while SCL lme SDA line 51
SCL
SDA
MSB Bit Bit Bit Bit Bit Bit LSB
Byte: 1010 1010 ( 0xAAh )
1 0 101010
SDA line stable while SCL line is high
ACK
ACK
SCL
SDA
START
Condition
STOP
Condition
Data Transfer
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Programming (continued)
– Master-receiver terminates the transfer with a STOP condition.
Figure 25. Definition of Start and Stop Conditions
Figure 26. Bit Transfer
Table 1 shows the interface definition.
Table 1. Interface Definition
BYTE BIT
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address H H H L H A1 A0 R/W
P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00
P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10
l TEXAS INSTRUMENTS ;\HL\H
0 0 0 B2 B1 B000
1 1 1 0 A1 A0
Slave Address R/W
Fixed Programmable
1
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8.6 Register Maps
8.6.1 Device Address
Figure 27 shows the address byte of the TCA9539.
Figure 27. TCA9539 Address
Table 2 shows the address reference of the TCA9539.
Table 2. Address Reference
INPUTS I2C BUS SLAVE ADDRESS
A1 A0
L L 116 (decimal), 0x74 (hexadecimal)
L H 117 (decimal), 0x75 (hexadecimal)
H L 118 (decimal), 0x76 (hexadecimal)
H H 119 (decimal), 0x77 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Note that the I2C addresses shown above are the 7-bit, right-justified hexadecimal values.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte shown in
Table 3 that is stored in the control register in the TCA9539. Three bits of this data byte state the operation (read
or write) and the internal register (input, output, Polarity Inversion or Configuration) that is affected. This register
can be written or read through the I2C bus. The command byte is sent only during a write transmission.
When a command byte has been sent, the register pair that was addressed continues to be accessed by reads
until a new command byte has been sent. Figure 28 shows the control register bits.
Figure 28. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS COMMAND
BYTE (HEX) REGISTER PROTOCOL POWER-UP
DEFAULT
B2 B1 B0
0 0 0 0x00 Input Port 0 Read byte xxxx xxxx
0 0 1 0x01 Input Port 1 Read byte xxxx xxxx
0 1 0 0x02 Output Port 0 Read/write byte 1111 1111
0 1 1 0x03 Output Port 1 Read/write byte 1111 1111
1 0 0 0x04 Polarity Inversion Port 0 Read/write byte 0000 0000
1 0 1 0x05 Polarity Inversion Port 1 Read/write byte 0000 0000
1 1 0 0x06 Configuration Port 0 Read/write byte 1111 1111
1 1 1 0x07 Configuration Port 1 Read/write byte 1111 1111
l TEXAS INSTRUMENTS
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8.6.3 Register Descriptions
The Input Port registers (registers 0 and 1) shown in Table 4 reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on
read operation. Writes to these registers have no effect. The default value, X, is determined by the externally
applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next. See the Writes section for more information and examples.
Table 4. Registers 0 And 1 (Input Port Registers)
Bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default XXXXXXXX
Bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default XXXXXXXX
The Output Port registers (registers 2 and 3) shown in Table 5 show the outgoing logic levels of the pins defined
as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In
turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual
pin value.
Table 5. Registers 2 And 3 (Output Port Registers)
Bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 11111111
Bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 11111111
The Polarity Inversion registers (registers 4 and 5) shown in Table 6 allow Polarity Inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's
polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity
is retained.
Table 6. Registers 4 And 5 (Polarity Inversion Registers)
Bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 00000000
Bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 00000000
The Configuration registers (registers 6 and 7) shown in Table 7 configure the directions of the I/O pins. If a bit in
this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If
a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Registers 6 And 7 (Configuration Registers)
Bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 11111111
Bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 11111111
8.6.3.1 Bus Transactions
Data is exchanged between the master and the TCA9539 through write and read commands, and this is
accomplished by reading from or writing to registers in the slave device.
Registers are locations in the memory of the slave which contain information, whether it be the configuration
information or some sampled data to send back to the master. The master must write information to these
registers in order to instruct the slave device to perform a task.
l TEXAS INSTRUMENTS D D Write to one register in a device TT T ?1 ACK STOP T 11 T TT ACK STOP
S 1 1 1 0 1 A1 A0 0
Device (Slave) Address (7 bits)
1 0 0
0 0 0 0 0 A
Register Address 0x01 (8 bits)
D7 D6 D5 D4 D3 D2 D1 D0 A
Data Byte to Register 0x01 (8 bits)
AP
START R/W=0 ACK ACK ACK STOP
Master controls SDA line
Slave controls SDA line
S 1 1 1 0 1 A1 A0 0
Device (Slave) Address (7 bits)
B7 B6 B5 B4 B3 B2 B1 B0 A
Register Address N (8 bits)
D7 D6 D5 D4 D3 D2 D1 D0 A
Data Byte to Register N (8 bits)
AP
START R/W=0 ACK ACK ACK STOP
Write to one register in a device
Master controls SDA line
Slave controls SDA line
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8.6.3.1.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting
the master know it is ready. After this, the master starts sending the register data to the slave until the master
has sent all the data necessary (which is sometimes only a single byte), and the master terminates the
transmission with a STOP condition.
See the Register Descriptions section to see list of the TCA9539s internal registers and a description of each
one.
Figure 29 shows an example of writing a single byte to a slave register.
Figure 29. Write to Register
<br/>
Figure 30. Write to the Polarity Inversion Register
‘5‘ TEXAS INSTRUMENTS DD Read from one re ister in a device vs) Add star Addres wumm Regw STOP TT TT TT /w
Read from one register in a device
S 1 1 1 0 1A1 A0 0
Device (Slave) Address (7 bits)
B7 B6 B5 B4 B3 B2 B1 B0 A
Register Address N (8 bits)
A
START ACK ACK
1Sr 1 1 1 0 A1 A0
Device (Slave) Address (7 bits)
Repeated START
1 A D7 D6 D5 D4 D3 D2 D1 D0 NA
Data Byte from Register N (8 bits)
P
NACK STOPACK
Master controls SDA line
Slave controls SDA line
R/W=0 R/W=1
1 2
SCL
SDA A A A
Data 0
R/W
tpv
9
00 0 0 0 0 0 1 0.7 0.0 Data 11.7 1.0 A
S 1 1 1 0 1 A1 A0 0
tpv
P
Slave Address Command Byte Data to Port 0 Data to Port 1
Start Condition Acknowledge
From Slave
Write to Port
Data Out from Port 1
Data Out from Port 0
Data Valid
Acknowledge
From Slave
Acknowledge
From Slave
34567 8
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Figure 31. Write to Output Port Registers
8.6.3.1.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this
register address, the master sends a START condition again, followed by the slave address with the R/W bit set
to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA
bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
See the Register Descriptions section for the list of the TCA9539s internal registers and a description of each
one.
Figure 32 shows an example of reading a single byte from a slave register.
Figure 32. Read from Register
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, the restart
occurs when Input Port 0 is being read. The original command byte is forgotten. If a subsequent restart occurs,
Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first
byte is read, additional bytes may be read, but the data now reflect the information in the other register in the
pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.
b TEXAS INSTRUMENTS xxfl wwfl u W m m xxxxfwfl wax \\fl\\\
1 2 3 4 5 6 7 8 9
S 1 1 1 0 1 A1 A0 1 A A
10.x
A
11.x
A
10.x
1
11.x
P
R/W
SCL
SDA
INT
tir
tiv
t
t
t
t
ph
iv
iv
ph
00 10 03 11
tps
t
t
ph
ir
11 12
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Data 02Data 01Data 00 Data 03
DataDataData 10
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
1 2 3 4 5 6 7 8 9
S 1 1 1 0 1 A1 A0 1 A 7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 A
I1.x
7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 1
I1.x
P
R/W
SCL
SDA
INT
tir
tiv
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master No Acknowledge
From Master
25
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Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 32 for these details).
Figure 33. Read Input Port Register, Scenario 1
<br/>
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 32 for these details).
Figure 34. Read Input Port Register, Scenario 2
l TEXAS INSTRUMENTS Cupynghl © 2016, Texas Insimmems Incurpura|ed
P00
P01
P02
P03
P04
P05
A1
A0
A
B
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
VCC
VCC
VCC
(5 V)
Controlled Switch
(e.g., CBT Device)
GND
INT
SDA
SCL
10 k 10 kΩ 10 kΩ 10 kΩ 2 kΩ
INT
Subsystem 1
(e.g., T emperature
Sensor)
Subsystem 2
(e.g., Counter)
TCA9539
SDA
SCL
INT
GND
Keypad
ALARM
RESET
ENABLE
Subsystem 3
(e.g., Alarm)
Master
Controller
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
22
23
1
2
21
12
24 Ω 100 kΩ
100 kΩ 100 kΩ
RESET
3
VCC
Ω
Copyright © 2016, Texas Instruments Incorporated
26
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9539 has this device connected as a slave to an I2C master (processor), and the I2C bus
may contain any number of other slave devices. The TCA9539 is typically in a remote location from the master,
placed close to the GPIOs to which the master must monitor or control.
IO Expanders such as the TCA9539 are typically used for controlling LEDs (for feedback or status lights),
controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.
9.2 Typical Application
Figure 35 shows an application in which the TCA9539 can be used.
A. Device address is configured as 1110100 for this example.
B. P00, P02, and P03 are configured as outputs.
C. P01 and P04 to P17 are configured as inputs.
D. Pin numbers shown are for the PW package.
Figure 35. Application Schematic
l TEXAS INSTRUMENTS deoRLL 0L 0L)
VCC
VCC
LED
Pn
100 k
( )
( )
d_PORT _H OH CC OH
P I V V= ´ -
( )
d_PORT _L OL OL
P I V= ´
( )
d CC_ STATIC CC d _ PORT _ L d _PORT _ H
P I V P P» ´ + +
å å
( )
j A JA d
T T P= + q ´
27
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with this device, it is important that the Recommended Operating Conditions not be violated.
Many of the parameters of this device are rated based on junction temperature. So junction temperature must be
calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature
is shown in Equation 1.
(1)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal
Information table. Pdis the total power dissipation of the device, and the approximation is shown in Equation 2.
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high, or
outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by
the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to
calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
9.2.1.2 Minimizing ICC When I/Os Control LEDs
When an I/O is used to control an LED, normally it is connected to VCC through a resistor see Figure 35.
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in the Electrical Characteristics table shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the
LED is off, to minimize current consumption.
Figure 36 shows a high-value resistor in parallel with the LED. Figure 37 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional
supply-current consumption when the LED is off.
Figure 36. High-Value Resistor in Parallel with LED
l TEXAS INSTRUMENTS
Cb (pF)
Rp(max) (kOhm)
0 50 100 150 200 250 300 350 400 450
0
5
10
15
20
25
D008
Standard-mode
Fast-mode
VCC (V)
Rp(min) (kOhm)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
D009
VCC > 2V
VCC <= 2
r
p(max)
b
t
R0.8473 C
=
´
CC OL(max)
p(min)
OL
V V
RI
-
=
VCC
3.3 V 5 V
LED
Pn
28
TCA9539
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Typical Application (continued)
Figure 37. Device Supplied by Lower Voltage
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 5.
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr(300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb, see Equation 6.
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9554A, Cifor SCL or
Cio for SDA, the capacitance of wires, connections and traces, and the capacitance of additional slaves on the
bus.
9.2.3 Application Curves
Standard-mode Fast-mode
(fSCL= 100 kHz, tr= 1 µs) (fSCL= 400 kHz, tr= 300 ns)
Figure 38. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Figure 39. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VCC)
‘5‘ TEXAS INSTRUMENTS
VCC
Time
VCC_GH
VCC_GW
VCC_MV
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VCC drops below V 50 mV
PORF –
VCC_RT
VCC_FT
VCC_TRR
29
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(1) TA= –40°C to +85°C (unless otherwise noted)
10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA9539 can be reset to its default conditions by using the power-
on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The voltage waveform for a power-on reset is shown in Figure 40.
VCC Is lowered below the POR threshold, then ramped back up to VCC
Figure 40. Voltage Waveform for Power-On Reset
Table 8 specifies the performance of the power-on reset feature for the TCA9539.
Table 8. Recommended Supply Sequencing and Ramp Rates (1)
PARAMETER MIN TYP MAX UNIT
VCC_FT Fall rate See Figure 40 0.1 ms
VCC_RT Rise rate See Figure 40 0.1 ms
VCC_TRR Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when
VCC drops to GND) See Figure 40 1μs
VCC_GH The level (referenced to VCC) that VCC can glitch down to, but
not cause a functional disruption when VCC_GW See Figure 41 1.2 V
VCC_MV The minimum voltage that VCC can glitch down to without
causing a reset (VCC_GH must not be violated) See Figure 41 1.5 V
VCC_GW Glitch width that will not cause a functional disruption See Figure 41 10 μs
VPORF Voltage trip point of POR on falling VCC 0.75 1 V
VPORR Voltage trip point of POR on rising VCC 1.2 1.5 V
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 41 and Table 8 provide more
information on how to measure these specifications.
Figure 41. Glitch Width and Glitch Height
{L} TEXAS INSTRUMENTS
VPORR
30
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VPOR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all
the registers and the I2C-SMBus state machine are initialized to their default states. The value of VPOR differs
based on the VCC being lowered to or from 0. Figure 42 and Table 8 provide more details on this specification.
Figure 42. VPOR
l TEXAS INSTRUMENTS
31
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9539, common PCB layout practices must be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the TCA9539 as possible. These best practices are shown in Figure 43.
For the layout example provided in Figure 43, it would be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However,
a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to
route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other
internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are
placed directly next to the surface mount component pad which must attach to VCC or GND and the via is
connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace
must be routed to the opposite side of the board, but this technique is not demonstrated in Figure 43.
{yfimfi INSTRUMENTS LEGEND
VCC
VCC
GND
By-pass/de-coupling
capacitors
INT
A1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
GND P10
P11
P12
P13
P14
P15
P16
P17
A0
SCL
SDA
VCC
PW package
Via to power plane
Partial view of plane
Via to GND plane
LEGEND
(inner layer )
To I/Os
TCA9539
To I/Os
1
2
3
4
5
6
7
8
12
11
10
9
13
14
15
16
13
14
15
16
13
14
15
16
To processor
32
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11.2 Layout Example
Figure 43. TCA9539 Layout
l TEXAS INSTRUMENTS
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•Understanding the I2C Bus,SLVA704
•I2C Pull-up Resistor Calculation,SLVA689
•Introduction to Logic,SLVA700
•Maximum Clock Frequency of I2C Bus Using Repeaters,SLVA695
•IO Expander EVM User's Guide,SLVUA59A
•I2C Bus Pull-Up Resistor Calculation,SLVA689
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
TEXAS INSTRUMENTS Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 9-Dec-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TCA9539PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW539
TCA9539RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TD9539
TCA9539RTWR ACTIVE WQFN RTW 24 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW539
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 9-Dec-2021
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCA9539 :
•Automotive : TCA9539-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TCA9539PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TCA9539RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TCA9539RTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TCA9539RTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA9539PWR TSSOP PW 24 2000 356.0 356.0 35.0
TCA9539RGER VQFN RGE 24 3000 367.0 367.0 35.0
TCA9539RTWR WQFN RTW 24 3000 356.0 356.0 35.0
TCA9539RTWR WQFN RTW 24 3000 367.0 367.0 35.0
Pack Materials-Page 2
I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL fig
www.ti.com
PACKAGE OUTLINE
C
22X 0.65
2X
7.15
24X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
7.9
7.7
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
1
12 13
24
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.000
gmmmflgmmfij ‘w“““‘+“‘w““‘ Emma—5% R
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
12 13
24
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
fiflmmmmmfimmmfi$% Emma—5%g
www.ti.com
EXAMPLE STENCIL DESIGN
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
12 13
24
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
WQFN - 0.8 mm max heightRTW 24
PLASTIC QUAD FLATPACK - NO LEAD
4 x 4, 0.5 mm pitch
4224801/A
\‘T flnnmnn
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
PACKAGE OUTLINE
4219135/B 11/2016
www.ti.com
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
A
0.08 C
0.1 C A B
0.05 C
B
SYMM
SYMM
4.15
3.85
4.15
3.85
PIN 1 INDEX AREA
0.8 MAX
0.05
0.00
C
SEATING PLANE
PIN 1 ID
(OPTIONAL)
2X
2.5
20X 0.5
2X 2.5
1
6
18
13
712
24 19
2.45±0.1
24X 0.3
0.18
24X 0.5
0.3
(0.2) TYP
25
EXPOSED
THERMAL PAD
¢| |A , A @fifi? ,,,,, AA A A ,,,,,,,, mm A
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
EXAMPLE BOARD LAYOUT
4219135/B 11/2016
www.ti.com
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
( 2.45)
24X (0.6)
24X (0.24)
1
6
712
13
18
19
24
(3.8)
(0.97)
(3.8)
(0.97)
25
(R0.05)
TYP
20X (0.5)
(Ø0.2) TYP
VIA
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
EXAMPLE STENCIL DESIGN
4219135/B 11/2016
www.ti.com
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
(3.8)
(0.64) TYP
1
6
712
13
18
19
24
25
(0.64)
TYP
4X( 1.08)
(R0.05) TYP
(3.8)
20X (0.5)
24X (0.24)
24X (0.6)
METAL
TYP
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4204104/H
vi iv:‘l_$f CCCECCN
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
24X 0.3
0.2
2.45 0.1
24X 0.5
0.3
1 MAX
(0.2) TYP
0.05
0.00
20X 0.5
2X
2.5
2X 2.5
A4.1
3.9 B
4.1
3.9 0.3
0.2
0.5
0.3
VQFN - 1 mm max heightRGE0024B
PLASTIC QUAD FLATPACK - NO LEAD
4219013/A 05/2017
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
613
18
7 12
24 19
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
25 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
j|j
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
24X (0.25)
24X (0.6)
( 0.2) TYP
VIA
20X (0.5)
(3.8)
(3.8)
( 2.45)
(R0.05)
TYP
(0.975) TYP
VQFN - 1 mm max heightRGE0024B
PLASTIC QUAD FLATPACK - NO LEAD
4219013/A 05/2017
SYMM
1
6
712
13
18
19
24
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
25
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
j||4 wig? ; Vi
www.ti.com
EXAMPLE STENCIL DESIGN
24X (0.6)
24X (0.25)
20X (0.5)
(3.8)
(3.8)
4X ( 1.08)
(0.64)
TYP
(0.64) TYP
(R0.05) TYP
VQFN - 1 mm max heightRGE0024B
PLASTIC QUAD FLATPACK - NO LEAD
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
25
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
6
712
13
18
19
24
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