78.C1GMS.4010B Datasheet by Apacer Memory America

Apacer Access the best
RoHS Compliant
8GB DDR4 SDRAM UDIMM Halogen free
Product Specifications
November 4, 2015
Version 0.2
Apacer Technology Inc.
1F., No.32, Zhongcheng Rd., Tucheng Dist., New Taipei City 236, Taiwan
Tel: +886-2-2267-8000 Fax: +886-2-2267-2261
www.apacer.com
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Table of Contents
General Description ....................................................................................................... 2
Ordering Information ..................................................................................................... 2
Key Parameters .............................................................................................................. 2
Specifications: ................................................................................................................ 3
Features: ......................................................................................................................... 4
Pin Assignments ............................................................................................................. 5
Pin Descriptions ............................................................................................................. 7
Functional Block Diagram ............................................................................................. 8
Absolute Maximum Ratings ........................................................................................ 10
DRAM Component Operating Temperature Range ..................................................... 11
Operating Conditions ................................................................................................... 12
Mechanical Drawing .................................................................................................... 13
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General Description
Apacer 78.C1GMS.4010B is a 1024M x 64 DDR4 SDRAM (Synchronous
DRAM) DIMM. This high-density memory module consists of 16 pieces 512M x
8 bits with 4 banks DDR4 synchronous DRAMs in FBGA packages and a 4K
Bits EEPROM. The module is a 288-pins dual in-line memory module and is
intended for mounting into a connector socket. The following provides general
specifications of this module.
Ordering Information
Part Number Bandwidth Speed Grade Max Frequency CAS Latency
78.C1GMS.4010B 19.2 GB/sec 2400 Mbps 1200 MHz CL17
Density Organization Component Rank
8GB 1024M x 64 512M x8*16 2
Key Parameters
MT/s DDR4-1866 DDR4-2133 DDR4-2400
Unit
Grade -CL13 -CL15 -CL17
tCK (min) 1.07 0.93 0.83 ns
CAS latency 13 15 17 tCK
tRCD (min) 13.92 14.06 14.16 ns
tRP (min) 13.92 14.06 14.16 ns
tRAS (min) 34 33 32 ns
tRC (min) 47.92 47.05 46.16 ns
CL-tRCD-tRP 13-13-13 15-15-15 17-17-17 tCK
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Specifications:
♦ On-DIMM thermal sensor : No
♦ Organization: 1024 words x 64 bits, 2 ranks
♦ Integrating 16 pieces of 4G bits DDR4 SDRAM sealed FBGA
♦ Package: 288-pin socket type dual in-line memory module (DIMM)
♦ PCB: height 31.25 mm, lead pitch 0.85 mm (pin),
♦ Serial Presence Detect (SPD)
♦ Power Supply: VDD=1.2V (1.14V to 1.26V)
♦ VDDQ = 1.2V (1.14V to 1.26V)
♦ VPP = 2.5V (2.375V to 2.75V)
♦ VDDSPD = 2.2V to 3.6V
♦ 16 internal banks
♦ TC of 0°C to 95°C
–64ms, 8192-cycle refresh at 0°C to 85°C
–32ms at 85°C to 95°C
♦ Lead-free (RoHS compliant)
♦ Halogen free
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Features:
♦ Functionality and operations comply with the DDR4 SDRAM datasheet
♦ Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for
the banks in the same or dif-ferent bank group accesses are available
♦ Bi-Directional Differential Data Strobe
♦ 8 bit pre-fetch
♦ Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
♦ Supports ECC error correction and detection
♦ Per DRAM Addressability is supported
♦ Internal Vref DQ level generation is available
♦ Write CRC is supported at all speed grades
♦ DBI (Data Bus Inversion) is supported(x8)
♦ CA parity (Command/Address Parity) mode is supported
Apacer Artoss the Des: 1 12 v, NC 145 12 v, NC 74 CK071 213 CK171 2 v33 146 VREFCA 75 01076 219 CK17c a 004 147 v33 75 v00 220 v00 4 v33 143 005 77 v77 221 v77 5 000 149 v33 78 EVENT7n 222 PARITY 6 v33 150 001 79 A0 223 v00 7003971, 003971, 0M07n, DBIO7n, NC 7003976, 0039712, NC 9 v33 153 003071 32 RA37n/A16 226 v00 10 006 154 v33 33 v00 227 RFU 11 v33 155 007 34 0307n 223 WE7n/A14 12 002 156 v33 35 v00 229 v00 13 v33 157 003 35 CA37n/A15 230 NC, 3AVE7n 14 0012 153 v33 37 0070 231 v00 15 v33 159 0013 38 v00 232 A13 16 003 160 v33 39 0317n, NC 233 v00 17 v33 161 009 90 v00 234 NC, A17 70031071, 0031071, 0M17n, 03117n, NC 7003107c, 003107c, NC 20 v33 164 003171 93 CO, 0327n, NC 237 NC, cs37n, c1 21 0014 165 v33 94 v33 235 3A2 22 v33 166 0015 95 0036 239 v33 23 0010 167 v33 95 v33 240 0037 24 v33 163 0011 97 0032 241 v33 25 0020 169 v33 98 v33 242 0033 70031371, 0031371, 0M47n, 03147n, NC 7003137c, 00313712, NC 23 v33 172 0017 101 v33 245 003471 70031171, 0031171, 0M27n, 03127n, NC 7003117c, 003117c, NC 31 v33 175 003271 104 0034 243 v33 32 0022 176 v33 105 v33 249 0035 33 v33 177 0023 106 0044 250 v33 34 0018 173 v33 107 v33 251 0045 35 v33 179 0019 105 0040 252 v33 36 DQ28 130 v33 109 v33 253 0041 70031471, 0031471, 0M57n, 03157n, NC 7003147c, 00314712, NC 39 v33 133 0025 112 v33 256 003571
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Pin Assignments
Pin
No. Pin name Pin
No. Pin name Pin
No. Pin name Pin
No. Pin name
1 12 V, NC 145 12 V, NC 74 CK0_t 218 CK1_t
2 VSS 146 VREFCA 75 CK0_c 219 CK1_c
3 DQ4 147 VSS 76 VDD 220 VDD
4 VSS 148 DQ5 77 VTT 221 VTT
5 DQ0 149 VSS 78 EVENT_n 222 PARITY
6 VSS 150 DQ1 79 A0 223 VDD
7 TDQS9_t, DQS9_t,
DM0_n, DBI0_n, NC 151 VSS 80 VDD 224 BA1
8 TDQS9_c, DQS9_c,
NC 152 DQS0_c 81 BA0 225 A10/AP
9 VSS 153 DQS0_t 82 RAS_n/A16 226 VDD
10 DQ6 154 VSS 83 VDD 227 RFU
11 VSS 155 DQ7 84 CS0_n 228 WE_n/A14
12 DQ2 156 VSS 85 VDD 229 VDD
13 VSS 157 DQ3 86 CAS_n/A15 230 NC, SAVE_n
14 DQ12 158 VSS 87 ODT0 231 VDD
15 VSS 159 DQ13 88 VDD 232 A13
16 DQ8 160 VSS 89 CS1_n, NC 233 VDD
17 VSS 161 DQ9 90 VDD 234 NC, A17
18 TDQS10_t, DQS10_t,
DM1_n, DBI1_n, NC 162 VSS 91 ODT1, NC 235 NC, C2
19 TDQS10_c,
DQS10_c, NC 163 DQS1_c 92 VDD 236 VDD
20 VSS 164 DQS1_t 93 C0, CS2_n, NC 237 NC, CS3_n, C1
21 DQ14 165 VSS 94 VSS 238 SA2
22 VSS 166 DQ15 95 DQ36 239 VSS
23 DQ10 167 VSS 96 VSS 240 DQ37
24 VSS 168 DQ11 97 DQ32 241 VSS
25 DQ20 169 VSS 98 VSS 242 DQ33
26 VSS 170 DQ21 99 TDQS13_t, DQS13_t,
DM4_n, DBI4_n, NC 243 VSS
27 DQ16 171 VSS 100 TDQS13_c, DQS13_c,
NC 244 DQS4_c
28 VSS 172 DQ17 101 VSS 245 DQS4_t
29 TDQS11_t, DQS11_t,
DM2_n, DBI2_n, NC 173 VSS 102 DQ38 246 VSS
30 TDQS11_c,
DQS11_c, NC 174 DQS2_c 103 VSS 247 DQ39
31 VSS 175 DQS2_t 104 DQ34 248 VSS
32 DQ22 176 VSS 105 VSS 249 DQ35
33 VSS 177 DQ23 106 DQ44 250 VSS
34 DQ18 178 VSS 107 VSS 251 DQ45
35 VSS 179 DQ19 108 DQ40 252 VSS
36 DQ28 180 VSS 109 VSS 253 DQ41
37 VSS 181 DQ29 110 TDQS14_t, DQS14_t,
DM5_n, DBI5_n, NC 254 VSS
38 DQ24 182 VSS 111 TDQS14_c, DQS14_c,
NC 255 DQS5_c
39 VSS 183 DQ25 112 VSS 256 DQS5_t
Apacer Artoss the Des: 10051271, 0051271, 0M37n 00137n4, NC 10051276, 005127c, NC 42 v55 156 005371 115 0042 259 v55 43 0030 157 v55 116 v55 260 0043 44 v55 155 0031 117 0052 261 v55 45 0026 159 v55 118 v55 262 0053 46 v55 190 0027 119 0048 263 v55 47 054, NC 191 v55 12o v55 264 0049 10051571, 0051571, DM67n, 05167n, NC 10031576, 005157c, NC 50 v55 194 CB1, NC 123 v55 267 005671 10051771, 0051771, 0M87n, DBI87n, NC 10051776, 005177c, NC 53 v55 197 005871 126 0050 270 v55 54 CB6, NC 195 v55 127 v55 271 0051 55 v55 199 CB7, NC 128 0060 272 v55 56 CB2, NC 200 v55 129 v55 273 0061 57 v55 201 CB3, NC 130 0056 274 v55 55 RESET7n 202 v55 131 v55 275 0057 10051671, 0051671, DM77n, 05177n, NC TDQS167C, 005167c, NC 61 v00 205 RFU 134 v55 275 005771 62 ACT7n 206 v00 135 0062 279 v55 63 B60 207 561 136 v55 280 0063 64 v00 205 ALERT7n 137 0058 281 v55 65 A12/Bc7n 209 v00 138 v55 282 0059 66 A9 210 A11 139 5A0 283 v55 67 v00 211 A7 140 5A1 284 v0051=0 65 A8 212 v00 141 501 285 50A 69 A6 213 A5 142 VPP 286 VPP 70 v00 214 A4 143 VPP 287 VPP 71 A3 215 v00 144 RFU 288 VPP 72 A1 216 A2 73 v00 217 v00
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Pin
No. Pin name Pin
No. Pin name Pin
No. Pin name Pin
No. Pin name
40 TDQS12_t, DQS12_t,
DM3_n, DBI3_n4, NC 184 VSS 113 DQ46 257 VSS
41 TDQS12_c,
DQS12_c, NC 185 DQS3_c 114 VSS 258 DQ47
42 VSS 186 DQS3_t 115 DQ42 259 VSS
43 DQ30 187 VSS 116 VSS 260 DQ43
44 VSS 188 DQ31 117 DQ52 261 VSS
45 DQ26 189 VSS 118 VSS 262 DQ53
46 VSS 190 DQ27 119 DQ48 263 VSS
47 CB4, NC 191 VSS 120 VSS 264 DQ49
48 VSS 192 CB5, NC 121 TDQS15_t, DQS15_t,
DM6_n, DBI6_n, NC 265 VSS
49 CB0, NC 193 VSS 122 TDQS15_c, DQS15_c,
NC 266 DQS6_c
50 VSS 194 CB1, NC 123 VSS 267 DQS6_t
51 TDQS17_t, DQS17_t,
DM8_n, DBI8_n, NC 195 VSS 124 DQ54 268 VSS
52 TDQS17_c,
DQS17_c, NC 196 DQS8_c 125 VSS 269 DQ55
53 VSS 197 DQS8_t 126 DQ50 270 VSS
54 CB6, NC 198 VSS 127 VSS 271 DQ51
55 VSS 199 CB7, NC 128 DQ60 272 VSS
56 CB2, NC 200 VSS 129 VSS 273 DQ61
57 VSS 201 CB3, NC 130 DQ56 274 VSS
58 RESET_n 202 VSS 131 VSS 275 DQ57
59 VDD 203 CKE1, NC 132 TDQS16_t, DQS16_t,
DM7_n, DBI7_n, NC 276 VSS
60 CKE0 204 VDD 133 TDQS16_c, DQS16_c,
NC 277 DQS7_c
61 VDD 205 RFU 134 VSS 278 DQS7_t
62 ACT_n 206 VDD 135 DQ62 279 VSS
63 BG0 207 BG1 136 VSS 280 DQ63
64 VDD 208 ALERT_n 137 DQ58 281 VSS
65 A12/BC_n 209 VDD 138 VSS 282 DQ59
66 A9 210 A11 139 SA0 283 VSS
67 VDD 211 A7 140 SA1 284 VDDSPD
68 A8 212 VDD 141 SCL 285 SDA
69 A6 213 A5 142 VPP 286 VPP
70 VDD 214 A4 143 VPP 287 VPP
71 A3 215 VDD 144 RFU 288 VPP
72 A1 216 A2
73 VDD 217 VDD
1. Light colored text indicates functions that are not applicable for RDIMM wiring. An example is the NC for pin 56
because RDIMMs defined by this specification will always have DIMM wiring for this pin.
*IC Component Composition : 256Mx8 A0~A13
512Mx8 A0~A14, 512Mx4 A0~A14
1024Mx8 A0~A15, 1024Mx4 A0~A15
2048Mx8 A0~A16, 2048Mx4 A0~A16
Apacer moss inc best Ax" SDRAM address bus BAx SDRAM bank select BGx SDRAM bank group select RASJ2 SDRAM row address strobe CASin3 SDRAM column address strobe WEinA SDRAM write enable CSxin DIMM Rank Select Lines CKEx SDRAM clock enable lines ODTx SDRAM on—die termination control lines ACTin SDRAM input for activate input DQx DIMM memory data bus CBX DIMM ECC Check bits Not used on UDIMMs DQSxic Data Buffer data strobes (negative line ofdifferential pair) Dlein CKxit SDRAM clock input (positive line of differential pair) CKxic SDRAM clocks input (negative line of differential pair) SCL I2C serial bus clock for SPD-TSE and register SDA I2C serial bus data line for SPD-TSE and register SAX I2C slave address select for SPD-TSE and register PARITY SDRAM parity input VDD SDRAM core power supply 12 V Optional Power Supply on socket but not used on DIMM VSS Power supply return (ground) VDDSPD Serial SPD-TSE positive power supply ALERTJ SDRAM ALERTin output VPP SDRAM Supply RESETin Set Register and SDRAMs to a Known State EVENTin SPD signals a thermal event has occurred V‘l‘l SDRAM l/O termination supply RFU Reserved for future use
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Pin Descriptions
Pin Name Description
Ax1* SDRAM address bus
BAx SDRAM bank select
BGx SDRAM bank group select
RAS_n2* SDRAM row address strobe
CAS_n3* SDRAM column address strobe
WE_n4* SDRAM write enable
CSx_n DIMM Rank Select Lines
CKEx SDRAM clock enable lines
ODTx SDRAM on-die termination control lines
ACT_n SDRAM input for activate input
DQx DIMM memory data bus
CBx DIMM ECC check bits
TDQSx_t ; TDQSx_c Dummy loads for mixed populations of x4 based and x8 based RDIMMs.
Not used on UDIMMs
DQSx_t Data Buffer data strobes (positive line of differential pair)
DQSx_c Data Buffer data strobes (negative line of differential pair)
DMx_n,
DBIx_n SDRAM data masks/data bus inversion(x8-based x72 DIMMs)
CKx_t SDRAM clock input (positive line of differential pair)
CKx_c SDRAM clocks input (negative line of differential pair)
SCL I2C serial bus clock for SPD-TSE and register
SDA I2C serial bus data line for SPD-TSE and register
SAx I2C slave address select for SPD-TSE and register
PARITY SDRAM parity input
VDD SDRAM core power supply
12 V Optional Power Supply on socket but not used on DIMM
VREFCA SDRAM command/address reference supply
VSS Power supply return (ground)
VDDSPD Serial SPD-TSE positive power supply
ALERT_n SDRAM ALERT_n output
VPP SDRAM Supply
RESET_n Set Register and SDRAMs to a Known State
EVENT_n SPD signals a thermal event has occurred
VTT SDRAM I/O termination supply
RFU Reserved for future use
*Notes:
1. Address A17 is only valid for 16 Gb x4 based SDRAMs. For UDIMMs this connection pin is NC.
2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
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Functional Block Diagram
Part 1 of 2
CK0_t,CK0_c
A[0:16],BA[0:1],
ACT_n,PARITY,BG[0:1]
CK0_t,CK0_c
A[0:16],BA[0:1],
Address, Command and Control lines
Back
Front
D1 D2 D3 D5 D6D4 D7
D10 D8D9D11D12D13D14D15
DQ [0:7]
DQS0_t
DQS0_c
DQ [8:15]
DQS1_t
DQS1_c
DQ [16:23]
DQS2_t
DQS2_c
DQ [24:31]
DQS3_t
DQS3_c
DQ [32:39]
DQS4_t
DQS4_c
DQ [40:47]
DQS5_t
DQS5_c
DQ [48:55]
DQS6_t
DQS6_c
DQ [56:63]
DQS7_t
DQS7_c
CKE0
ODT0
CS0_n
D0
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
CKE0
CS0_n
ODT0
ACT_n,PARITY,BG[0:1]
A,BA,BG,Par
CK
D1
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D2
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D3
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D4
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D5
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D6
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D7
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D0
DM3_n/DBI3_n DM_n/DBI_n
DM2_n/DBI2_n DM_n/DBI_n
DM1_n/DBI1_n DM_n/DBI_n
DM0_n/DBI0_n DM_n/DBI_n DM4_n/DBI4_n DM_n/DBI_n
DM5_n/DBI5_n DM_n/DBI_n
DM6_n/DBI6_n DM_n/DBI_n
DM7_n/DBI7_n DM_n/DBI_n
Note 1: Unless otherwise noted, resistor values are 15Ω ± 5%.
Note 2: ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram.
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Part 2 of 2
V
SS
D0-D15
D0-D15
V
DD
D0-D15
VREFCA
V
DDSPD
Serial PD
V
TT
Note 1: Unless otherwise noted, resistor values are 15Ω ± 5%.
Note 2: ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram.
Note 3: For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 of 2.
Note 4: EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.
SA0 SA1 SA2
SA0 SA1
SDA
SCL
EVENT_n
SA2
EVENT_n
Serial PD with Thermal sensor
V
PP
D0-D15
CK1_t,CK1_c
A[0:16],BA[0:1],
ACT_n,PARITY,BG[0:1]
CK1_t,CK1_c
A[0:16],BA[0:1],
DQ [0:7]
DQS0_t
DQS0_c
DQ [8:15]
DQS1_t
DQS1_c
DQ [16:23]
DQS2_t
DQS2_c
DQ [24:31]
DQS3_t
DQS3_c
DQ [32:39]
DQS4_t
DQS4_c
DQ [40:47]
DQS5_t
DQS5_c
DQ [48:55]
DQS6_t
DQS6_c
DQ [56:63]
DQS7_t
DQS7_c
CKE1
ODT1
CS1_n
D15
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
CKE1
CS1_n
ODT1
ACT_n,PARITY,BG[0:1]
A,BA,BG
,Par
CK
D14
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D13
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D12
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG,Par
CK
D11
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG
,Par
CK
D10
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG
,Par
CK
D9
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG
,Par
CK
D8
DQS_c
DQS_t
CKE
CS_n
DQ [0:7]
ODT
ZQ
VSS
A,BA,BG
,Par
CK
DM0_n/DBI0_n DM_n/DBI_n
DM1_n/DBI1_n DM_n/DBI_n
DM2_n/DBI2_n DM_n/DBI_n
DM3_n/DBI3_n DM_n/DBI_n DM7_n/DBI7_n DM_n/DBI_n
DM6_n/DBI6_n DM_n/DBI_n
DM5_n/DBI5_n DM_n/DBI_n
DM4_n/DBI4_n DM_n/DBI_n
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Absolute Maximum Ratings
Parameter Symbol Description Units Notes
Voltage on VDD pin relative to Vss VDD - 0.3 V ~ 1.5 V V 1,3
Voltage on VDDQ pin relative to Vss VDDQ - 0.3 V ~ 1.5 V V 1,3
Voltage on VPP pin relative to Vss VPP - 0.3 V ~ 3.0 V V 4
Voltage on any pin relative to Vss VIN, VOUT - 0.3 V ~ 3.0 V V 1
Storage Temperature TSTG -55 to +100 ℃ 1,2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times; and VREFCA must be not greater than 0.6 x
VDDQ, When VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times
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DRAM Component Operating Temperature
Range
Symbol Parameter Rating Units Notes
TOPER
Normal Operating Temperature Range 0 to 85 ℃ 1,2
Extended Temperature Range 85 to 95 ℃ 1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For
measurement conditions please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0℃ - 85℃ under all operating
conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85℃ and 95℃
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature
Range. Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either
use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and
MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature
range.
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Operating Conditions
Recommended DC Operating Conditions – DDR4 (1.2V) operation
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3
VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3
VPP 2.375 2.5 2.75 V 3
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD..
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
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Revision History
Revision Date Description Remark
0.1 5/5/2014 Initial release
0.2 11/2/2015 Updated VDDSPD
Apacer Amhabd amlsa‘es@agacer com sa@agacerus com salesQagacer | salesQagacer om n sa‘es Ind|a@agace com
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Global Presence
Taiwan (Headquarters)
Apacer Technology Inc.
1F., No.32, Zhongcheng Rd., Tucheng Dist.,
New Taipei City 236, Taiwan R.O.C.
Tel: +886-2-2267-8000
Fax: +886-2-2267-2261
amtsales@apacer.com
U.S.A.
Apacer Memory America, Inc.
46732 Lakeview Blvd., Fremont, CA 94538
Tel: 1-408-518-8699
Fax: 1-510-249-9568
sa@apacerus.com
Japan
Apacer Technology Corp.
5F, Matsura Bldg., Shiba, Minato-Ku
Tokyo, 105-0014, Japan
Tel: 81-3-5419-2668
Fax: 81-3-5419-0018
jpservices@apacer.com
Europe
Apacer Technology B.V.
Science Park Eindhoven 5051 5692 EB Son,
The Netherlands
Tel: 31-40-267-0000
Fax: 31-40-290-0686
sales@apacer.nl
China
Apacer Electronic (Shanghai) Co., Ltd.
Room D, 22/FL, No.2, Lane 600, JieyunPlaza,
Tianshan RD , Shanghai , 200051, China
Tel: 86-21-6228-9939
Fax:86-21-6228-9936
sales@apacer.com.cn
India
Apacer Technologies Pvt Ltd.
Unit No.201, "Brigade Corner", 7th Block Jayanagar,
Yediyur Circle, Bangalore – 560082, India
Tel: 91-80-4152-9061
Fax: 91-80-4170-0215
sales_india@apacer.com