AOZ5636QI Datasheet

ALPHA & OMEGA SEMICONDUCTOR
Rev. 1.0 November 2018 www.aosmd.com Page 1 of 15
AOZ5636QI
High-Current, High-Performance
DrMos Power Module
General Description
The AOZ5636QI is a high efficiency synchronous buck
power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The High-Side MOSFET is optimized
to achieve low capacitance and gate charge for fast
switching with low duty cycle operation. The Low-Side
MOSFET has ultra low ON resistance to minimize
conduction loss.
The AOZ5636QI uses a PWM input for accurate control
of the power MOSFETs switching activities, is compatible
with 3V and 5V (CMOS) logic and supports Tri-State
PWM.
A number of features are provided making the
AOZ5636QI a highly versatile power module. The boot-
strap switch is integrated in the driver. The Low-Side
MOSFET can be driven into diode emulation mode to
provide asynchronous operation and improve light-load
performance. The pin-out is also optimized for low para-
sitics, keeping their effects to a minimum.
Features
4.5V to 20V power supply range
4.5V to 5.5V driver supply range
50A continuous output current
- Up to 70A with 10ms ON pulse
- Up to 110A with 10us ON pulse
Up to 2MHz switching operation
3V / 5V PWM / Tri-State input compatible
Under-Voltage Lockout protection
SMOD# control for Diode Emulation / CCM operation
Low Profile 5x5 QFN-31L package
Applications
Memory and graphic cards
VRMs for motherboards
Point of load DC/DC converters
Video gaming console
Typical Application
HS
Driver
VIN
BOOT
SMOD#
CBOOT CIN
VSWH L1 VOUT
PWM
COUT
GL
VCC PGND
PGND5V
PWM
Controller
Driver
Logic
and
Delay
LS
Driver
CPVCC
4.5V ~ 20V
DISB#
THWN
VCC
PVCC
AGND
CVCC
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AOZ5636QI
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Ordering Information
All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
QFN5x5-31L
(Top View)
Part Number Ambient Temperature Range Package Environmental
AOZ5636QI -40°C to +125°C QFN5x5-31L RoHS
31 30 29 28 27 25 24
1
2
23
3
PWM
22
4
PGND
21
5
10 11 12 13 14 15
SMOD#
VCC
NC
PHASE
VIN
VIN
VIN
PGND
PGND
PGND
PGND
VSWH
VSWH
VSWH
VSWH
VSWH
GL
PGND
PVCC
THWN
DISB#
VIN
GL
6
7
8
BOOT
VIN
AGND 20
19
18
17
16 VSWH
VSWH
VSWH
VSWH
9
26
PGND
VSWH
VSWH
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AOZ5636QI
Pin Description
Pin Number Pin Name Pin Function
1PWM
PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be
disconnected and this pin will be at high impedance.
2SMOD#
Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode.
There is an internal pull-down resistor to AGND.
3VCC
5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and
AGND (Pin 4).
4 AGND Signal Ground.
5BOOT
High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between
BOOT and the PHASE (Pin 7).
6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN.
7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5).
8, 9, 10, 11 VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET).
12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET).
16, 17, 18, 19,
20, 21, 22, 23,
24, 25, 26
VSWH
Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side
MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as
main inductor terminal.
27 GL Low-Side MOSFET Gate connection. This is for test purposes only.
28 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF
directly between PGND and PVCC (Pin 29).
29 PVCC 5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC
directly between PVCC and PGND (Pin 28).
30 THWN Thermal warning indicator. This is an open−drain output. When the temperature at the driver
IC die reaches the Over Temperature Threshold, this pin is pulled low.
31 DISB# Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an
internal pull−down resistor to AGND.
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AOZ5636QI
Functional Block Diagram
VSWH
VCC ZCD
PVCC
GL
PGND
ZCD Select REF/BIAS
UVLO
Level
Shifter
HS
Gate
Driver
Enable
Sequencing
And
Propagation
Delay Control
Boot HS
Control Logic
Driver
Logic
HS Gate
PHASE Check
LS Min On
ZCD Detect
LS
PWM
Tri-State
Logic
PWM
Tri-State
LS Gate
LS
Gate
Driver
SMOD#
PWM
VINBOOTVCC
PHASE
PVCC
Thermal
Monitor
THWN AGND
DISB#
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AOZ5636QI
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Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
Notes:
1. Peak voltages can be applied for 10ns per switching cycle.
2. Devices are inherently ESD sensitive, handling precaution are
required. Human body model rating: 1.5in series with 100pF.
Recommended Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter Rating
Low Voltage Supply (VCC, PVCC) -0.3V to 7V
High Voltage Supply (VIN) -0.3V to 25V
Control Inputs (PWM, SMOD#, DISB#) -0.3V to
(VCC+0.3V)
Output (THWN) -0.3V to
(VCC+0.3V)
Bootstrap Voltage DC (BOOT-PGND) -0.3V to 28V
Bootstrap Voltage Transient(1)
(BOOT-PGND) -8V to 35V
Bootstrap Voltage DC
(BOOT-PHASE/VSWH) -0.3V to 7V
BOOT Voltage Transient(1)
(BOOT-PHASE/VSWH) -0.3V to 9V
Switch Node Voltage DC
(PHASE/VSWH) -0.3V to 25V
Switch Node Voltage Transient(1)
(PHASE/VSWH) -8V to 33V
Low-Side Gate Voltage DC (GL) (PGND-0.3V) to
(PVCC+0.3V)
Low-Side Gate Voltage Transient(1)
(GL)
(PGND-2.5V) to
(PVCC+0.3V)
VSWH Current DC 50A
VSWH Current 10ms Pulse 70A
VSWH Current 10us Pulse 110A
Storage Temperature (TS) -65°C to +150°C
Max Junction Temperature (TJ) 150°C
ESD Rating(2) 2kV
Parameter Rating
High Voltage Supply (VIN) 4.5V to 20V
Low Voltage / MOSFET Driver
Supply VCC, PVCC 4.5V to 5.5V
Control Inputs
(PWM, SMOD#, DISB#) 0V to VCC
Output (THWN) 0V to VCC
Operating Frequency 200kHz to 2MHz
Electrical Characteristics(3)
TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VCC= PVCC= DISB# = 5.0V, unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Units
General
VIN Power Stage Power Supply 4.5 20 V
VCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V
RJC(3)
Thermal Resistance PCB Temp = 100°C 2.5 °C/W
RJA(3) 13.8 °C/W
Input Supply and UVLO
VCC_UVLO Under-Voltage Lockout VCC Rising 3.5 3.9 V
VCC_HYST VCC Hysteresis 400 mV
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AOZ5636QI
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Note:
3. All voltages are specified with respect to the corresponding AGND pin.
4. GH is an internal pin.
5. Characterization value. Not tested in production.
IVCC Control Circuit Bias Current
DISB# = 0V 1
µA
SMOD# = 5V, PWM = 0V 550
SMOD# = 0V, PWM = 0V 535
SMOD# = 0V, PWM =1.65V 430
IPVCC Drive Circuit Operating Current PWM = 400kHz, 20% Duty Cycle 20 mA
PWM = 1MHz, 20% Duty Cycle 50 mA
PWM Input
VPWMH Logic High Input Voltage 2.7 V
VPWML Logic Low Input Voltage 0.72 V
IPWM_SRC PWM Pin Input Current PWM = 0V -150 µA
IPWM_SNK PWM = 3.3V 150 µA
V
TRI
PWM Tri-State Window 1.35 1.95 V
VPWM_
FLOAT
PWM Tri-State Voltage Clamp PWM = Floating 1.65 V
DISB# Input
V
DISB#_ON
Enable Input Voltage 2.0 V
V
DISB#_OFF
Disable Input Voltage 0.8 V
R
DISB#
DISB# Input Resistance Pull-Down Resistor 850 kΩ
SMOD# Input
VSMOD#_H Logic High Input Voltage 2.0 V
VSMOD#_L Logic Low Input Voltage 0.8 V
RSMOD# SMOD# Input Resistance Pull-Down Resistor 850 kΩ
Gate Driver Timing
tPDLU PWM to High-Side Gate PWM: H L, VSWH: H L30ns
tPDLL PWM to Low-Side Gate PWM: L H, GL: H L25ns
tPDHU
Low-Side to High-Side Gate
Deadtime GL: H L, GH(4): L H15ns
tPDHL
High-Side to Low-Side Gate
Deadtime VSWH: H 1V, GL: L H13ns
tTSSHD Tri-State Shutdown Delay PWM: L VTRI, GL: H L and
PWM: H VTRI, VSWH: H L25 ns
tTSEXIT Tri-State Propagation Delay PWM: VTRI H, VSWH: L H
PWM: VTRI L, GL: L H35 ns
tLGMIN LS Minimum On Time SMOD# = L 350 ns
Thermal Notification
(5)
TJTHWN Junction Thermal Threshold Temperature Rising 150 °C
TJHYST Junction Thermal Hysteresis 30 °C
VTHWN THWN Pin Output Low ITHWN = 0.5mA 60 mV
RTHWN THWN Pull-Down Resistance 120 Ω
Electrical Characteristics(3)
TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VCC= PVCC= DISB# = 5.0V, unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Units
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AOZ5636QI
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Table 1. Input Control Truth Table
Note: Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State. Zero Cross Detection (ZCD) at
IL *Rdson(LS) = 0.5mV to turn off GL.
Timing Diagrams
Figure 1. PWM Logic Input Timing Diagram
Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram
DISB# SMOD# PWM(1) GH (Not a Pin) GL
LXXLL
HLHHL
HLLL
H, Forward IL
L, Reverse IL
HXTri-StateL L
HHHHL
HHL LH
VPWMH
VPWML
tPDLL
1V 1V
1V
tPDHU
tPDLU
1V
tPDHL
PWM
GL
VSWH
90%
tTSSHD
tTSEXIT
tTSSHD
TTSEXIT
tTSSHD
tTSEXIT
tTSSHD
tTSEXIT
PWM
GL
VSWH
VTRI
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AOZ5636QI
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Typical Characteristics
TA = 25°C, VIN = 12V, VOUT = 1.0V, PVCC = VCC = 5V, unless otherwise specified.
Figure 3. Efficiency vs Load Current Figure 4. Power Loss vs Load Current
Figure 5. Supply Current (IPVCC) vs. Temperature Figure 6. PWM Threshold vs. Temperature
Figure 7. SMOD# Threshold vs. Temperature Figure 8. UVLO (VCC) Threshold vs. Temperature
Efficiency (%)
Load Current (A)
0 5 10 15 20 30
25 35 40
94
91
88
85
82
79
76
73
70
500kHz
800kHz
300kHz
Power Loss (W)
Load Current (A)
0 5 10 15 20 30
25 40
35
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
05
500kHz
800kHz
300kHz
VCC Current (uA)
Temperature (°C)
-50 -25 0 25 50 100
75 150
125
600
580
560
540
520
500
480
460
440
PWM Voltage (V)
Temperature (°C)
-50 -25 0 25 50 100
75 150
125
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Logic High Threshold
Logic Low Threshold
Tri-state Window
Logic High Threshold
SMOD# Voltage (V)
Temperature (°C)
-50 -25 0 25 50 100
75 125 150
Logic Low Threshold
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VCC Voltage (V)
Temperature (°C)
-50 -25 0 25 50 100
75 125 150
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
Rising Threshold
Falling Threshold
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AOZ5636QI
Typical Characteristics (continued)
TA = 25°C, VIN = 12V, PVCC = VCC = 5V, unless otherwise specified.
Figure 9. DISB# Threshold vs. Temperature
Figure 10. PWM Threshold vs VCC Voltage
DISB# Voltage (V)
Temperature (°C)
-50 -25 0 25 50 100
75 125 150
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Logic High Threshold
Logic Low Threshold
DISB# Voltage (V)
Temperature (°C)
-50 -25 0 25 50 100
75 125 150
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Logic High Threshold
Logic Low Threshold
PWM Voltage (V)
VCC Voltage (V)
4.2 4.4 4.6 4.8 5 5.4
5.2 5.8
5.6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Logic High Threshold
Tri-state Window
Logic Low Threshold
ALPHA a OMEGA SEMICDND (Ic TOR
AOZ5636QI
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Application Information
AOZ5636QI is a fully integrated power module designed
to work over an input voltage range of 4.5V to 20V with a
separate 5V supply for gate drive and internal control cir-
cuitry. The MOSFETs are individually optimized for effi-
cient operation on both High-Side and Low-Side for a
low duty cycle synchronous buck converter. High current
MOSFET Gate Drivers are integrated in the package to
minimize parasitic loop inductance for optimum switching
efficiency.
Powering the Module and the Gate Drives
An external supply PVCC = 5V is required for driving the
MOSFETs. The MOSFETs are designed with optimally
customized gate thresholds voltages to achieve the most
advantageous compromise between fast switching
speed and minimal power loss. The integrated gate
driver is capable of supplying large peak current into the
Low-Side MOSFET to achieve fast switching. A ceramic
bypass capacitor of 1mF or higher is
recommended
from
PVCC (Pin 29) to PGND (Pin 28). The control logic sup-
ply VCC (Pin 3) can be derived from the gate drive sup-
ply PVCC (Pin 29) through an RC filter to bypass the
switching noise (See Typical Application Circuit).
The boost supply for driving the High-Side MOSFET is
generated by connecting a small capacitor (100nF)
between the BOOT (Pin 5) and the switching node
PHASE (Pin 7). It is recommended that this capacitor
CBOOT should be connected to the device across Pin 5
and Pin 7 as close as possible. A bootstrap switch is
integrated into the device to reduce external component
count. An optional resistor RBOOT in series with CBOOT
between 1Ω to 5Ω can be used to slow down the turn on
speed of the High-Side MOSFET to achieve both short
switching time and low VSWH switching node spikes at
the same time.
Under-voltage Lockout
AOZ5636QI starts up to normal operation when VCC
rises above the Under-Voltage LockOut (UVLO)
threshold voltage. The UVLO release is set at 3.5V
typically. Since the PWM control signal is provided from
an external controller or a digital processor, extra caution
must be taken during start up. AOZ5636QI must be
powered up before PWM input is applied.
Normal system operation begins with a soft start
sequence by the controller to minimize in-rush current
during start up. Powering the module with a full duty cycle
PWM signal may lead to many undesirable conse-
quences due to excessive power. AOZ5636QI provides
some protections such as UVLO and thermal monitor.
For system level protection, the PWM controller should
monitor the current output and protect the load under all pos-
sible operating and transient conditions.
Disable (DISB#) Function
The AOZ5636QI can be enabled and disabled through
DISB# (Pin 31). The driver output is disabled when
DISB# input is connected to AGND. The module would
be in standby mode with low quiescent current of less
than 1uA. The module will be active when DISB# is con-
nected to VCC Supply. The driver output will follow
PWM input signal. A weak pull-down resistor is con-
nected between DISB# and AGND.
Power up sequence design must be implemented to
ensure proper coordination between the module and
external PWM controller for soft start and system
enable/disable. It is recommended that the AOZ5636QI
should be disabled before the PWM controller is dis-
abled. This would make sure AOZ5636QI will be operat-
ing under the recommended conditions.
Input Voltage VIN
AOZ5636QI is rated to operate over a wide input range
from 4.5V to 20V. For high current synchronous buck
converter applications, large pulse current at high fre-
quency and high current slew rates (di/dt) will be drawn
by the module during normal operation. It is strongly rec-
ommended to place a bypass capacitor very close to the
package leads at the input supply (VIN). Both X7R or X5R
quality surface mount ceramic capacitors are suitable.
The High-Side MOSFET is optimized for fast switching by
using low gate charges (QG) device. When the module is
operated at high duty cycle ratio, conduction loss from the
High-Side MOSFET will be higher. The total power loss for
the module is still relatively low but the High-Side MOS-
FET higher conduction loss may have higher tempera-
ture. The two MOSFETs have their own exposed pads
and PCB copper areas for heat dissipation. It is recom-
mended that worst case junction temperature be mea-
sured for both High-Side MOSFET and Low-Side MOSFET
to ensure that they are operating within Safe Operating
Area (SOA).
PWM Input
AOZ5636QI is compatible with 3V and 5V (CMOS)
PWM logic. Refer to Figure 1 for PWM logic timing and
propagation delays diagram between PWM input and
the MOSFET gate drives.
The PWM is also compatible with Tri-State input. When
the PWM output from the external PWM controller is in
high impedance or not connected both High-Side and
Low-Side MOSFETs are turned off and VSWH is in high
impedance state. Table 2 shows the thresholds level for
high-to-low and low-to-high transitions as well as Tri-
State window.
ALPHA .5 OMEGA SEMICOND (Ic TOR
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There is a Holdoff Delay between the corresponding
PWM Tri-State signal and the MOSFET gate drivers to
prevent spurious triggering of Tri-State mode which may
be caused by noise or PWM signal glitches. The Holdoff
Delay is typically 25ns.
Table 2. PWM Input and Tri-State Threshold
Note: See Figure 2 for propagation delays and Tri-State window.
Diode Mode Emulation of Low-Side MOSFET
(SMOD#)
AOZ5636QI can be operated in the diode emulation or
pulse skipping mode using SMOD# (Pin 2). This
enables the converter to operate in asynchronous mode
during start up, light load or under pre-bias conditions.
When SMOD# is high, the module will operate in Con-
tinuous Conduction Mode (CCM). The Driver logic will
use the PWM signal and generate both the High-Side
and Low-Side complementary gate drive outputs with
minimal anti-overlap delays to avoid cross conduction.
When SMOD# is low, the module can operate in Dis-
continuous Conduction Mode (DCM). The High-Side
MOSFET gate drive output is not affected but Low-Side
MOSFET will enter diode emulation mode. See Table 1
for all truth table for DISB#, SMOD# and PWM inputs.
Gate Drives
AOZ5636QI has an internal high current high speed
driver that generates the floating gate driver for the
High-Side MOSFET and a complementary driver for the
Low-Side MOSFET. An internal shoot through protec-
tion scheme is implemented to ensure that both MOS-
FETs cannot be turned on at the same time. The
operation of PWM signal transition is illustrated as
below.
1) PWM from logic Low to logic High
When the falling edge of Low-Side Gate Driver output
GL goes below 1V, the blanking period is activated.
After a pre-determined value (tPDHU), the complemen-
tary High-Side Gate Driver output GH is turned on.
2) PWM from logic High to logic Low
When the falling edge of switching node VSWH goes
below 1V, the blanking period is activated. After a pre-
determined value (tPDHL), the complementary Low-Side
Gate Driver output GL is turned on.
This mechanism prevents cross conduction across the
input bus line VIN and PGND. The anti-overlap circuit
monitors the switching node VSWH to ensure a smooth
transition between the two MOSFETs under any load
transient conditions.
Thermal Warning (THWN)
The driver IC temperature is internally monitored and an
thermal warning flag at THWN (Pin 30) is asserted if it
exceeds 150°C. This warning flag is reset when the
temperature drop back to 120°C. THWN is an open
drain output that is pulled to AGND to indicate an over-
temperature condition. It should be connected to VCC
through a resistor for monitoring purpose. The device
will not power down during the over temperature condi-
tion.
PCB Layout Guidelines
AOZ5636QI is a high current module rated for operation
up to 2MHz. This requires fast switching speed to keep
the switching losses and device temperatures within lim-
its. An integrated gate driver within the package elimi-
nates driver-to-MOSFET gate pad parasitic of the
package or on PCB.
To achieve high switching speeds, high levels of slew
rate (dv/dt and di/dt) will be present throughout the
power train which requires careful attention to PCB lay-
out to minimize voltage spikes and other transients. As
with any synchronous buck converter layout, the critical
requirement is to minimize the path of the primary switch-
ing current loop formed by the High-Side MOSFET, Low-
Side MOSFET,
and the
input bypass capacitor CIN. The
PCB design is greatly simplified by the optimization of
the AOZ5636QI pin out. The power inputs of VIN and
PGND are located adjacent to each other and the input
bypass capacitors CIN should be placed as close as
possible to these pins. The area of the secondary
switching loop is formed by Low-Side MOSFET, output
inductor L1, and output capacitor COUT is the next criti-
cal requirement. This requires second layer or “Inner 1”
to be the PGND plane. VIAs should then be placed near
PGND pads.
While AOZ5636QI is a highly efficient module, it is still
dissipating significant amount of heat under high power con-
ditions. Special attention is required for thermal design.
MOSFETs in the package are directly attached to individ-
ual exposed pads (VIN and PGND) to simplify thermal
management. Both VIN and VSWH pads should be
attached to large areas of PCB copper. Thermal relief
pads should be placed to ensure proper heat dissipation
to the board. An inner power plane layer dedicated to
VIN, typically the high voltage system input, is desirable
and VIAs should be provided near the device to connect
Threshold VPWMH VPWML VTRIH VTRIL
AOZ5636QI 2.7V 0.72V 1.35V 1.95V
ALPHA & 0mm :EMICOND uc TOR descendin Figure 12.
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AOZ5636QI
the VIN pads to the power plane. Significant amount of
heat can also be dissipated through multiple PGND pins.
A large copper area connected to the PGND pins in addi-
tion to the system ground plane through VIAs will further
improve thermal dissipation.
Figure 11. Top Layer of Demo Board, VIN, VSWH
and PGND Copper Pads
As shown on Figure. 11, the top most layer of the PCB
should comprise of wide and exposed copper area for
the primary AC current loop which runs along VIN pad
originating from the input capacitors C10, C11 and C12
that are mounted to a large PGND pad. They serve as
thermal relief as heat flows down to the VIN exposed
pad that fan out to a wider area. Adding VIAs will only
help transfer heat to cooler regions of the PCB board
through the other layers beneath but serve no purpose
to AC activity as all the AC current sees the lowest
impedance on the top layer only.
As the primary and secondary (complimentary) AC cur-
rent loops move through VIN to VSWH and through
PGND to VSWH, large positive and negative voltage
spike appear at the VSWH terminal which are caused
by the large internal di/dt produced by the package par-
asitic. To minimize the effects of this interference at the
VSWH terminal, at which the main inductor L1 is
mounted, size just enough for the inductor to physically
fit. The goal is to employ the least amount of copper
area for this VSWH terminal, only enough so the induc-
tor can be securely mounted.
To minimize the effects of switching noise coupling to the
rest of the sensitive areas of the PCB, the area directly
underneath the designated VSWH pad or inductor
terminal is voided and the shape of this void is replicated
descending down through the rest of the layers. Refer to
Figure 12.
Figure 12. Bottom Layer of PCB
The exposed pads dimensional footprint of the 5x5 QFN
package is shown on the package dimensions page.
For optimal thermal relief, it is recommended to fill the
PGND and VIN exposed landing pattern with 10mil
diameter VIAs. 10mil diameter is a commonly used via
diameter as it is optimally cost effective based on the
tooling bit used in manufacturing. Each via is associated
with a 20mil diameter keep out. Maintain a 5mil clear-
ance (127um) around the inside edge of each exposed
pad in an event of solder overflow, potentially shorting
with the adjacent expose thermal pad.
ALPIIA I: OMEGA » mrmwm ma D mm mm 9v mums ‘0 LIJ TOP VIEW M w I m DIMENSION IN MM DIMENSION IN INCHES I | <£ %="" 2="" a="" 0,700="" 0,750="" 0900="" 0028="" 0030="" 0031="" a1="" 0000="" -="" 0050="" 0000="" -="" 0002="" 0.200ree="" 0009ref="" s‘de="" view="" d="" 4900="" 5,000="" 5100="" 0193="" 0197="" 0201="" 01="" 1,970="" 1,920="" 1970="" 0074="" 0076="" 0079="" recommended="" land="" pattern="" 02="" 0,950="" 0,900="" 0950="" 0033="" 0035="" 0037="" a="" 9:0qu="" 10="" eww’="" 3,="" i;="" d4="" 0250="" 0.300="" 0350="" 0010="" 0012="" 0014="" w="">7 E E g 0; E1 3975 3,925 3975 0153 0155 0156 g T E2 1270 1,320 1370 0050 0052 0054 N [ EIE I I S2393 fax—13““ E4 0500 0,550 0600 0020 0022 0024 Q I 1.750 % “19%: x W 81300 E6 3061 3,111 3161 0121 0122 0124 £14 + E; E7 0936 0,996 0936 0033 0035 0037 4 © © © “593 L 0350 0.400 0450 0014 0016 0019 © ' 0950 D @\ i 1.900 L2 0575 0.625 0675 0023 0025 0027 1.. g | / I § % g g 0,3 3 g] 50 L5 0450 0,500 0550 0018 0020 0022 EE§EE§§EE Egg; 01 0,130 0:010:21: 0230 0005 0323109751: 0009 (\IN—iv—i—io'déd Adam * UNI 1‘: mm NOTE CONTROLLING DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXAC .
Rev. 1.0 November 2018 www.aosmd.com Page 13 of 15
AOZ5636QI
Package Dimensions, QFN5x5A-31L, EP3_S
MIN NOM MAX MIN NOM MAX
A 0.700 0.750 0.800 0.028 0.030 0.031
A1 0.000 - 0.050 0.000 - 0.002
A2
D 4.900 5.000 5.100 0.193 0.197 0.201
E 4.900 5.000 5.100 0.193 0.197 0.201
D1 1.870 1.920 1.970 0.074 0.076 0.078
D2 0.850 0.900 0.950 0.033 0.035 0.037
D3 0.990 1.040 1.090 0.039 0.041 0.043
D4 0.250 0.300 0.350 0.010 0.012 0.014
D5 0.200 0.250 0.300 0.008 0.010 0.012
E1 3.875 3.925 3.975 0.153 0.155 0.156
E2 1.270 1.320 1.370 0.050 0.052 0.054
E3 2.050 2.100 2.150 0.081 0.083 0.085
E4 0.500 0.550 0.600 0.020 0.022 0.024
E5 1.661 1.711 1.761 0.065 0.067 0.069
E6 3.061 3.111 3.161 0.121 0.122 0.124
E7 0.836 0.886 0.936 0.033 0.035 0.037
E8 1.650 1.700 1.750 0.065 0.067 0.069
L 0.350 0.400 0.450 0.014 0.016 0.018
L1 0.350 0.400 0.450 0.014 0.016 0.018
L2 0.575 0.625 0.675 0.023 0.025 0.027
L3 0.350 0.400 0.450 0.014 0.016 0.018
L4 0.400 0.450 0.500 0.016 0.018 0.020
L5 0.450 0.500 0.550 0.018 0.020 0.022
b 0.200 0.250 0.300 0.008 0.010 0.012
b1 0.130 0.180 0.230 0.005 0.007 0.009
e
DIMENSION IN INCHESDIMENSION IN MM
0.500BSC
SYMBOLS
0.020BSC
0.200REF 0.008REF
ALPIIA I: OMEGA F mrmwm ma 4HFT I m 1.1 I 1.1 0— _ Kg- L. ‘ — P" ‘ n“ ‘— A” * rEEmNa nmzcnuu LINITI MM PACKAGE A0 120 KB 00 01 E E1 EE FD Fl P2 T QFNSXS 5.25 5.25 1.10 1.50 1.50 12.0 1.75 5.50 8.00 4.00 2.00 0.30 (12 mm) 10.10 20.10 20.10 MIN. 1%: 20.3 20.10 10.05 20.10 10.10 20.05 10.05 Uml Pzr Reel 3000pcs X l 4 PW um: MM TAPE SIZE REEL SIZE M N V V1 H K S G R V 12 Pm W330 ¢33Ufl $79.0 12.4 17.0 $13.0 10.5 2.0 ’ ’ 12.0 km :3.“ :5» 10.5 20.2 20.5 (9 6) ® (9 (9 (9 O i TRAILER TAPE 300 mm MIN. DR CDMFDNENTS TAPE *1 DRIENTATIDN IN PEICKET LEADER TAPE 4 500 mm MIN. DR
AOZ5636QI
Rev. 1.0 November 2018 www.aosmd.com Page 14 of 15
Tape and Reel Drawing, QFN5x5A-31L, EP3_S
Carrier Tape
Reel
Leader/Trailer & Orientation
NORMAL
ALPHA .5 OMEGA SEMICOND (Ic TOR AOS' products are provided subject to AOS‘ terms and hflgzllwwwaosmdcom/terms and condifions of sale
AOZ5636QI
Rev. 1.0 November 2018 www.aosmd.com Page 15 of 15
Part Marking
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
LEGAL DISCLAIMER
Applications or uses as critical components in life support devices or systems are not authorized. AOS does not
assume any liability arising out of such applications or uses of its products. AOS reserves the right to make
changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the
product for their intended application. Customer shall comply with applicable legal requirements, including all
applicable export control rules, regulations and limitations.
AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:
http://www.aosmd.com/terms_and_conditions_of_sale