SN54LVT8996, SN74LVT8996 Datasheet by Texas Instruments

Datasheet Feedback/Errors

u—u—u—‘ ] ] ] ] A0[ ] WI: ] GNDI: ] ] ] ] ] ] r—Il—u—H—H—H—H—I PTDO[ PTCKI: PTMS[ PTD‘ [ W[ {P TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments (TI)

Broad Family of Testability Products

Supporting IEEE Std 1149.1-1990 (JTAG)

Test Access Port (TAP) and Boundary-Scan

Architecture

Extend Scan Access From Board Level to

Higher Levels of System Integration

Promote Reuse of Lower-Level

(Chip/Board) Tests in System Environment

While Powered at 3.3 V, Both the Primary

and Secondary TAPs Are Fully 5-V Tolerant

for Interfacing to 5-V and/or 3.3-V Masters

and Targets

Switch-Based Architecture Allows Direct

Connect of Primary TAP to Secondary TAP

Primary TAP Is Multidrop for Minimal Use of

Backplane Wiring Channels

Shadow Protocols Can Occur in Any of

Test-Logic-Reset, Run-Test/Idle, Pause-DR,

and Pause-IR TAP States to Provide for

Board-to-Board Test and Built-In Self-Test

Simple Addressing (Shadow) Protocol Is

Received/Acknowledged on Primary TAP

10-Bit Address Space Provides for up to

1021 User-Specified Board Addresses

Bypass (BYP) Pin Forces

Primary-to-Secondary Connection Without

Use of Shadow Protocols

Connect (CON) Pin Provides Indication of

Primary-to-Secondary Connection

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Support Backplane Interface at Primary and

High Fanout at Secondary

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Package Options Include Plastic

Small-Outline (DW) and Thin Shrink

Small-Outline (PW) Packages, Ceramic

Chip Carriers (FK), and Ceramic DIPs (JT)

SN54LVT8996 ...JT PACKAGE

SN74LVT8996 . . . DW OR PW PACKAGE

(TOP VIEW)

BYP

GND

PTDO

PTCK

PTMS

PTDI

PTRST

VCC

CON

STDI

STCK

STMS

STDO

STRST

432128

12 13 14 15 16

VCC

CON

STDI

STCK

BYP

GND

PTDO

PTCK

SN54LVT8996 . . . FK PACKAGE

(TOP VIEW)

STRST

STDO

PTDI

PTRST

PTMS

STMS

27 26

NC – No internal connection

description

The ’LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE testability

integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate

testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a boundary-scannable

device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test

access port (TAP) to extend scan access beyond the board level.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and TI are trademarks of Texas Instruments Incorporated.

*9 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

These devices are functionally equivalent to the ’ABT8996 ASPs. Additionally, they are designed specifically

for low-voltage (3.3-V) VCC operation, but with the capability to interface to 5-V masters and/or targets.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP

signals to a set of secondary TAP signals – for example, to interface backplane TAP signals to a board-level

TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and

secondary TAPs are connected, only a moderate propagation delay is introduced – no storage/retiming

elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.

Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered

directly onto the secondary test clock (STCK) output.

Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the

secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the

assertion of the primary test reset (PTRST) input or by use of shadow protocol. PTRST is always buffered

directly onto the secondary test reset (STRST) output, ensuring that the ASP and its associated secondary TAP

can be reset simultaneously.

When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered

onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while

the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected,

STDO is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow

protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary

TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be

synchronously reset to the Test-Logic-Reset state.

In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged

on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR

or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols

is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially

at PTDI that matches that at the parallel address inputs (A9–A0), the ASP serially retransmits its address at

PTDO as an acknowledgment and then assumes the connected (ON) status, as above. If the received address

does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without

acknowledgment.

The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs

respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to

disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures

that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the

secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA)

causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA)

causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the

connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the

secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation

(such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is

valid only when received in the Pause-DR or Pause-IR TAP states.

Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP)

input. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up reset. This

bypassing feature is especially useful in the board-test environment, since it allows the board-level automated

test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP input is high, the ASP is free to

respond to shadow protocols. Otherwise, when BYP is low, shadow protocols are ignored.

gardless NW N \s (h andw tTAPsta *5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Whether the connected status is achieved by use of shadow protocol or by use of BYP, this status is indicated

by a low level at the connect (CON) output. Likewise, when the secondary TAP is disconnected from the primary

TAP, the CON output is high.

The SN54LVT8996 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74LVT8996 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS SHADOW-PROTOCOL OUTPUTS PRIMARY-TO-SECONDARY

BYP PTRST RESULT†STRST STCK STMS STDO PTDO CON CONNECT STATUS

L L — L PTCK H‡PTDI STDI L BYP/TRST‡

LH—H PTCK PTMS PTDI STDI L BYP

HL—L PTCK H Z Z H TRST

H H RESET H PTCK H Z Z H RESET

H H MATCH H PTCK PTMS PTDI STDI L ON

HH NO MATCH H PTCK STMS0§Z Z H OFF

HH HARD ERROR¶H PTCK STMS0§Z Z H OFF

H H DISCONNECT H PTCK STMS0§Z Z H OFF

H H TEST SYNCHRONIZATION H PTCK PTMS PTDI Z L MULTICAST

†Shadow protocols are received serially via PTCK and PTDI and acknowledged serially via PTCK and PTDO under certain conditions in which

PTMS is static low or static high (see shadow protocol). The result shown here follows any required acknowledgment.

‡In normal operation of IEEE Std 1149.1-compliant architectures, it is recommended that TMS be high prior to release of TRST. The BYP/TRST

connect status ensures that this condition is met at STMS regardless of the applied PTMS. Also, it is recommended that STMS be kept high for

a minimum duration of 5 PTCK cycles following assertion of PTRST, either by maintaining PTRST low or by setting PTMS high. This ensures

that ICs both with and without TRST inputs are moved to their Test-Logic-Reset TAP states. It is expected that in normal application, this condition

occurs only when BYP is fixed at the low state. In such case, upon release of PTRST, the ASP immediately resumes the BYP connect status.

§STMS level before indicated steady-state conditions were established

¶The shadow protocol is well defined. Some variations in the protocol are tolerated (see protocol errors). Those that are not tolerated produce

protocol result HARD ERROR and cause disconnect as indicated.

PTRST PTMS PTDI STDI Shadow—Prnlncol Receive Connect Conllol AQ—AD Shadow—Prnlncol Transmil *9 TEXAS INSTRUMENTS 4 POST OFFICE EOX $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

CON

Shadow-Protocol

Receive

PTCK

PTRST

VCC STCK

STRST

STMSPTMS

VCC

PTDI

VCC

STDO

STDI

VCC

PTDO

BYP

VCC

A9–A0

VCC Connect Control

Shadow-Protocol

Transmit

Pin numbers shown are for the DW, JT, and PW packages.

20–24,

1–5

*5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME DESCRIPTION

A9–A0 Address inputs. The ASP compares addresses received via shadow protocol against the value at A9–A0 to determine address

match. The bit order is from most significant to least significant. An internal pullup at each A9–A0 terminal forces the terminal

to a high level if it has no external connection.

BYP Bypass input. A low input at BYP forces the ASP into BYP or BYP/TRST status, depending on PTRST being high or low,

respectively. While BYP is low, shadow protocols are ignored. Otherwise, while BYP is high, the ASP is free to respond to

shadow protocols. An internal pullup forces BYP to a high level if it has no external connection.

CON Connect indicator (output). The ASP indicates secondary-scan-port activity (resulting from BYP, BYP/TRST, MULTICAST, or

ON status) by forcing CON to be low. Inactivity (resulting from OFF, RESET, or TRST status) is indicated when CON is high.

GND Ground

PTCK Primary test clock. PTCK receives the TCK signal required by IEEE Std 1149.1-1990. The ASP always buffers PTCK to STCK.

Shadow protocols are received/acknowledged synchronously to PTCK and connect-status changes invoked by shadow

protocol are made synchronously to PTCK.

PTDI

Primary test data input. PTDI receives the TDI signal required by IEEE Std 1149.1-1990. During appropriate TAP states, the

ASP monitors PTDI for shadow protocols. During shadow protocols, data at PTDI is captured on the rising edge of PTCK. When

a valid shadow protocol is received in this fashion, the ASP compares the received address against the A9–A0 inputs. If the

ASP detects a match, it outputs an acknowledgment and then connects its primary TAP terminals to its secondary TAP

terminals. Under BYP, BYP/TRST, MULTICAST or ON status, the ASP buffers the PTDI signal to STDO. An internal pullup

forces PTDI to a high level if it has no external connection.

PTDO

Primary test data output. PTDO transmits the TDO signal required by IEEE Std 1149.1-1990. During shadow protocols, the

ASP transmits any required acknowledgment via the PTDO. The acknowledgment data output at PTDO changes on the falling

edge of PTCK. Under BYP, BYP/TRST, or ON status, the ASP buffers the PTDO signal from STDI. Under OFF, MULTICAST,

RESET, or TRST status, PTDO is at high impedance.

PTMS

Primary test mode select. PTMS receives the TMS signal required by IEEE Std 1149.1-1990. The ASP monitors the PTMS to

determine the TAP-controller state. During stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset,

Run-Test-Idle, Pause-DR, Pause-IR) the ASP can respond to shadow protocols. Under BYP, MULTICAST, or ON status, the

ASP buffers the PTMS signal to STMS. An internal pullup forces PTMS to a high level if it has no external connection.

PTRST

Primary test reset. PTRST receives the TRST signal allowed by IEEE Std 1149.1-1990. The ASP always buffers PTRST to

STRST. A low input at PTRST forces the ASP to assume TRST or BYP/TRST status, depending on BYP being high or low,

respectively. Such operation also asynchronously resets the internal ASP state to its power-up condition. Otherwise, while

PTRST is high, the ASP is free to respond to shadow protocols. An internal pullup forces PTRST to a high level if it has no

external connection.

STCK Secondary test clock. STCK retransmits the TCK signal required by IEEE Std 1149.1-1990. The ASP always buffers STCK from

PTCK.

STDI Secondary test data input. STDI receives the TDI signal required by IEEE Std 1149.1-1990. Under BYP, BYP/TRST, or ON

status, the ASP buffers STDI to PTDO. An internal pullup forces STDI to a high level if it has no external connection.

STDO Secondary test data output. STDO transmits the TDO signal required by IEEE Std 1149.1-1990. Under BYP, BYP/TRST,

MULTICAST, or ON status, the ASP buffers STDO from PTDI. Under OFF, RESET, or TRST status, STDO is at high impedance.

STMS

Secondary test mode select. STMS retransmits the TMS signal required by IEEE Std 1149.1-1990. Under BYP, MULTICAST,

or ON status, the ASP buffers STMS from PTMS. When disconnected (as a result of OFF status), STMS maintains its last valid

state until the ASP assumes BYP/TRST, RESET, or TRST status (upon which it is forced high) or the ASP again assumes BYP,

MULTICAST, or ON status.

STRST Secondary test reset. STRST retransmits the TRST signal allowed by IEEE Std 1149.1-1990. The ASP always buffers STRST

from PTRST.

VCC Supply voltage

INSTRUMENTS *5 TEXAS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

application information

In application, the ASP is used at each of several (serially-chained) groups of IEEE Std 1149.1-compliant

devices. The ASP for each such group is assigned an address (via inputs A9–A0) that is unique from that

assigned to ASPs for the remaining groups. Each ASP is wired at its primary TAP to common (multidrop) TAP

signals (sourced from a central IEEE Std 1149.1 bus master) and fans out its secondary TAP signals to the

specific group of IEEE Std 1149.1-compliant devices with which it is associated. An example is shown in

Figure 1.

ASP

IEEE Std 1149.1-

Compliant

Device Chain

PTRST

PTDI

PTMS

PTCK

PTDO

STRST

STDO

STMS

STCK

STDI

ADDR1

A9–A0

ASP

IEEE Std 1149.1-

Compliant

Device Chain

PTRST

PTDI

PTMS

PTCK

PTDO

STRST

STDO

STMS

STCK

STDI

ADDR2

A9–A0

ASP

IEEE Std 1149.1-

Compliant

Device Chain

PTRST

PTDI

PTMS

PTCK

PTDO

STRST

STDO

STMS

STCK

STDI

ADDR3

A9–A0

TRST

TDO

TMS

TCK

TDI

IEEE

Std

1149.1

Bus

Master

Other

Modules

BYP

Figure 1. ASP Application

This application allows the ASP to be wired to a 4- or 5-wire multidrop test access bus, such as might be found

on a backplane. Each ASP would then be located on a module, for example a printed-circuit board (PCB), that

contains a serial chain of IEEE Std 1149.1-compliant devices and that would plug into the module-to-module

bus (e.g., backplane). In the complete system, the ASP shadow protocols would allow the selection of the scan

chain on a single module. The selected scan chain could then be controlled, via the multidrop TAP, as if it were

the only scan chain in the system. Normal IR and DR scans can then be performed to accomplish the module

test objectives.

Once scan operations to a given module are complete, another module can be selected in the same fashion,

at which time the ASP-based connection to the first module is dissolved. This procedure can be continued

progressively for each module to be tested. Finally, one of two global addresses can be issued to either leave

all modules unselected (disconnect address, DSA) or to deselect and reset scan chains for all modules (reset

address, RSA).

Additionally, in Pause-DR and Pause-IR TAP states, a third global address (test-synchronization address, TSA)

can be invoked to allow simultaneous TAP-state changes and multicast scan-in operations to selected modules.

This is especially useful in the former case, for allowing selected modules to be moved simultaneously to the

Run-Test-Idle TAP state for module-level or module-to-module built-in self-test (BIST) functions, which operate

synchronously to TCK in that TAP state, and in the latter case, for scanning common test setup/data into multiple

like modules.

.\. *5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

architecture

Conceptually, the ASP can be viewed as a bank of switches that can connect or isolate a module-level TAP

to/from a higher-level (e.g., module-to-module) TAP. This is shown in Figure 2. The state of the switches (open

versus closed) is based on shadow protocols, which are received on PTDI and are synchronous to PTCK.

The simple architecture of the ASP allows the system designer to overcome the limitations of IEEE Std 1149.1

ring

and

star

configurations. Ring configurations (in which each module’s TDO is chained to the next module’s

TDI) are of limited use in backplane environments, since removal of a module breaks the scan chain and

prevents test of the remainder of the system. Star configurations (in which all module TDOs and TDIs are

connected in parallel) are suited to the backplane environment, but, since each module must receive its own

TMS, are costly in terms of backplane routing channels. By comparison, use of the ASP allows all five IEEE

Std 1149.1 signals to be routed in multidrop fashion.

Control

CON

STDI

STCK

STMS

STDO

STRST

PTDO

PTCK

PTMS

PTDI

PTRST

BYP

A9–A0

From Multidrop,

Module-to-Module

Test Access Port

To Module-Level

Test Access Port

Figure 2. ASP Conceptual Model

As shown in the functional block diagram, the ASP comprises three major logic blocks. Blocks for

shadow-protocol receive and shadow-protocol transmit are responsible for receipt of select protocol and

transmission of acknowledge protocol, respectively. The connect-control block is responsible for TAP-state

monitor and address matching.

Some additional logic is illustrated outside of these major blocks. This additional logic is responsible for

controlling the activity of the ASP outputs based on the shadow-protocol result and/or protocol bypass [as

selected by an active (low) BYP input].

L b TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

shadow protocol

Addressing of an ASP in system is accomplished by shadow protocols, which are received at PTDI

synchronously to PTCK. Shadow protocols can occur only in the following stable TAP states: Test-Logic-Reset,

Run-Test/Idle, Pause-DR, and Pause-IR. Shadow protocols never occur in Shift-DR or Shift-IR states to prevent

contention on the signal bus to which PTDO is wired. Additionally, the ASP PTMS must be held at a constant

low or high level throughout a shadow protocol. If TAP-state changes occur in the midst of a shadow protocol,

the shadow protocol is aborted and the select-protocol state machine returns to its initial state.

The shadow protocol is based on a serial bit-pair signaling scheme in which two bit-pair combinations (data one,

data zero) are used to represent address data and the other two bit-pair combinations (select, idle) are used

for framing – that is, to indicate where address data begins and ends.

These bit pairs are received serially at PTDI (or transmitted serially at PTDO) synchronously to PTCK as follows:

– The idle bit pair (I) is represented as two consecutive high signals.

– The select bit pair (S) is represented as two consecutive low signals.

– The data-one bit pair (D) is represented as a low signal followed by a high signal.

– The data-zero bit pair (D) is represented as a high signal followed by a low signal.

PTCK

PTDI

PTDO

First Bit of Pair Is Transmitted

First Bit of Pair Is Received

Second Bit of Pair Is Transmitted

Second Bit of Pair Is Received

Figure 3. Bit-Pair Timing (Data Zero Shown)

A complete shadow protocol is composed of the receipt of a select protocol followed, if applicable, by the

transmission of an acknowledge protocol (which is issued from PTDO only if the received address matches that

at the A9–A0 inputs). Both of these subprotocols are composed of ten data bit pairs framed at the beginning

by idle and select bit pairs and at the end by select and idle bit pairs. This is represented in an abbreviated

fashion as follows: ISDDDDDDDDDDSI. Figure 4 shows a complete shadow protocol (the symbol T is used to

represent a high-impedance condition on the associated signal line – since the high-impedance state at PTDI

is logically high due to pullup, it maps onto the idle bit pair).

T I S D D D D D D D D D D S I T T T T T T T T T T T T T T T

T T T T T T T T T T T T T T T I S D D D D D D D D D D S I T

Received at PTDI

Transmitted at PTDO

Primary Tap Is Inactive

Select Protocol Begins

Select Protocol Ends

Acknowledge Protocol Begins

Acknowledge Protocol Ends

Primary-to-Secondary Connect,

Scan Operations Can Be Initiated

LSB MSB LSB MSB

Figure 4. Complete Shadow Protocol

IS(D}S(DH JsmStSH *5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

select protocol

The select protocol is the ASP’s means of receiving (at PTDI) address information from an IEEE Std 1149.1 bus

master. It follows the ISDDDDDDDDDDSI sequence described previously. A 10-bit address value is decoded

from the received data-one and/or data-zero bit pairs. These bit pairs are interpreted in least-significant-bit-first

order (that is, the first data bit pair received is considered to correspond to A0).

acknowledge protocol

Following the receipt of a complete select-protocol sequence, the protocol result provisionally is set to NO

MATCH and the connect status set to OFF. The received address is then compared to that at the ASP address

inputs (A9–A0). If these address values match, the ASP immediately (with no delay) responds with an

acknowledge protocol transmitted from PTDO. This protocol follows the ISDDDDDDDDDDSI sequence

described previously. The transmitted address represents the address of the selected ASP which, by definition,

is the same address the ASP received in the select protocol. The 10-bit address value is encoded into data-one

and/or data-zero bit pairs. The bit pairs are to be interpreted in least-significant-bit-first order (that is, the first

data bit pair transmitted is to be considered to correspond to A0). If the received address does not match that

at the A9–A0 inputs, no acknowledge protocol is transmitted and the shadow protocol is considered complete.

protocol errors

Protocol errors occur when bit pairs are received out of sequence. Some of these sequencing errors can be

tolerated and produce protocol result SOFT ERROR – no specific action occurs as a result. Other errors

represent cases where the addressing information could be incorrectly received and produce protocol result

HARD ERROR – these are characterized by sequences in which at least one bit of address data has been

properly transmitted, followed by a sequencing error; when protocol result HARD ERROR occurs, any

connection to an ASP is dissolved.

Table 1 lists the bit-pair sequences that produce protocol results SOFT ERROR and HARD ERROR. A hard

error also results when the primary TAP state changes during select protocol following the proper transmission

of at least one bit of address data. Figures 16 and 17 show shadow-protocol timing in case of protocol result

HARD ERROR while Figure 18 shows shadow-protocol timing in case of protocol result SOFT ERROR.

Table 1. Shadow-Protocol Errors†

SOFT ERROR HARD ERROR

I(D)I

I(D)(S)I

I(D)(S)(D)I IS(D)I

IS(D)S(D)I

I(S)I

IS(D)S(D)I

)S(S)

IS(S)(D)I

IS(D)S(S)I

IS(S)(D)(S)I

†A bit-pair token in parentheses

represents one or more instances.

long address

Receipt of an address longer than ten bits produces protocol result HARD ERROR and the ASP assumes OFF

status. The sole exceptions are when all data ones are received or all data zeros are received. In these special

cases, the global addresses represented by these bit sequences are observed and appropriate action taken.

That is, in the case that only data ones (ten or more) are received, the shadow-protocol result is TEST

SYNCHRONIZATION (if the primary TAP state is Pause-DR or Pause-IR), and in the case that only data zeros

(ten or more) are received, the shadow-protocol result is RESET (see test-synchronization address and

reset address).

< capture-dr="" ptms="L" shift-dr="" ptms="L" ptms="H" ptms="H" exin-dr="" exili-ir="" ptms="L" ptms="L" hausa="" pause-ir="" ptms="L" ptms="H" ptms="PTMS" :="" l="" ptms="L" ‘="">< exil2-dr="" exilz-ir="" ptms="H" ptms="H" 7="" update-dr=""> < update-ir="" ptms="H" ptms="L" ptms="H" ptms="L" i="" *9="" texas="" instruments="" 9057="" omca="" aox="" $55303="" -="" dallas="" iexas="" 752s5="">

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

short address

In all cases, receipt of an address shorter than ten bits produces protocol result HARD ERROR and the ASP

assumes OFF status.

connect control

The connect-control block monitors the primary TAP state to enable receipt/acknowledge of shadow protocols

in appropriate states (namely, the stable, non-Shift TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-DR,

and Pause-IR). Upon receipt of a valid shadow protocol, this block performs the address matching required to

compute the shadow-protocol result.

TAP-state monitor

The TAP-state monitor is a synchronous finite-state machine that monitors the primary TAP state. The state

diagram is shown in Figure 5 and mirrors that specified by IEEE Std 1149.1-1990. The TAP-state monitor

proceeds through its states based on the level of PTMS at the rising edge of PTCK. Each state is described both

in terms of its significance for ASP devices and for connected IEEE Std 1149.1-compliant devices (called

targets). However, the monitor state (primary TAP) can be different from that of disconnected scan chains

(secondary TAP).

Test-Logic-Reset

Run-Test/Idle Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = LPTMS = H

PTMS = L

PTMS = H

PTMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

PTMS = L

PTMS = H

PTMS = L

PTMS = H

PTMS = LPTMS = H

PTMS = L

Exit2-IR

PTMS = L

PTMS = H PTMS = H

PTMS = H

PTMS = L

PTMS =HPTMS = H

PTMS = H

PTMS = L

PTMS = H

PTMS = L

Figure 5. TAP-Monitor State Diagram

*5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Test-Logic-Reset

The ASP TAP-state monitor powers up in the Test-Logic-Reset state. Alternatively, the ASP can be forced

asynchronously to this state by assertion of its PTRST input. In the stable Test-Logic-Reset state, the ASP is

enabled to receive and respond to shadow protocols. The ASP does not recognize the TSA in this state.

For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal

logic function of the device is performed. The instruction register is reset to an opcode that selects the optional

IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their

power-up values.

Run-Test/Idle

In the stable Run-Test/Idle state, the ASP is enabled to receive and respond to shadow protocols. The ASP does

not recognize the TSA in this state.

For a target device, Run-Test/Idle is a stable state in which the test logic can be actively running a test or can

be idle.

Select-DR-Scan, Select-lR-Scan

The ASP is not enabled to receive and respond to shadow protocols in the Select-DR-Scan and

Select-lR-Scan states.

For a target device, no specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the

TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either

data-register scan or instruction-register scan.

Capture-DR

The ASP is not enabled to receive and respond to shadow protocols in the Capture-DR state.

For a target device in the Capture-DR state, the selected data register can capture a data value as specified

by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the Capture-DR

state is exited.

Shift-DR

The ASP is not enabled to receive and respond to shadow protocols in the Shift-DR state.

For a target device, upon entry to the Shift-DR state, the selected data register is placed in the scan path

between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an

active state. TDO outputs the logic level present in the least-significant bit of the selected data register. While

in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

Exit1-DR, Exit2-DR

The ASP is not enabled to receive and respond to shadow protocols in the Exit1-DR and Exit2-DR states.

For a target device, the Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is

possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the

high-impedance state.

Pause-DR

In the stable Pause-DR state, the ASP is enabled to receive and respond to shadow protocols. Additionally, the

TSA can be recognized in this state.

For target devices, no specific function is performed in the stable Pause-DR state. The Pause-DR state

suspends and resumes data-register scan operations without loss of data.

*9 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Update-DR

The ASP is not enabled to receive and respond to shadow protocols in the Update-DR state.

For a target device, if the current instruction calls for the selected data register to be updated with current data,

such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

The ASP is not enabled to receive and respond to shadow protocols in the Capture-IR state.

For a target device in the Capture-IR state, the instruction register captures its current status value. This capture

operation occurs on the rising edge of TCK, upon which the Capture-IR state is exited.

Shift-IR

The ASP is not enabled to receive and respond to shadow protocols in the Shift-IR state.

For a target device, upon entry to the Shift-IR state, the instruction register is placed in the scan path between

TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state.

TDO outputs the logic level present in the least-significant bit of the instruction register. While in the stable

Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle.

Exit1-IR, Exit2-IR

The ASP is not enabled to receive and respond to shadow protocols in the Exit1-IR and Exit2-IR states.

For target devices, the Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan.

It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction

high-impedance state.

Pause-IR

In the stable Pause-IR state, the ASP is enabled to receive and respond to shadow protocols. Additionally, the

TSA can be recognized in this state.

For target devices, no specific function is performed in the stable Pause-IR state, in which the TAP controller

can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without

loss of data.

Update-IR

The ASP is not enabled to receive and respond to shadow protocols in the Update-IR state.

For target devices, the current instruction is updated and takes effect on the falling edge of TCK, following entry

to the Update-IR state.

*5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

address matching

Connect status of the ASP is computed by a match of the address received in the last valid shadow protocol

against that at the address inputs (A9–A0) as well as against the three dedicated addresses that are internal

to the ASP (DSA, RSA, and TSA). The address map is shown in Table 2.

Table 2. Address Map

ADDRESS NAME BINARY

CODE HEX

CODE SHADOW-PROTOCOL

RESULT

RESULTANT

PRIMARY-TO-SECONDARY

CONNECT STATUS

Reset Address (RSA) 0000000000 000 RESET RESET

Matching Address A9–A0 A9–A0 MATCH ON

Disconnect Address (DSA) 1111111110 3FE DISCONNECT OFF

Test Synchronization Address (TSA) 1111111111 3FF TEST SYNCHRONIZATION MULTICAST

All Other Addresses All others All others NO MATCH OFF

If the shadow-protocol address matches the address inputs (A9–A0), then the ASP responds by transmitting

an acknowledge protocol. Following the complete transmission of the acknowledge protocol, the ASP assumes

ON status (in which PTDI, PTDO, and PTMS are connected to STDO, STDI, and STMS, respectively). The ON

status allows the scan chain associated with the ASP’s secondary TAP to be controlled from the multidrop

primary TAP as if it were directly wired as such. Figures 6 and 7 show the shadow-protocol timing for MATCH

result when the prior ASP connect status is ON and OFF, respectively.

If the shadow-protocol address does not match the address inputs (A9–A0), then (unless the address is one

of the three dedicated global addresses described below) the ASP responds immediately by assuming the OFF

status (in which PTDO and STDO are high impedance and STMS is held at its last level). This has the effect

of deselecting the scan chain associated with the ASP secondary TAP, but leaves the TAP state of the scan chain

unchanged. No acknowledge protocol is sent. Figures 8 and 9 show the shadow-protocol timing for NO MATCH

result when the prior ASP connect status is ON and OFF, respectively.

disconnect address

The disconnect address (DSA) is one of the three internally dedicated addresses that are recognized globally.

When an ASP receives the DSA, it immediately responds by assuming the OFF status (in which PTDO and

STDO are high impedance and STMS is held at its last level). This has the effect of deselecting the scan chain

associated with the ASP secondary TAP, but leaves the TAP state of the scan chain unchanged. No

acknowledge protocol is sent. Figures 10 and 11 show the shadow-protocol timing for DISCONNECT result

when the prior ASP connect status is ON and OFF, respectively.

The same result occurs when a nonmatching address is received. No specific action to disconnect an ASP is

required, as a given ASP is disconnected by the address that connects another. The dedicated DSA ensures

that at least one address is available for the purpose of disconnecting all receiving ASPs. It is especially useful

when the currently selected scan chain is in a different TAP state than that to be selected. In such a case, the

DSA is used to leave the former scan chain in the proper state, after which the primary TAP state is moved to

that needed to select the latter scan chain.

reset address

The reset address (RSA) is one of the three internally dedicated addresses that are recognized globally. When

an ASP receives the RSA, it immediately responds by assuming the RESET status (in which PTDO and STDO

are high impedance and STMS is forced to the high level). This has the effect of deselecting and resetting (to

Test-Logic-Reset state) the scan chain associated with the ASP secondary TAP. No acknowledge protocol is

sent. Figures 12 and 13 show the shadow-protocol timing for RESET result when the prior ASP connect status

is ON and OFF, respectively.

*9 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

test synchronization address

The test synchronization address (TSA) is one of the three internally dedicated addresses that are recognized

globally. When an ASP receives the TSA while its secondary TAP state is Pause-DR or Pause-IR, it immediately

responds by assuming the MULTICAST status (in which PTDI and PTMS are connected to STDO and STMS

respectively, while PTDO is high impedance). No acknowledge protocol is sent. The TSA is valid only when the

TAP state of both primary and secondary is Pause-DR or Pause-IR. If the TSA is received when the TAP state

of either primary or secondary is Test-Logic-Reset or Run-Test-Idle, the shadow-protocol result is considered

to be DISCONNECT. Figures 14 and 15 show the shadow-protocol timing for TEST SYNCHRONIZATION result

when the prior ASP connect status is ON and OFF, respectively.

The TSA allows simultaneous operation of the scan chains of all selected ASPs, either for global TAP-state

movement or for scan input of common serial test data via PTDI. This is especially useful in the former case,

to simultaneously move such scan chains into the Run-Test/Idle state in which module-level or

module-to-module BIST operations can operate synchronous to TCK in that TAP state, and in the later case,

to scan common test setup/data into multiple like modules.

protocol bypass

Protocol bypass is selected by a low BYP input. This protocol-bypass mode forces the ASP into BYP status

(primary TAP signals are connected to secondary TAP signals) regardless of previous shadow-protocol results.

The CON output is made active (low). Receipt of shadow protocols is disabled.

When BYP is taken low, the primary TAP serial data signals (PTDI, PTDO) are immediately (asynchronously

to PTCK) connected to their respective secondary TAP signals (STDO, STDI). The primary TAP mode-select

signal (PTMS) is also connected to its respective secondary TAP signal (STMS) unless PTRST is low, in which

case STMS remains high until PTRST is released. Also, the shadow-protocol-receive block is reset to its

power-up state and is held in this state such that select protocols appearing at the primary TAP are ignored.

When the BYP input is released (taken high), the ASP immediately (asynchronously to PTCK) resumes the

connect status selected by the last valid shadow protocol. The shadow-protocol-receive block is again enabled

to respond to select protocols.

Figures 19 and 20 show protocol-bypass timing when the ASP connect status before BYP active is ON and

OFF, respectively.

asynchronous reset

While the PTRST input is always buffered directly to the STRST output, it also serves as an asynchronous reset

for the ASP. Given that BYP is high, when PTRST goes low, the ASP immediately assumes TRST status, in

which CON is high and PTDO and STDO are at high impedance. Otherwise, if BYP is low, the ASP assumes

BYP/TRST status. In either case, STMS is set high so that connected IEEE Std 1149.1-compliant devices can

be synchronously driven to their Test-Logic-Reset states. While PTRST is low, receipt of shadow protocols

is disabled.

Figures 21 and 22 show asynchronous reset timing when the ASP connect status before PTRST active is ON

and OFF, respectively. Figure 23 shows asynchronous reset timing when BYP is low.

connect indicator

The CON output indicates secondary-scan-port activity (STDO, STMS active) regardless of whether such

activity is achieved via protocol bypass or shadow protocol. If the BYP input is low, the CON output is low.

Otherwise, if the BYP input is high, the CON output is low if the result of the last valid shadow protocol is MATCH

or TEST SYNCHRONIZATION. In all other cases, and while acknowledge protocol is in progress, the CON

output is high.

I AQ—AD Kon'l Care D l l BVF 1 l I I I I I I I I I I I I I I I I I I I I I I I I I PTDI Idle $elee‘l Aup Asp ‘éelec‘l Idle PTMS l l PTRST 1 l I STDI Don lKare l l l I —c0N l l l l l 1 1 I l l l l I I I I I I I I I I I I ‘ mo 9%?) =¥TI§IW Idle \Selecl yAOp ' \ y RA s‘rDo M A9 I STMS STMS = PTMS STRST Select Protocol Acknowledge T The lnslantaneous value al PTDI dunng pmmcol acknowledge .5 "don’t care" as long as me cum selecl protocol or produce prolocol result HARD ERROR *5 TEXAS INSTRUMENTS POST OFFICE EOX $55303 - DALLAS lExAs 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

shadow-protocol timing

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care†

Don’t Care Don’t Care

A0PA9P

PTDO = STDI

STMS = PTMS

A0PA9P

STMS = STMS0

PTCK

STCK

PTMS Don’t Care

STDI

STMS = PTMS

STDO = PTDI

PTDO = STDI

BYP

PTRST

STRST

Select Protocol Acknowledge Protocol ON

†The instantaneous value of PTDI during protocol acknowledge is “don’t care” as long as the cumulative effect does not represent another valid

select protocol or produce protocol result HARD ERROR.

Don’t Care

Idle Select Idle

Idle Select Select Idle

Select

Figure 6. Shadow-Protocol Timing, Protocol Result = MATCH, Prior Connect Status = ON

\ A9—A0 B/on'l Care m < 17="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" \="" \="" \="" \="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ptdi="" idle="" ‘éelee‘\="" aop="" asp="" $elec‘k="" idle="" ptms="" \="" \="" \="" \="" ptrst="" 1="" 1="" \="" \="" \="" \="" stdi="" \bon‘ybsre="" ‘="" ‘="" ‘="" ‘="" ‘="" \="" \="" \="" \="" \="" con="" \="" ‘="" 1="" ‘="" 1="" ‘="" x="" x="" ‘="" x="" w="" x="" x="" \="" \="" \="" ‘="" ,="" ptdo="" %="" idle="" \selecl="" ‘ladp="" ‘="" ‘="" 1*":="" stms="" stms="" :="" stmsu="" \="" \="" strst="" \="" \="" select="" protocol="" \="" acknowledge="" t="" the="" msmmaneous="" vame="" m="" ptd‘="" dunng="" premcm="" acknaw‘edge="" ‘5="" "don‘t="" care"="" as="" \ang="" as="" me="" cum="" se‘ecl="" pmlocol="" 0r="" produce="" pmmcm="" resun="" hard="" error.="" *9="" texas="" instruments="" 16="" post="" office="" eox="" $55303="" '="" dallas="" iexas="" 75285="">

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care†

Don’t Care Don’t Care

A0PA9P

STMS = STMS0

PTCK

STCK

PTMS Don’t Care

STDI

STMS = PTMS

STDO = PTDI

PTDO = STDI

BYP

PTRST

STRST

Select Protocol Acknowledge Protocol ON

†The instantaneous value of PTDI during protocol acknowledge is “don’t care” as long as the cumulative effect does not represent another valid

select protocol or produce protocol result HARD ERROR.

Don’t Care

Idle Select Select Idle

Figure 7. Shadow-Protocol Timing, Protocol Result = MATCH, Prior Connect Status = OFF

W 115me x x x x x x x x x \ AQ—AO \60n'l Care m < v="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" \="" \="" \="" \="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ptdi="" idle="" ‘éelec‘\="" nmap="" ‘éelec‘k="" idle="" ptms="" pthst="" stdi="" don="" 129mg="" ptdo="" o'ovovow="" v_="" v="" v="" v="" v="" v="" wyyy="" v="" otfofg="" aofofma‘fmfofg="" a="" a="" stck="" \="" \="" stdo="" ‘="" nmap="" ‘="" stms="" stms="PTMS" sthst="" select="" protocol="" *5="" texas="" instruments="" 9057="" omca="" aox="" $55303="" -="" dallas="" iexas="" 752s5="">

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

NMAP

PTDO = STDI

STMS = PTMS STMS = STMS0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol OFF

Don’t Care

Idle Select Select Idle

NMAP

Don’t Care

Don’t Care Don’t Care

Figure 8. Shadow-Protocol Timing, Protocol Result = NO MATCH, Prior Connect Status = ON

WWIWWW \ \ AS—AD Bf:n'l%are Do“ Kare \ x x x ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ PTDI Idle #9»? NN’AP J‘seleﬁ Idle Bf". 96m PTMS ﬁgméare PTRST STDI BSn 1X5"; PTDO STDO STMS STMS = STMSu Salem Plolocol \ \ STRST \ \ \ OFF *9 TEXAS INSTRUMENTS 18 POST OFFICE EOX $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

NMAP

STMS = STMS0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol OFF

Don’t Care

Idle Select Select Idle

Don’t Care

Don’t Care Don’t Care

Figure 9. Shadow-Protocol Timing, Protocol Result = NO MATCH, Prior Connect Status = OFF

AQ—AD Eon'l Cale \ x x \ BVF 1 1 x x \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ PTDI Idle {selec‘k DSAp $elec‘k Idle PTMS PTRST STDI Kora/Care PTDO “w 7 v v v v vo'ovo A Aofommfofg A A \ \ STDO ‘ DSAp ‘ STMS STMS : PTMS STRST Selecl Prolocol *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

DSAP

PTDO = STDI

STMS = PTMS STMS = STMS0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol OFF

Don’t Care

Idle Select Select Idle

DSAP

Don’t Care

Figure 10. Shadow-Protocol Timing, Protocol Result = DISCONNECT, Prior Connect Status = ON

AS—AD Kon'l Care ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ x x , , x \ PTDI Idle ‘éelec‘k DSA $9.24 Idle PTMS PTRST STDI \Son'VCare PTDO STDO STMS STMS = STMSg \ \ STRST \ \ Select Protocol \ *9 TEXAS INSTRUMENTS 20 POST OFFICE EOX $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

DSAP

STMS = STMS0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol OFF

Don’t Care

Idle Select Select Idle

Don’t Care

Figure 11. Shadow-Protocol Timing, Protocol Result = DISCONNECT, Prior Connect Status = OFF

AQ—AD \Eon'l Care ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ x x I , x \ PTDI Idle {selec‘k RSLAP ‘éeleé Idle s‘rm \ﬁonYegre n z PTDO STCK STDO STMS STMS > PTMS ’ STRST Selecl Prolocol *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

RSAP

PTDO = STDI

STMS = PTMS

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol RESET

Don’t Care

Idle Select Select Idle

RSAP

Don’t Care

Figure 12. Shadow-Protocol Timing, Protocol Result = RESET, Prior Connect Status = ON

AQ—AD Kon'l Cale ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ PTDI Idle $elec‘k RSAp {Salt-32“ Idle PTMS PTRST STDI \Son'E/Care n z PTDO \ 5700 1 \ \ sms sms STMSg I STRST Selecl Plolocol *9 TEXAS INSTRUMENTS 22 POST OFFICE EOX $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

RSAP

STMS = STMS0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol RESET

Don’t Care

Idle Select Select Idle

Don’t Care

Figure 13. Shadow-Protocol Timing, Protocol Result = RESET, Prior Connect Status = OFF

AQ—AD B/on't Care ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ PTDI Idle $elec‘k TSAP {selec‘ﬁ Idle PTMS PTRST STDI b/on'ﬁare vvvvvvv - - AAAAAAAAO \ \ STRST \ \ \ Select Protocol *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

TSAP

STMS = PTMS

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol MULTICAST

Don’t Care

Idle Select Select Idle

Don’t Care

STMS = PTMS

STDO = PTDI

PTDO = STDI

TSAP

Figure 14. Shadow-Protocol Timing,

Protocol Result = TEST SYNCHRONIZATION, Prior Connect Status = ON

WWW—WWW A9—A0 DOINE/are BVP ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ \ \ \ \ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ PTDI Idle {selec‘k TSAp ‘éelec‘k Idle PTMS \ W } x \ STDI Dom Kare PTDO \ \ \ STRST \ \ \ Select Protocol *9 TEXAS INSTRUMENTS 24 POST OFFICE EOX $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

TSAP

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol MULTICAST

Don’t Care

Idle Select Select Idle

Don’t Care

STMS = PTMS

STDO = PTDI

STMS = STMS0

Figure 15. Shadow-Protocol Timing,

Protocol Result = TEST SYNCHRONIZATION, Prior Connect Status = OFF

SN54LVT8996, SN74LVT8996 ADDRESSABLE SCAN PORTS 9.1 gJTAGkTAP TRANSCEIVERS 556 5A7 APR 19977 HEWSED DECEMBEH1999 1 1 1 1 1 1 1 1 1 1 1 AQ—AO \Eon'l Care 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 — 1 1 1 1 1 1 1 1 1 1 1 BVP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PTDI Idle éelec1 nap an éeIeA Idle ¥0n¥8§re 1 1 1 1 1 1 1 1 PTMS 'ﬁomére 1 1 1 1 1 1 1 1 1 — 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 STDI \ﬁonYéz/ue 1 1 1 1 3220292 2 2 2 2 122.29%: STRST 1 STMS sms = PTMS @ STMS 1 1 1 1 Select Protocol (aborted) NOTE A. The posman cl PTMS shown *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

PTDO = STDI

STMS = PTMS STMS = STMS0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol

(aborted) OFF

Don’t Care

Idle Select Select IdleD0PDnP

D0PDnP

Don’t Care

NOTE A: The position of PTMS shown in this figure is only one of many that would produce protocol result HARD ERROR.

Figure 16. Shadow-Protocol Timing,

Protocol Result = HARD ERROR (PTMS Change During Select Protocol), Prior Connect Status = ON

l AS—AD Don [Kare l l l l l l l l l l l l l l l l l l l l l l l l l l l l l PTDI Idle ‘éelec‘l ADPLAQP {selecl Idle PTMS PTRST l l l l l l STDI \60n'l Care m ioitizimtizi STCK l l l l 5100 ‘ A0}: A9 l 1 l l l STMS STMS = PTMS STRST Select Protocol Acknowledge Protocol (aboned) NOTE A The posmon m PTMS shown m «ms «we ls only one m many that would produce or *9 TEXAS INSTRUMENTS 26 POST OFFICE EOX $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

Don’t Care Don’t Care

A0PA9P

PTDO = STDI

STMS = PTMS

A0PA9P

STMS = STMS0

PTCK

STCK

STDI

BYP

PTRST

STRST

Select Protocol Acknowledge Protocol

(aborted) OFF

Don’t Care

Idle Select Select Idle

PTMS Don’t Care

NOTE A: The position of PTMS shown in this figure is only one of many that would produce protocol result HARD ERROR.

Idle

Figure 17. Shadow-Protocol Timing,

Protocol Result = HARD ERROR (PTMS Change During Acknowledge Protocol),

Prior Connect Status = ON

\SonW/Care WWW —\ VW STDO STRST Select Prolocol \ \ \ \ \ (aborted) \ NOTE A. We sequence m PTD‘ has shown m «me ﬁgure ‘5 WW one m many that wau‘d produ *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

Don’t Care

STMS = PTMS

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Select Protocol

(aborted) ON

Don’t Care

Idle Select Select IdleSelect

Don’t Care

PTDO = STDI

STMS = PTMS

STDO = PTDI

NOTE A: The sequence of PTDI bits shown in this figure is only one of many that would produce protocol result SOFT ERROR.

Figure 18. Shadow-Protocol Timing,

Protocol Result = SOFT ERROR, Prior Connect Status = ON

[Ll—1mm mm A9—A0 ﬂank/Care W 1 1 PTDI \SonYCare 1 1 1 1 PTMS Em Care 1 1 PTRST 1 1 1 1 STDI Kora/Care 1 1 — 1 1 1 1 PTDO 1986 = ¥rBT 1 1 STCK , / 1 1 ' Wﬁﬁw 1 1 1 1 sms ENE: pﬁé 1 1 1 1 STRST 1 1 ON 1 an: 1 0 iii TEXAS INSTRUMENTS 28 9057 omcz aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

protocol-bypass timing

PTDI

PTDO

CON

STDO

STMS

A9–A0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Don’t Care

ON BYP

STMS = PTMS

STDO = PTDI

PTDO = STDI

Figure 19. Protocol-Bypass Timing, Prior Connect Status = ON

AQ—AO \Som Care avp \ \ PTDI Kern Care \ \ \ \ PTMS \6un'VCare \ \ \ \ \ \ \ \ STDI \Sun't Care 0'0'6'OVO'OV'O'OW'OVVVVV'O'O' $‘o’922 ’ ” ' ’o’ofofofofofo’o’ A- OAOAAAAAAAAA A PTDO 5m" ’on 9A “ugfof \ x x x \ \ OFF \ avp \ o {P TEXAS INSTRUMENTS 9057 omcz aox $55303 - DALLAS IEXAS 752s5

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

STMS = STMS0

OFF

Don’t Care

STMS = STMS0

Don’t Care

OFF BYP

STMS = PTMS

STDO = PTDI

PTDO = STDI

PTDI

PTDO

CON

STDO

STMS

A9–A0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Figure 20. Protocol-Bypass Timing, Prior Connect Status = OFF

WWW A9.“ Kan-96m W PTDI B/on'Péare PTMS B/on'héare PTRST ‘ ‘ STDI B/on'Péare STDO S '33:; El 1‘ \ sms sﬁn¥=$ﬁfsz STHST —‘\—/‘— 0N \ TRST \ RE *9 TEXAS INSTRUMENTS 30 POST OFFICE on $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

asynchronous reset timing

PTDI

PTDO

CON

STDO

STMS

A9–A0

PTDO = STDI

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

Don’t Care

STDO = PTDI

STMS = PTMS

TRST RESET

Figure 21. Asynchronous Reset Timing, Prior Connect Status = ON

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

OFF

Don’t Care

TRST

STMS = STMS0

RESET

Figure 22. Asynchronous Reset Timing, Prior Connect Status = OFF

WWW—MUM AQ—AD Kern Care W PTDI Kern Care PTMS \Sun'E/Care PTRST ‘ ‘ STDI \Sun'YCare ‘ ‘ \ ‘ con 1 1 ‘ ‘ ‘ \ PTDO MB?) = é/ﬁfl ‘ ‘ ‘ STCK ‘ \ \ smo s¥Do = KTKI m memgj‘ W «In: BVP \ BVP/TRST *9 TEXAS INSTRUMENTS 32 POST OFFICE on $55303 ' DALLAS IEXAS 75285

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PTDI

PTDO

CON

STDO

STMS

A9–A0

PTCK

STCK

PTMS

STDI

BYP

PTRST

STRST

BYP

Don’t Care

BYP/TRST

STMS = PTMS STMS = PTMS

BYP

PTDO = STDI

STDO = PTDI

Figure 23. Asynchronous Reset Timing, BYP = L

*5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, VO

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54LVT8996 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVT8996 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, IO (see Note 2): SN54LVT8996 48 mA. . . . . . . . . . . . . . . . . . . . . . . .

SN74LVT8996 64 mA. . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 3): DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and VO > VCC.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

SN54LVT8996 SN74LVT8996

UNIT

MIN MAX MIN MAX

UNIT

VCC Supply voltage 2.7 3.6 2.7 3.6 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VIInput voltage 5.5 5.5 V

IOH High-level output current –24 –32 mA

IOL Low-level output current 48 64 mA

∆t/∆vInput transition rise or fall rate 10 10 ns/V

∆t/∆VCC Power-up ramp rate 200 200 µs/V

TAOperating free-air temperature –55 125 –40 85 °C

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

PARAMETER TEST CONDITIONS *9 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN54LVT8996 SN74LVT8996

UNIT

PARAMETER

TEST

CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

VIK VCC = 2.7 V, II = –18 mA –1.2 –1.2 V

VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2

VOH

VCC = 2.7 V, IOH = –8 mA 2.4 2.4

VCC =3V

IOH = –24 mA 2

CC =

IOH = –32 mA 2

VCC =27V

IOL = 100 µA 0.2 0.2

CC =

IOL = 24 mA 0.5 0.5

VOL

IOL = 16 mA 0.4 0.4

VCC =3V

IOL = 32 mA 0.5 0.5

CC =

IOL = 48 mA 0.55

IOL = 64 mA 0.55

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

µA

IPTCK VCC = 3.6 V, VI = VCC or GND ±1±1µ

IIH

PTDI, PTMS, PTRST

VCC =36V

VI=V

1 1

µA

IH A9–A0, BYP, STDI

CC =

I =

CC 1 1 µ

IIL

PTDI, PTMS, PTRST

VCC =36V

VI= GND

–8 –30 –8 –30

µA

IL A9–A0, BYP, STDI

CC =

I =

GND

–25 –100 –25 –100 µ

Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

IOZH PTDO, STDO VCC = 3.6 V, VO = 3 V 5 5 µA

IOZL PTDO, STDO VCC = 3.6 V, VO = 0.5 V –5 –5 µA

IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, ±100* ±100 µA

IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V ±100* ±100 µA

OFF, STCK = H,

STMS = H 2 2

ICC

VCC = 3.6 V,

VI = VCC or

ON, PTDO = L,

STCK = L,

STDO = L, STMS = L 20 20

ICC

GND,

IO = 0 ON, PTDO = H,

STCK = H,

STDO = H,

STMS = H

7 7

TRST, STCK = L 10 10

∆ICC‡VCC = 3 V to 3.6 V,

One input at VCC – 0.6 V,

Other inputs at VCC or GND 0.2 0.2 mA

CiVI = 3 V or 0 3.5 3.5 pF

CoVO = 3 V or 0 6.5 6.5 pF

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

†All typical values are at VCC = 3.3 V, TA = 25°C.

‡This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

C(nck vrequencu Pmse d raunn Ser 1.) me HDld lime {P TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 24)

SN54LVT8996 SN74LVT8996

UNIT

MIN MAX MIN MAX

UNIT

flk

Clock frequency

PTCK

VCC = 2.7 V 20 20

MHz

clock

Clock

freq

enc

PTCK

VCC = 3.3 V ±0.3V 25 25

BYP low†8 8

Pulse duration

PTCK high 20 20

lse

ration

PTCK low 12 12

PTRST low 9 9

A9–A0 before PTCK↓‡10.2 10.2

Setu

time

PTDI before PTCK↑10.1 10.1

Set

time

PTMS before BYP↑†4 4

PTMS before PTCK↑10 10

A9–A0 after PTCK↓‡4 4

Hold time

PTDI after PTCK↑4 4

Hold

time

PTMS after BYP↑†4 4

PTMS after PTCK↑4 4

†In normal application of the ASP, such timing requirements with respect to BYP are met implicitly and, therefore, need not be considered.

‡These requirements apply only in the case in which the address inputs are changed during a shadow protocol. For normal application of the ASP,

it is recommended that the address inputs remain static throughout any shadow protocols. In such cases, the timing of address inputs relative

to PTCK need not be considered.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

PTD1 PTMS PTRST PTRSTJ STD1 *9 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 24)

SN54LVT8996

PARAMETER FROM

(INPUT) TO

(OUTPUT) VCC = 3.3 V

±0.3 V VCC = 2.7 V UNIT

MIN MAX MIN MAX

fmax PTCK 25 20 MHz

tPLH BYP↑

CON

1 8.7 1 10

tPHL BYP↓

CON

1 10 1 11.6

tPLH

BYP↓

STMS

2.5 12.6 2.5 15.4

tPHL

BYP↓

STMS

2.5 12.1 2.5 13.9

tPLH

PTCK

STCK

1 10.2 1 11.8

tPHL

PTCK

STCK

1 10.5 1 12.2

tPLH

PTCK↓

CON

3.5 22 3.5 26.4

tPHL

PTCK↓

CON

3.5 24.6 3.5 28.8

tPLH PTCK

↓

PTDO

3 15.5 3 18.3

tPHL (shadow-protocol acknowledge)

PTDO

3 15.7 3 18.4

tPLH†PTCK

↓

STMS

5.5 20.1 5.5 25.1

tPHL†(connect)

STMS

5.5 20.3 5.5 24.2

tPLH

PTDI

STDO

1 8.8 1 10.3

tPHL

PTDI

STDO

1 9 1 10.6

tPLH

PTMS

STMS

1 8.9 1 10.3

tPHL

PTMS

STMS

1 9.1 1 10.6

tPLH

PTRST

STRST

1 8.7 1 10.2

tPHL

PTRST

STRST

1 9 1 10.5

tPLH

PTRST↓

CON 3.5 25.9 3.5 31.1

PLH

PTRST↓

STMS 2.5 14.1 2.5 18.3

tPLH

STDI

PTDO

1 7.3 1 8.5

tPHL

STDI

PTDO

1 7.9 1 9.3

†The transitions at STMS are possible only when a shadow-protocol select is issued while STMS is held (in the OFF status) at a level that differs

from that at PTMS. Such operation is not recommended since state synchronization of the primary TAP to secondary TAP cannot be ensured.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

BYP 7 W7 PTCKt FTCKt PTRST ). PTRST ). {P TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued) (see Figure 24)

SN54LVT8996

PARAMETER FROM

(INPUT) TO

(OUTPUT) VCC = 3.3 V

±0.3 V VCC = 2.7 V UNIT

MIN MAX MIN MAX

tPZH†

BYP↓

PTDO

1.5 9.5 1.5 11.6

tPZL

BYP↓

PTDO

1.5 10.7 1.5 12.7

tPZH‡

BYP↓

STDO

1.5 8.6 1.5 10.2

tPZL

BYP↓

STDO

1.5 9.7 1.5 11.5

tPZH†PTCK↓PTDO 4 15.3 4 18.2 ns

tPZH‡PTCK↓STDO 4 16.6 4 19.6 ns

tPZL PTCK↓STDO 4 17.3 4 20.5 ns

tPHZ†

BYP↑

PTDO

1.5 8.6 1.5 10.3

tPLZ

BYP↑

PTDO

1.5 8.2 1.5 7

tPHZ‡

BYP↑

STDO

1.5 7.6 10.4

tPLZ

BYP↑

STDO

1.5 7.4 1.5 7.9

tPHZ†

PTCK↓

PTDO

3 15 3 18.1

tPLZ

PTCK↓

PTDO

3 14.4 3 16.3

tPHZ‡

PTCK↓

STDO

3.5 16.9 3.5 18.8

tPLZ§

PTCK↓

STDO

3.5 13.8 3.5 16.7

tPHZ†

PTRST↓

PTDO

3.5 19.6 3.5 26.2

tPLZ

PTRST↓

PTDO

3.5 19.3 3.5 21.3

tPHZ‡

PTRST↓

STDO

4.5 19.4 4.5 23.6

tPLZ

PTRST↓

STDO

4.5 20.6 4.5 23.8

†In most applications, the node to which PTDO is connected has a pullup resistor. In such cases, this parameter is not significant.

‡In most applications, the node to which STDO is connected has a pullup resistor. In such cases, this parameter is not significant.

§This parameter applies only in case of protocol result HARD ERROR.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

PTD1 PTMS PTRST PTRSTJ STD1 *9 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 24)

SN74LVT8996

PARAMETER FROM

(INPUT) TO

(OUTPUT) VCC = 3.3 V

±0.3 V VCC = 2.7 V UNIT

MIN MAX MIN MAX

fmax PTCK 25 20 MHz

tPLH BYP↑

CON

1 8.2 1 9.4

tPHL BYP↓

CON

1 9.8 1 11.4

tPLH

BYP↓

STMS

2.5 12 2.5 14.7

tPHL

BYP↓

STMS

2.5 11.7 2.5 13.4

tPLH

PTCK

STCK

1 9.6 1 11.2

tPHL

PTCK

STCK

1 10 1 11.8

tPLH

PTCK↓

CON

3.5 20.6 3.5 24.8

tPHL

PTCK↓

CON

3.5 23 3.5 27.4

tPLH PTCK

↓

PTDO

3 14.7 3 17.4

tPHL (shadow-protocol acknowledge)

PTDO

3 15 3 17.7

tPLH†PTCK

↓

STMS

5.5 19.9 5.5 23.9

tPHL†(connect)

STMS

5.5 19.1 5.5 22.9

tPLH

PTDI

STDO

1 8.3 1 9.9

tPHL

PTDI

STDO

1 8.6 1 10.2

tPLH

PTMS

STMS

1 8.5 1 9.8

tPHL

PTMS

STMS

1 8.8 1 10.3

tPLH

PTRST

STRST

1 8.4 1 10

tPHL

PTRST

STRST

1 9 1 10.5

tPLH

PTRST↓

CON 3.5 23.9 3.5 29

PLH

PTRST↓

STMS 2.5 13.2 2.5 15.7

tPLH

STDI

PTDO

1 6.8 1 8.2

tPHL

STDI

PTDO

1 7.6 1 9

†The transitions at STMS are possible only when a shadow-protocol select is issued while STMS is held (in the OFF status) at a level that differs

from that at PTMS. Such operation is not recommended since state synchronization of the primary TAP to secondary TAP cannot be ensured.

BYP T W7 PTCKt PTCKt W1. PTRST ). *5 TEXAS INSTRUMENTS

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued) (see Figure 24)

SN74LVT8996

PARAMETER FROM

(INPUT) TO

(OUTPUT) VCC = 3.3 V

±0.3 V VCC = 2.7 V UNIT

MIN MAX MIN MAX

tPZH†

BYP↓

PTDO

1.5 9 1.5 10.6

tPZL

BYP↓

PTDO

1.5 10.1 1.5 11.9

tPZH‡

BYP↓

STDO

1.5 8.1 1.5 9.3

tPZL

BYP↓

STDO

1.5 9.2 1.5 10.7

tPZH†PTCK↓PTDO 4 14.5 4 16.8 ns

tPZH‡

PTCK↓

STDO

4 15.8 4 18.4

tPZL

PTCK↓

STDO

4 16.4 4 19.1

tPHZ†

BYP↑

PTDO

1.5 8.3 1.5 9.3

tPLZ

BYP↑

PTDO

1.5 7.7 1.5 8.3

tPHZ‡

BYP↑

STDO

1.5 7.3 1.5 8.5

tPLZ

BYP↑

STDO

1.5 7.4 1.5 7.1

tPHZ†

PTCK↓

PTDO

3 14 3 16.6

tPLZ

PTCK↓

PTDO

3 13.9 3 15.5

tPHZ‡

PTCK↓

STDO

3.5 16.9 3.5 18.3

tPLZ§

PTCK↓

STDO

3.5 13 3.5 15.1

tPHZ†

PTRST↓

PTDO

3.5 18.3 3.5 21.6

tPLZ

PTRST↓

PTDO

3.5 19.3 3.5 19.6

tPHZ‡

PTRST↓

STDO

4.5 18.2 4.5 21.4

tPLZ

PTRST↓

STDO

4.5 20.6 4.5 23.4

†In most applications, the node to which PTDO is connected has a pullup resistor. In such cases, this parameter is not significant.

‡In most applications, the node to which STDO is connected has a pullup resistor. In such cases, this parameter is not significant.

§This parameter applies only in case of protocol result HARD ERROR.

cL = so pF (see Note A) LOAD CIRCUIT ., ., aller \‘ ‘L,, 1} 1‘ x #4 \4—pL m‘wawe *9 TEXAS INSTRUMENTS 40 p057 OFFICE

SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Output

Control

1.5 V

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

6 V

Open

GND

500 Ω

Data Input

Timing Input 1.5 V

2.7 V

0 V

1.5 V 1.5 V

2.7 V

0 V

2.7 V

0 V

1.5 V 1.5 V

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPLH

VOH

VOL

1.5 V 1.5 V

2.7 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

3 V

0 V

1.5 V VOL + 0.3 V

1.5 V VOH – 0.3 V

≈0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: B. CL includes probe and jig capacitance.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.

E. The outputs are measured one at a time with one transition per measurement.

Figure 24. Load Circuit and Voltage Waveforms

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN74LVT8996DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVT8996

SN74LVT8996DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVT8996

SN74LVT8996PW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LX8996

SN74LVT8996PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LX8996

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVT8996 :

•Enhanced Product: SN74LVT8996-EP

NOTE: Qualified Version Definitions:

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74LVT8996DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

SN74LVT8996PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVT8996DWR SOIC DW 24 2000 350.0 350.0 43.0

SN74LVT8996PWR TSSOP PW 24 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

SN74LVT8996DW DW SOIC 24 25 506.98 12.7 4826 6.6

SN74LVT8996PW PW TSSOP 24 60 530 10.2 3600 3.5

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL ﬁg

www.ti.com

PACKAGE OUTLINE

22X 0.65

7.15

24X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

NOTE 4

4.5

4.3

NOTE 3

7.9

7.7

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

12 13

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.000

gmmmﬂgmmﬁj ‘w“““‘+“‘w““‘ Emma—5% R

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

12 13

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

ﬁﬂmmmmmﬁmmmﬁ$% Emma—5%g

www.ti.com

EXAMPLE STENCIL DESIGN

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

12 13

MECHANICAL DATA DW «#:5075220 JLASW‘ SMALL 0U J\L HHHHHHHHHHHH’ﬁ N A AH Hnec' d'vnensm m ‘mmes (mammaers) D'ws'nmng md tu‘ermc'mq per ASME w 5M 1994, B TH: drawmq ‘5 Sn :0 change wan: nohce. a Body dimensmns ca nut inc‘ude mom ﬂcsh ur mum" rut m exceed 0035 (055) D FONS WMHH JEDEC MSiOH vermin" ADV NOTES: {if TEXAS INSTRUMENTS wwvmi .com

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SN54LVT8996, SN74LVT8996 Datasheet by Texas Instruments

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