SN54HC259, SN74HC259 Datasheet by Texas Instruments

U Ordering 2; Technical Design a 3 Support 5 . . quahly documentation development naming I TEXAS INSTRUMENTS m as 11 U‘UdeUQ eeeeeee :2 a1 acne o
SNx4HC259 8-Bit Addressable Latches
1 Features
• Wide operating voltage range of 2 V to 6 V
• High-current inverting outputs drive up to 10
LSTTL loads
• Low power consumption, 80-μA max ICC
• Typical tpd = 14 ns
• ±4-mA output drive at 5 V
• Low input current of 1 μA max
• 8-bit parallel-out storage register performs serial-
to-parallel conversion with storage
• Asynchronous parallel clear
• Active-high decoder
• Enable input simplifies expansion
• Expandable for n-bit applications
• Four distinct functional modes
2 Description
These 8-bit addressable latches are designed
for general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional devices
capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or
demultiplexer with active-high outputs.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74HC259D SOIC (16) 9.90 mm × 3.90 mm
SN74HC259N PDIP (16) 19.31 mm × 6.35 mm
SN74HC259NS SO (16) 6.20 mm × 5.30 mm
SN74HC259PW TSSOP (16) 5.00 mm × 4.40 mm
SN54HC259J CDIP (16) 24.38 mm × 6.92 mm
SNJ54HC259FK LCCC (20) 8.89 mm × 8.45 mm
(1) For all available packages, see the orderable addendum at
the end of the document.
Pin numbers are for the D, J, N, NS, PW, and W packages.
Functional Block Diagram
SN54HC259, SN74HC259
SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements ................................................. 5
5.6 Switching Characteristics ...........................................6
5.7 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2003) to Revision F (March 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references thorughout the document to reflect
modern data sheet standards............................................................................................................................. 1
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022 www.ti.com
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4 Pin Configuration and Functions
J, D, N, NS, or PW Package
16-Pin CDIP, SOIC, PDIP, SO, TSSOP
Top View FK Package
20-Pin LCCC
Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IOContinuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HC259 SN74HC259 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VIH High-level input voltage
VCC = 2 V 1.5 1.5
VVCC = 4.5 V 3.15 3.15
VCC = 6 V 4.2 4.2
VIL Low-level input voltage
VCC = 2 V 0.5 0.5
VVCC = 4.5 V 1.35 1.35
VCC = 6 V 1.8 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
ttInput transition rise/fall time
VCC = 2 V 1000 1000
nsVCC = 4.5 V 500 500
VCC = 6 V 400 400
TAOperating free-air temperature −55 125 −40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
D (SOIC) N (PDIP) NS (SO) PW (TSSOP)
UNIT16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal
resistance(1) 73 67 64 108 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST
CONDITIONS(1) VCC (V) TA = 25°C SN54HC259 SN74HC259 UNIT
MIN TYP MAX MIN MAX MIN MAX
VOH
IOH = −20 μA
2 1.9 1.998 1.9 1.9
V
4.5 4.4 4.499 4.4 4.4
6 5.9 5.999 5.9 5.9
IOH = −4 mA 4.5 3.98 4.3 3.7 3.84
IOH = −5.2 mA 6 5.48 5.8 5.2 5.34
VOL
IOL = 20 μA
2 0.002 0.1 0.1 0.1
V
4.5 0.001 0.1 0.1 0.1
6 0.001 0.1 0.1 0.1
IOL = 4 mA 4.5 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 ±0.1 ±100 ±1000 ±1000 nA
ICC
VI = VCC or 0, IO
= 0 6 8 160 80 μA
Ci2 to 6 3 10 10 10 pF
(1) VI = VIH or VIL, unless otherwise noted.
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC (V) TA = 25°C SN54HC259 SN74HC259 UNIT
MIN MAX MIN MAX MIN MAX
twPulse duration
CLR low
2 80 120 100
ns
4.5 16 24 20
6 14 20 17
G low
2 80 120 100
4.5 16 24 20
6 14 20 17
tsu Setup time, data or address before G↑
2 75 115 95
ns4.5 15 23 19
6 13 20 16
thHold time, data or address after GG↑
2 5 5 5
ns4.5 5 5 5
6 5 5 5
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5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement
Information)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) VCC (V) TA = 25°C SN54HC259 SN74HC259 UNIT
MIN TYP MAX MIN MAX MIN MAX
tPHL CLR Any Q
2 60 150 225 190
ns4.5 18 30 45 38
6 14 26 38 32
tpd
Data Any Q
2 56 130 195 165
ns
4.5 17 26 39 33
6 13 22 33 28
Address Any Q
2 74 200 300 250
4.5 21 40 60 50
6 17 34 51 43
G Any Q
2 66 170 255 215
4.5 20 34 51 43
6 16 29 43 37
ttAny
2 28 75 110 95
ns4.5 8 15 22 19
6 6 13 19 16
5.7 Operating Characteristics
TA = 25℃
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per latch No load 33 pF
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6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
CL(1)
From Output
Under Test
Test
Point
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
50%Input 50%
VCC
0 V
50% 50%
VOH
VOL
tPLH(1) tPHL(1)
VOH
VOL
tPHL(1) tPLH(1)
Output
Output 50% 50%
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
VOH
VOL
Output
VCC
0 V
Input
tf(1)
tr(1)
90%
10%
90%
10%
tr(1)
90%
10%
tf(1)
90%
10%
(1) The greater between tr and tf is the same as tt.
Figure 6-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
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SN54HC259, SN74HC259
SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
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7 Detailed Description
7.1 Overview
These 8-bit addressable latches are designed for general-purpose storage applications in digital systems.
Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers.
They are multifunctional devices capable of storing single-line data in eight addressable latches and being a
1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the
addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch
follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode,
all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are
changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input
with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.
7.2 Functional Block Diagram
SN54HC259, SN74HC259
SCLS134F – DECEMBER 1982 – REVISED MARCH 2022 www.ti.com
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Pin numbers shown are for the D, J, N, NS, PW, and W packages.
Figure 7-1. Logic Diagram, Each Internal Latch (positive logic)
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS OUTPUT OF
ADDRESSED
LATCH
EACH OTHER
OUTPUT FUNCTION
CLR G
H L D QiO Addressable latch
H H QiO QiO Memory
L L D L 8-line demultiplexer
L H L L Clear
Table 7-2. Latch Selection Table
SELECT INPUTS LATCH
ADDRESSED
S2 S1 S0
L L L 0
L L H 1
L H L 2
L H H 3
H L L 4
H L H 5
H H L 6
H H H 7
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
85519012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 85519012A
SNJ54HC
259FK
8551901EA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8551901EA
SNJ54HC259J
JM38510/65402BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65402BEA
M38510/65402BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65402BEA
SN54HC259J ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54HC259J
SN74HC259D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC259N
SN74HC259NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC259N
SN74HC259NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SNJ54HC259FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 85519012A
SNJ54HC
259FK
I TEXAS INSTRUMENTS Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54HC259J ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8551901EA
SNJ54HC259J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC259, SN74HC259 :
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PACKAGE OPTION ADDENDUM
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Addendum-Page 3
•Catalog : SN74HC259
•Military : SN54HC259
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Wiotn ot the carrier tape i P1 Ptlch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE a O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Dtrecllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC259DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC259PWR TSSOP PW 16 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
SN74HC259PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC259PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC259PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC259DR SOIC D 16 2500 853.0 449.0 35.0
SN74HC259DR SOIC D 16 2500 340.5 336.1 32.0
SN74HC259DR SOIC D 16 2500 364.0 364.0 27.0
SN74HC259DRG4 SOIC D 16 2500 340.5 336.1 32.0
SN74HC259DRG4 SOIC D 16 2500 367.0 367.0 38.0
SN74HC259NSR SO NS 16 2000 853.0 449.0 35.0
SN74HC259PWR TSSOP PW 16 2000 366.0 364.0 50.0
SN74HC259PWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74HC259PWR TSSOP PW 16 2000 853.0 449.0 35.0
SN74HC259PWT TSSOP PW 16 250 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
85519012A FK LCCC 20 1 506.98 12.06 2030 NA
SN74HC259D D SOIC 16 40 507 8 3940 4.32
SN74HC259D D SOIC 16 40 506.6 8 3940 4.32
SN74HC259DG4 D SOIC 16 40 506.6 8 3940 4.32
SN74HC259DG4 D SOIC 16 40 507 8 3940 4.32
SN74HC259N N PDIP 16 25 506 13.97 11230 4.32
SN74HC259N N PDIP 16 25 506 13.97 11230 4.32
SN74HC259NE4 N PDIP 16 25 506 13.97 11230 4.32
SN74HC259NE4 N PDIP 16 25 506 13.97 11230 4.32
SNJ54HC259FK FK LCCC 20 1 506.98 12.06 2030 NA
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 3
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PACKAGE OUTLINE
C
8.2
7.4 TYP
14X 1.27
16X 0.51
0.35
2X
8.89
0.15 TYP
0 - 10
0.3
0.1
2.00 MAX
(1.25)
0.25
GAGE PLANE
1.05
0.55
A
10.4
10.0
NOTE 3
B5.4
5.2
NOTE 4
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
£353 RE Vi“““‘ ““““““ WEECE = Era ,MQL 1"
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
14X (1.27)
(R0.05) TYP
(7)
16X (1.85)
16X (0.6)
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
Efimfifij v¢\‘\‘\‘\
www.ti.com
EXAMPLE STENCIL DESIGN
(7)
(R0.05) TYP
16X (1.85)
16X (0.6)
14X (1.27)
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
MECHANICAL DATA D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
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