SN54/74AHC573 Datasheet by Texas Instruments

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SNx4AHC573 Octal Transparent D-Type Latches With 3-State Outputs
1 Features 3 Description
The SNx4AHC573 devices are octal transparent D-
1• Operating Range 2-V to 5.5-V VCC type latches designed for 2-V to 5.5-V VCC operation.
• 3-State Outputs Directly Drive Bus Lines
• Latch-Up Performance Exceeds 250 mA Per Device Information(1)
JESD 17 PART NUMBER PACKAGE BODY SIZE (NOM)
• On Products Compliant to MIL-PRF-38535, SSOP (20) 7.20 mm × 5.30 mm
All Parameters Are Tested Unless Otherwise TVSOP (20) 5.00 mm × 4.40 mm
Noted. On All Other Products, Production SNx4AHC573 SOIC (20) 12.80 mm × 7.50 mm
Processing Does Not Necessarily Include Testing PDIP (20) 25.40 mm × 6.35 mm
of All Parameters. TSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
• Servers
• PCs and Notebooks
• Network Switches
• Wearable Health and Fitness Devices
• Telecom Infrastructures
• Electronic Points of Sale
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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5 Revision History
Changes from Revision K (January 2004) to Revision L Page
• Updated document to new TI data sheet format.................................................................................................................... 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Added Military Disclaimer to Features list. ............................................................................................................................. 1
• Added Applications................................................................................................................................................................. 1
• Added Pin Functions table...................................................................................................................................................... 3
• Added Handling Ratings table................................................................................................................................................ 4
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5
• Added Thermal Information table. .......................................................................................................................................... 5
• Added –40°C to 125°C temperature range for SN74AHC573 in Electrical Characteristics table.......................................... 6
• Added TA= –40°C to 125°C temperature range for SN74AHC573 in Timing Requirements table. ..................................... 6
• Added TA= –40°C to 125°C temperature range for SN74AHC573 in Timing Requirements table. ..................................... 6
• Added TA= –40°C to 125°C temperature range for SN74AHC573 in Switching Characteristics table. ............................... 7
• Added TA= –40°C to 125°C temperature range for SN74AHC573 in Switching Characteristics table. ............................... 8
• Added Typical Characteristics................................................................................................................................................ 9
• Added Detailed Description section...................................................................................................................................... 11
• Added Application and Implementation section.................................................................................................................... 12
• Added Power Supply Recommendations and Layout sections............................................................................................ 13
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OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
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2Q
3Q
4Q
5Q
6Q
3D
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5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
LE
VCC
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6 Pin Configuration and Functions
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 OE I Output Enable
2 1D I 1D Input
3 2D I 2D Input
4 3D I 3D Input
5 4D I 4D Input
6 5D I 5D Input
7 6D I 6D Input
8 7D I 7D Input
9 8D I 8D Input
10 GND — Ground
11 LE I Latch Enable
12 8Q O 8Q Output
13 7Q O 7Q Output
14 6Q O 6Q Output
15 5Q O 5Q Output
16 4Q O 4Q Output
17 3Q O 3Q Output
18 2Q O 2Q Output
19 1Q O 1Q Output
20 VCC — Power Pin
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7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
VIInput voltage range(2) –0.5 7 V
VOOutput voltage range(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –20 mA
IOK Output clamp current VO< 0 or VO> VCC ±20 mA
IOContinuous output current VO= 0 to VCC ±25 mA
Continuous current through VCC or GND ±75 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 0 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification 0 1000
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN54AHC573 SN74AHC573 UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 3 V 2.1 2.1 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 3 V 0.9 0.9 V
VCC = 5.5 V 1.65 1.65
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V –50 –50 µA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4 –4 mA
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4 4 mA
VCC = 5 V ± 0.5 V 8 8
VCC = 3.3 V ± 0.3 V 100 100
∆t/∆v Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20 20
TAOperating free-air temperature –55 125 –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74AHC573
THERMAL METRIC(1) DW DB DGV N NS PW UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 79.4 97.9 117.2 53.3 79.2 103.3
RθJC(top) Junction-to-case (top) thermal resistance 45.7 59.6 32.7 40.0 45.7 37.8
RθJB Junction-to-board thermal resistance 46.9 53.1 58.7 34.2 46.8 54.3 °C/W
ψJT Junction-to-top characterization parameter 18.7 21.3 1.15 26.4 19.3 2.9
ψJB Junction-to-board characterization parameter 46.5 52.7 58.0 34.1 46.4 53.8
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 125°C
TA= 25°C SN54AHC573 SN74AHC573 SN74AHC573
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX MIN MAX
2 V 1.9 2 1.9 1.9 1.9
IOH =−50 µA 3 V 2.9 3 2.9 2.9 2.9 V
VOH 4.5 V 4.4 4.5 4.4 4.4 4.4
IOH =−4 mA 3 V 2.58 2.48 2.48 2.48
IOH =−8 mA 4.5 V 3.94 3.8 3.8 3.8
2 V 0.1 0.1 0.1 0.1
IOL = 50 µA 3 V 0.1 0.1 0.1 0.1 V
VOL 4.5 V 0.1 0.1 0.1 0.1
IOL = 4 mA 3 V 0.36 0.5 0.44 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44 0.44
0 V to
IIVI= 5.5 V or GND ±0.1 ±1(1) ±1 ±1 µA
5.5 V
VI= VIL or VIH,
IOZ 5.5 V ±0.25 ±2.5 ±2.5 ±2.5 µA
VO= VCC or GND
ICC VI= VCC or GND, IO= 0 5.5 V 4 40 40 40 µA
CiVI= VCC or GND 5 V 2.5 10 10 10 pF
CoVO= VCC or GND 5 V 3.5 pF
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
7.6 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA= –40°C to 125°C
TA= 25°C SN54AHC573 SN74AHC573 SN74AHC573
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
twPulse duration, LE high 5 5 5 5 ns
tsu Setup time, data before LE↓3.5 3.5 3.5 3.5 ns
thHold time, data after LE↓1.5 1.5 1.5 1.5 ns
7.7 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA= –40°C to 125°C
TA= 25°C SN54AHC573 SN74AHC573 SN74AHC573
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
twPulse duration, LE high 5 5 5 5 ns
tsu Setup time, data before LE↓3.5 3.5 3.5 3.5 ns
thHold time, data after LE↓1.5 1.5 1.5 1.5 ns
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7.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA= –40°C to 125°C
TA= 25°C SN54AHC573 SN74AHC573
FROM TO LOAD SN74AHC573
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX
tPLH 7(1) 11(1) 1(1) 13(1) 1 13 1 14
D Q CL= 15 pF ns
tPHL 7(1) 11(1) 1(1) 13(1) 1 13 1 14
tPLH 7.6(1) 11.9(1) 1(1) 14(1) 1 14 1 15
LE Q CL= 15 pF ns
tPHL 7.6(1) 11.9(1) 1(1) 14(1) 1 14 1 15
tPZH 7.3(1) 11.5(1) 1(1) 13.5(1) 1 13.5 1 14.5
OE Q CL= 15 pF ns
tPZL 7.3(1) 11.5(1) 1(1) 13.5(1) 1 13.5 1 14.5
tPHZ 8.3(1) 11(1) 1(1) 13(1) 1 13 1 14
OE Q CL= 15 pF ns
tPLZ 8.3(1) 11(1) 1(1) 13(1) 1 13 1 14
tPLH 9.5 14.5 1 16.5 1 16.5 1 18
D Q CL= 50 pF ns
tPHL 9.5 14.5 1 16.5 1 16.5 1 18
tPLH 10.1 15.4 1 17.5 1 17.5 1 19
LE Q CL= 50 pF ns
tPHL 10.1 15.4 1 17.5 1 17.5 1 19
tPZH 9.8 15 1 17 1 17 1 18
OE Q CL= 50 pF ns
tPZL 9.8 15 1 17 1 17 1 18
tPHZ 10.7 14.5 1 16.5 1 16.5 1 17.5
OE Q CL= 50 pF ns
tPLZ 10.7 14.5 1 16.5 1 16.5 1 17.5
tsk(o) CL= 50 pF 1.5(2) 1.5 ns
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(2) On products compliant to MIL-PRF-38535, this parameter does not apply.
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7.9 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA= –40°C to 125°C
TA= 25°C SN54AHC573 SN74AHC573
FROM TO LOAD SN74AHC573
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX MIN MAX
tPLH 4.5(1) 6.8(1) 1(1) 8(1) 1 8 1 8.5
D Q CL= 15 pF ns
tPHL 4.5(1) 6.8(1) 1(1) 8(1) 1 8 1 8.5
tPLH 5(1) 7.7(1) 1(1) 9(1) 1 9 1 10
LE Q CL= 15 pF ns
tPHL 5(1) 7.7(1) 1(1) 9(1) 1 9 1 10
tPZH 5.2(1) 7.7(1) 1(1) 9(1) 1 9 1 10
OE Q CL= 15 pF ns
tPZL 5.2(1) 7.7(1) 1(1) 9(1) 1 9 1 10
tPHZ 5.2(1) 7.7(1) 1(1) 9(1) 1 9 1 10
OE Q CL= 15 pF ns
tPLZ 5.2(1) 7.7(1) 1(1) 9(1) 1 9 1 10
tPLH 6 8.8 1 10 1 10 1 11
D Q CL= 50 pF ns
tPHL 6 8.8 1 10 1 10 1 11
tPLH 6.5 9.7 1 11 1 11 1 12
LE Q CL= 50 pF ns
tPHL 6.5 9.7 1 11 1 11 1 12
tPZH 6.7 9.7 1 11 1 11 1 12
OE Q CL= 50 pF ns
tPZL 6.7 9.7 1 11 1 11 1 12
tPHZ 6.7 9.7 1 11 1 11 1 12
OE Q CL= 50 pF ns
tPLZ 6.7 9.7 1 11 1 11 1 12
tsk(o) CL= 50 pF 1(2) 1 ns
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(2) On products compliant to MIL-PRF-38535, this parameter does not apply.
7.10 Noise Characteristics(1)
VCC = 5 V, CL= 50 pF, TA= 25°C
SN74AHC573
PARAMETER UNIT
MIN MAX
VOL(P) Quiet output, maximum dynamic VOL 1 V
VOL(V) Quiet output, minimum dynamic VOL –0.8 V
VOH(V) Quiet output, minimum dynamic VOH 4 V
VIH(D) High-level dynamic input voltage 3.5 V
VIL(D) Low-level dynamic input voltage 1.5 V
(1) Characteristics are for surface-mount packages only.
7.11 Operating Characteristics
VCC = 5 V, TA= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 16 pF
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Temperature (qC)
TPD (ns)
-100 -50 0 50 100 150
0
1
2
3
4
5
6
D001
TPD in ns
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7.12 Typical Characteristics
Figure 1. TPD vs Temperature at 5 V Figure 2. TPD vs VCC
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l TEXAS INSTRUMENTS “ “x ' ’ fl‘ f i: f ,,, x x c ‘ 5 ‘ 1 5 ‘ EL,,, \ \ x w H H # w m k E. An paramemrs and waveforms are no: appncame m an devmes.
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤1 MHz, ZO= 50 Ω, tr≤3 ns, tf≤3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL= 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
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8 Parameter Measurement Information
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SNx4AHC573 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pull-up components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
9.3 Feature Description
• Wide operating voltage range
– Operates from 2 V to 5.5 V
• Allows down voltage translation
– Inputs accept voltages to 5.5 V
• Slow edges reduce output ringing
9.4 Device Functional Modes
Table 1. Function Table
(Each Latch)
INPUTS OUTPUT
Q
OE LE D
L H H H
L H L L
L L X Q0
H X X Z
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µC or
System Logic
OE V
GND
1D
8D
1Q
8Q
Regulated 5.0 V
5 V µC
System Logic
CC
LE
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AHC573 is a low-drive CMOS device that can be used for a multitude of bus-interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs accept voltages up to 5.5 V allowing down translation to the VCC level. Figure 5 shows
how the slower edges can reduce ringing on the output compared to higher drive parts like AC.
10.2 Typical Application
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
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Vcc
Unused Input
Input
Output
Input
Unused Input Output
AHC573
HC573
AC573
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Typical Application (continued)
10.2.3 Application Curves
Figure 5. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF bypass capacitor is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is
recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 6 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the IO’s so they cannot float when
disabled.
12.2 Layout Example
Figure 6. Layout Diagram
Copyright © 1995–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: SN54AHC573 SN74AHC573
l TEXAS INSTRUMENTS Am
SN54AHC573
,
SN74AHC573
SCLS242L –OCTOBER 1995–REVISED SEPTEMBER 2014
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
SN54AHC573 Click here Click here Click here Click here Click here
SN74AHC573 Click here Click here Click here Click here Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC573 SN74AHC573
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9685601Q2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
9685601Q2A
SNJ54AHC
573FK
Samples
5962-9685601QRA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9685601QR
A
SNJ54AHC573J
Samples
5962-9685601QSA ACTIVE CFP W 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9685601QS
A
SNJ54AHC573W
Samples
SN74AHC573DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA573 Samples
SN74AHC573DGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA573 Samples
SN74AHC573DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC573 Samples
SN74AHC573DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC573 Samples
SN74AHC573DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC573 Samples
SN74AHC573DWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC573 Samples
SN74AHC573DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC573 Samples
SN74AHC573N ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHC573N Samples
SN74AHC573NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC573 Samples
SN74AHC573PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA573 Samples
SN74AHC573PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HA573 Samples
SN74AHC573PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA573 Samples
SNJ54AHC573FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
9685601Q2A
SNJ54AHC
573FK
Samples
Addendum-Page 1
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2022
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54AHC573J ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9685601QR
A
SNJ54AHC573J
Samples
SNJ54AHC573W ACTIVE CFP W 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9685601QS
A
SNJ54AHC573W
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2022
OTHER QUALIFIED VERSIONS OF SN54AHC573, SN74AHC573 :
•Catalog : SN74AHC573
•Automotive : SN74AHC573-Q1, SN74AHC573-Q1
•Military : SN54AHC573
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
Addendum-Page 3
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHC573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74AHC573DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHC573DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74AHC573NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74AHC573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74AHC573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74AHC573PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC573DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74AHC573DGVR TVSOP DGV 20 2000 356.0 356.0 35.0
SN74AHC573DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74AHC573NSR SO NS 20 2000 367.0 367.0 45.0
SN74AHC573PWR TSSOP PW 20 2000 356.0 356.0 35.0
SN74AHC573PWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74AHC573PWRG4 TSSOP PW 20 2000 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9685601Q2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9685601QSA W CFP 20 1 506.98 26.16 6220 NA
SN74AHC573DW DW SOIC 20 25 507 12.83 5080 6.6
SN74AHC573DWG4 DW SOIC 20 25 507 12.83 5080 6.6
SN74AHC573N N PDIP 20 20 506 13.97 11230 4.32
SN74AHC573PW PW TSSOP 20 70 530 10.2 3600 3.5
SNJ54AHC573FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54AHC573W W CFP 20 1 506.98 26.16 6220 NA
Pack Materials-Page 3
MECHANICAL DATA W (R—GDFP—FZO) CERAWC DUAL FLATPACK Base and Szafing Hana (114111045 0.500 (7.62) f7 [1026 (0 as) 0.245 (6.22) f .: i ‘ ‘ 0.009 (023) fl? 0.004 0.10 <7 0.520="" (0.13)="" max="" 4»="" i="" 20="" :3="" i3:="" 0.022="" 0.56="" i:="" 3="" e="" )="" :i="" i:="" i="" 0.015="" (0.30)="" :3="" i:="" t="" :3="" ::i="" :3="" ::i="" 0.540="" (13.72)="" max="" [:3="" |::l="" [:3="" |::l="" [:3="" |::l="" [:3="" |::l="" “-005="" (m)="" m="" 4="" race:="" [:3="" i3:="" i="" 10="" i1="" 0="" 370="" (9,40)="" 0.370="" (9.40)="" 0.250="" (6.35)="" 0,250="" (5.35)="" 404013074/r="" 04/14="" notes:="" a.="" wpflw="" f0”:="" wilhin="" mh—std="" 1835="" gdfpz—fzo="" ah="" hnear="" dimensions="" are="" in="" inches="" (mhhmeters).="" this="" drawing="" ts="" sumeu="" \o="" cnange="" wunom="" nofice.="" this="" package="" can="" be="" hermelicahy="" semi="" win="" a="" ceramic="" lid="" using="" glass="" iril="" )ndex="" point="" is="" provided="" on="" cup="" (or="" lermina)="" identifica‘ion="" any.="" i="" texas="" instruments="" www.mmm="">
--I L J f T , g T Q f fl g
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
6.6
6.4
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
““‘w‘+‘w““‘
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
gmgmmj r Egg;
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
LAND PATTERN DATA PW (R7PDSOmGZO) PLAST‘C SMALL OUTLINE Exam ‘9 Board LG I“ F W Based on o stencii thickness oi .127mm (.oosinen). -—iiiiii‘fli*m -—iiiifi°fi°’i”ii ——U/,'Efli‘iiiiii -—HHHH1QXQBQHJH« A , Pad Geometry “\ 0,07 /’ ‘ ‘AH Arourig/ 421128475/6 08/15 NOTES: A. AH iineor dimensions are in miiiimeters. B. Inis drawing is subject to change without notice. c. Publication iPcr735i is recommended for aitemate design. D Laser cutting apertures witn trapezoidoi wuHs and oiso rounding earners wiii oiier aetter paste reieose. Customers should contact tneir board assembiy site (or stencii design recommendations. Reier to iPc—7525 (or otner stencii recommendations. E. Cusmmers shuuid Contact ‘heir hoard fubr‘icufiun site for solder musk tolerances beLween and nruund signal pads. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
I-III
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10
11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
“‘w“‘+“‘w“‘
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
mi: 2.5%
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MEC MPDSODSCr FEERUAHV199 DGV (R-PDSO-G“) PLASTIC 24 PINS SHOWN 0,16 NOM 17 i Gage Plane 0,15 7|,20MAX 0E PINS N 14 1s 20 24 as 43 56 DIM AMAX 3170 3.70 5110 5.10 7190 9,80 11,40 AMIN 350 3,50 490 4,90 7170 9,50 11,20 407325| /E 03/00 *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 75285
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
DW0020A I
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DW0020A
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DW0020A $$$$$fififiifi%
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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