NCP347 Datasheet by onsemi

ON Semiconductor8 (m NCP347 provides a ncgativc going flag (FLAG
© Semiconductor Components Industries, LLC, 2010
May, 2010 − Rev. 4
1Publication Order Number:
NCP347/D
NCP347
Positive Overvoltage
Protection Controller with
Internal Low RON NMOS FET
and Status FLAG
The NCP347 is able to disconnect the systems from its output pin
in case wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28 V.
Due to this device using internal NMOS, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
The NCP347 is able to instantaneously disconnect the output from
the input, due to integrated Low RON Power NMOS (65 mW), if the
input voltage exceeds the overvoltage threshold (OVLO) or
undervoltage threshold (UVLO).
At powerup (EN pin = low level), the Vout turns on 50 ms after the
Vin exceeds the undervoltage threshold.
The NCP347 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
Features
•Overvoltage Protection up to 28 V
•On−Chip Low RDS(on) NMOS Transistor: 65 mW
•Internal Charge Pump
•Overvoltage Lockout (OVLO)
•Undervoltage Lockout (UVLO)
•Internal 50 ms Startup Delay
•Alert FLAG Output
•Shutdown EN Input
•Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
•ESD Ratings: Machine Model = B
Human Body Model = 3
•10 Lead WDFN 2.5x2 mm Package
•This is a Pb−Free Device
Applications
•Cell Phones
•Camera Phones
•Digital Still Cameras
•Personal Digital Applications
•MP3 Players
WDFN10
MT SUFFIX
CASE 516AA
PIN CONNECTIONS
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MARKING
DIAGRAM
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
(Top View)
IN OUT
1
FLAG NC
GND NC
IN EN
Q
IN OUT
2
3
4
5
10
9
8
7
6
PAD1
GND
PAD2
IN
XXX M
G
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 12 of this data sheet.
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Figure 1. Typical Application Circuit
BAT 10
VSNS 9
V2P8 7
EN 6
1
ISEL
8
TIMER
4
GND
5
3
2
NCP1835B
IN
1OUT 6
GND
2
10
3
IN
4
IN
5OUT 7
NC 8
NC 9
NCP347
0
D3
7011X/SM
4.7 mF
15 pF
100 nF
1 mF
270 K
1 M
V2P8
ENABLE / Microprocessor
Wall Adapter − AC/DC
Lithium BATTERY
0
VBat
CFLG
FAULT
VCC
VBat
VBat
VBat
ENABLE /
Microprocessor
EN FLAG
Figure 2. Functional Block Diagram
INPUT OUTPUT
VREF VREF DISABLE
OVLO
UVLO
UVLO
OVLO
VREG
VREG
ESD
Protection
Core
Negative
Protection
Power
ON
ESD
Protection
Gate
Driver
60 mA
FLAG
10 V
EN
EN
Block
ESD
Protection
200 kHz
Delay
Generator
Oscillator
LDO
VREF
Charge
Pump
Output Impedance = 200 k
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PIN FUNCTION DESCRIPTION
Pin No. Symbol Function Description
1
4
5
IN POWER Input Voltage Pin.
This pin is connected to the power supply.
The device system core is supplied by this input.
A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND.
The three IN pins must be hardwired to common supply.
2 GND POWER Ground
3 FLAG OUTPUT Fault Indication Pin.
This pin allows an external system to detect a fault on IN pin.
The FLAG pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold.
Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added.
6
7
OUT OUTPUT Output Voltage Pin.
This pin follows IN pin when “no fault” is detected.
The output is disconnected from the Vin power supply when the input voltage is under the UVLO
threshold or above OVLO threshold.
The two OUT pins must be hardwired to common supply.
8 NC OPEN No Connect
9 NC OPEN No Connect
10 EN INPUT Enable Pin.
The device enters in shutdown mode when this pin is tied to a high level. In this case the output is
disconnected from the input.
To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin.
This pin does not have an impact on the fault detection.
PAD1 PAD1, under the device. See PCB recommendations page 10.
Can be shorted to GND.
PAD2 The PAD2 is electrically connected to the internal NMOS drain and connected to Pins 4 and 5.
See PCB recommendations page 10.
MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage (IN to GND) Vminin −0.3 V
Minimum Voltage (All others to GND) Vmin −0.3 V
Maximum Voltage (IN to GND) Vmaxin 30 V
Maximum Voltage (All others to GND) Vmax 7.0 V
Maximum Current (UVLO<VIN<OVLO) Imax 2.0 A
Thermal Resistance, Junction−to−Air (Note 1) RqJA 280 °C/W
Operating Ambient Temperature Range TA−40 to +85 °C
Storage Temperature Range Tstg −65 to +150 °C
Junction Operating Temperature TJ150 °C
ESD Withstand Voltage (IEC 61000−4−2) (input only) when bypassed with 1.0 mF capacitor
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd 15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity MSL Level 1 −
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The RqJA is highly dependent on the PCB heat sink area (connected to pad 2). As example RqJA is 268 °C/W with 30 mm2 (copper 35 mm) and
189 °C/W with 400 mm2.
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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ELECTRICAL CHARACTERISTICS (Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C,
unless otherwise noted.)
Characteristic Symbol Conditions Min Typ Max Unit
Input Voltage Range Vin −1.2 −28 V
Undervoltage Lockout Threshold (Note 4) UVLO Vin falls down UVLO threshold
from 5 V to 2.7 V
2.8 2.95 3.1 V
Undervoltage Lockout Hysteresis UVLOhyst Vin rises up UVLO + UVLOhyst 30 60 90 mV
Overvoltage Lockout Threshold (Note 4)
NCP347MTAE
NCP347MTAF
NCP347MTAH
NCP347MTAI
OVLO Vin rises up OVLO threshold
5.39
5.63
6.80
5.70
5.63
5.90
7.20
5.85
5.88
6.17
7.50
6.00
V
Overvoltage Lockout Hysteresis
NCP347MTAE, NCP347MTAF, NCP347MTAI
NCP347MTAH
OVLOhyst Vin falls down OVLO + OVLOhyst
30
50
60
70
90
100
mV
Vin versus Vout Resistance RDS(on) Vin = 5.0 V, EN = GND,
Load connected to Vout
−65 110 mW
Supply Quiescent Current Idd No load. EN = 5.0 V −90 150 mA
No load. EN = Gnd −170 250 mA
UVLO Supply Current Idduvlo VIN = 2.7 V −60 −mA
FLAG Output Low Voltage Volflag 1.2 V < VIN < UVLO
Sink 50 mA on/FLAG pin
−20 400 mV
VIN > OVLO
Sink 1.0 mA on FLAG pin
− − 400 mV
FLAG Leakage Current FLAGleak FLAG level = 5.0 V −1.0 −nA
EN Voltage High Vih −1.2 − − V
EN Voltage Low Vol − − − 0.4 V
EN Leakage Current ENleak EN = 5.0 V or GND −1.0 −nA
TIMINGS
Startup Delay
NCP347MTAE, NCP347MTAF, NCP347MTAH
NCP347MTAI
ton From Vin: (0 to (OVLO − 300 mV)
< Vin < OVLO) to Vout = 0.3 V
Rise time<4ms (See Figures 3&7)
30
6.0
50
10
70
14
ms
FLAG Going Up Delay
NCP347MTAE, NCP347MTAF, NCP347MTAH
NCP347MTAI
tstart From Vout = 0.3 V to FLAG =
1.2 V (See Figures 3 & 9) 30
6.0
50
10
70
14
ms
Output Turn Off Time toff From Vin > OVLO to Vout < =
0.3 V (See Figures 4 & 8)
Vin increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−1.5 5.0 ms
Alert Delay tstop From Vin > OVLO to FLAG < =
0.4 V (See Figures 4 & 10)
Vin increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−1.0 −ms
Disable Time tdis From EN > = 1.2 V to
Vout < 0.3 V
Rload = 5.0 W
(See Figures 5 & 12)
−1.0 5.0 ms
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representative for availability.
Figure 5. Disable on W Figure 6. FLAG Response with W
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TIMING DIAGRAMS
FLAG
Vout
Vin UVLO
ton
0.3 V tstart
1.2 V
<OVLO
Vin − (RDS(on) I)
FLAG
Vin
EN 1.2 V
OVLO
UVLO
100 ms
FLAG
Vout
Vin
OVLO
toff
0.3 V
tstop
0.4 V
Vin − (RDS(on) I)
FLAG
Vout
EN 1.2 V
tdis
0.3 V
Vin − (RDS(on) I)
Figure 3. Startup Figure 4. Shutdown on Overvoltage Detection
Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1
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TYPICAL OPERATING CHARACTERISTICS
Figure 7. Startup
Vin = Ch1, Vout = Ch3
Figure 8. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 9. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 10. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 11. Initial Overvoltage Delay
Vin = Ch1, Vout = Ch2, FLAG = Ch3
Figure 12. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
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TYPICAL OPERATING CHARACTERISTICS
Figure 13. Inrush Current with Cout = 100 mF,
I charge = 1 A, Output Wall Adaptor Inductance 1 mH
Figure 14. Output Short Circuit
Figure 15. Output Short Circuit (Zoom Fig. 14)
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VOLTAGE DETECTION
IN OUT
CONDITIONS
VIN > OVLO
0 < VIN < UVLO
And/Or
/EN = 1
VOLTAGE DETECTION
IN OUT
CONDITIONS
/EN = 0
&
UVLO < VIN < OVLO
Figure 16. Simplified Diagram
Figure 17. Simplified Diagram
Operation
The NCP347 provides overvoltage protection for
positive voltage, up to 28 V. A Low RDS(on) NMOS FET
protects the systems (i.e.: charger) connected on the Vout
pin, against positive overvoltage. At powerup, with EN pin
= low, the output is rising up 50 ms after the input
overtaking undervoltage UVLO (Figure 3). The NCP347
provides a FLAG output, which alerts the system that a fault
has occurred. A 50 ms additional delay, regarding
available output (Figure 3) is added between output signal
rising up and to FLAG signal rising up. FLAG pin is an open
drain output.
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Timer Check
Check Vin
FLAG = Low
Timer Count
Timer Check
Vin < UVLO or
Vin > OVLO
Check EN
Check EN
Vout = Vin
FLAG = High
Check Vin
Vout = Open
FLAG = High
Check Vin
Figure 18. State Machine
OVLO > Vin > UVLO
T < 50 ms
T = 50 ms
Reset Timer
Vout = 0
FLAG = Low
Reset Timer
Vin < UVLO or
Vin > OVLO Vout = 0
FLAG = Low
Timer Count
UVLO < Vin < OVLO
EN = 0EN = 1
Vin < UVLO or
Vin > OVLO
UVLO < Vin < OVLO
EN = 0EN = 1
T = 50 ms
Vout = Open
Vin < UVLO or
Vin > OVLO
T < 50 ms
UVLO < Vin < OVLO
Vout = Vin
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Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in undervoltage lockout (UVLO) circuit.
During Vin positive going slope, the output remains
disconnected from input until Vin voltage is below 2.92 V,
plus hysteresis, nominal. The FLAG output is tied to low as
long as Vin does not reach UVLO threshold. This circuit has
a 60 mV hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO can be manufactured. (See Selection Guide on page
12) Contact your ON Semiconductor representative for
availability.
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds
5.675 V typical (NCP347MTAE). Additional OVLO
thresholds ranging from OVLO can be manufactured. (See
Selection Guide on page 12) Contact your ON
Semiconductor representative for availability.
FLAG output is tied to low until Vin is higher than OVLO.
This circuit has a 90 mV hysteresis to provide noise
immunity to transient conditions.
FLAG Output
The NCP347 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the Vin level is below the UVLO
threshold. When Vin level recovers normal condition,
FLAG is held high, keeping in mind that an additional
50 ms delay has been added between available output and
FLAG = high. The pin is an open drain output, thus a pull
up resistor (typically 1 MW, minimum 10 kW) must be
added to Vbat. Minimum Vbat supply must be 2.5 V. The
FLAG level will always reflects Vin status, even if the
device is turned off (EN = 1).
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal NMOS FET
The NCP347 includes an internal Low RDS(on) NMOS
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
the RDS(on), during normal operation, will create low losses
on Vout pin.
As example: Rload = 8.0 W, Vin = 5.0 V
Typical RDS(on) = 65 mW, Iout = 618 mA
Vout = 8 x 0.618 = 4.95 V
NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW
ESD Tests
The NCP347 input pin fully supports the IEC61000−4−2.
1.0 mF (minimum) must be connected between Vin and
GND, close to the device.
That means, in Air condition, Vin has a "15 kV ESD
protected input. In Contact condition, Vin has "8.0 kV
ESD protected input.
Please refer to Figure 19 to see the IEC 61000−4−2
electrostatic discharge waveform.
Figure 19. Electrostatic Discharge Waveform
PCB Recommendations
The NCP347 integrates a 2 amperes rated NMOS FET,
and the PCB rules must be respected to properly evacuate
the heat out of the silicon. The PAD1 is internally isolated
from the active silicon and should preferably be connected
to ground. The PAD2 of the NCP347 package is connected
to the internal NMOS drain and can be used to increase the
heat transfer if necessary from an applications standpoint.
Depending upon the power dissipated in the application,
one can either use the PCB tracks connected to Pins 4 and
5 to evacuate heat, or make profit of the PAD2 area to add
extra copper surface to reduce the junction temperature
(See Figure 20). Of course, in any case, this pad shall be not
connected to any other potential. Figure 20 shows copper
area according to RqJA and allows the design of the heat
transfer plane connected to PAD2.
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Figure 20.
270
0 25 50 75 100 125 150 175
qJA (°C/W)
COPPER HEAT SPREADING AREA (mm2)
250
230
210
190
175
150
1 oz C.F.
310
290
200225 250 275 300 325350
2 oz C.F.
1 oz Sim
2 oz Sim
2
1
Figure 21. Demo Board Layout
1 mF 25 V X5R 0603 C1
EN
IN
IN
IN
FLAG
NC
NC
OUT
OUT
NCP347
GND
2
5
4
1
10
6
7
8
9
3
EN
100 k
R3
1
23
100 k
R2
OUTPUT
100 nF 50 V X7R 0805 not necessary
C2
1
2
R1
1 M
J2
FLAG Power
FLAG_State
1
2
GND F1 F2 F3 F4
Figure 22. Demo Board Schematic
EN_State
INPUT
EN_Power
FLAG
Murata GRM188R61E105KA12D
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ORDERING INFORMATION
Device Marking Package Shipping†
NCP347MTAETBG BAL
WDFN−10
(Pb−Free) 3000 / Tape & Reel
NCP347MTAFTBG BAM
NCP347MTAHTBG BAK
NCP347MTAITBG ACJ
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP347 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
a
NCP347MTxxTxG
bc
Code Contents
aUVLO Typical Threshold
a: A = 2.95 V
bOVLO Typical Threshold
b: E = 5.63 V
b: F = 5.90 V
b: H = 7.20 V
b: I = 5.85 V
cTape & Reel Type
c: B = 3000
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PACKAGE DIMENSIONS
WDFN10, 2.5x2, 0.5P
CASE 516AA−01
ISSUE C
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.13
2.50
0.50
0.05
0.73
10X
DIMENSIONS: MILLIMETERS
0.58
0.95
PITCH
0.30
10X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
C
A
SEATING
PLANE
DB
E
0.10 C
A3
A
A1
2X
2X 0.10 C
DIM
A
MIN NOM
MILLIMETERS
0.70 0.75
A1 0.00 ---
A3 0.20 REF
b0.20 0.25
D2.50 BSC
D2 0.97 1.08
E2.00 BSC
0.80 0.90
E2
e0.50 BSC
0.375 BSC
G
PIN ONE
REFERENCE
0.08 C
0.10 C
10X
A0.10 C
NOTE 3
L
e
D2
E2
b
B
5
6
10X
1
10
10X
0.05 C
8X
0.20 0.30
L
G1
A0.10 CB
0.05 C D3
G
A0.10 CB
0.05 C
K
D3 0.57 0.68
G1 0.35 BSC
K0.20 ---
0.80
0.05
0.30
1.18
1.00
0.40
0.78
---
MAX
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Phone: 81−3−5773−3850
NCP347/D
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