SN65DP159, SN75DP159 Datasheet by Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN65DP159

SN75DP159

SLLSEJ2G –JULY 2015–REVISED MARCH 2020

SNx5DP159 6-Gbps AC-Coupled TMDS™ to HDMI™ Level Shifter Retimer

1 Features

1• AC-coupled TMDS or DisplayPort Dual-Mode

Physical Layer Input to HDMI2.0b TMDS Physical

Layer Output Supporting up to 6 Gbps Data Rate,

Compatible with HDMI2.0b Electrical Parameters

• Supporting DisplayPort Dual-Mode Standard

Version 1.1

• Adaptive Receiver Equalizer and Programmable

Fixed Equalizer up to 16.5 dB

• High Speed Lane Control, Pre-emphasis and

Transmit Swing, and Slew Rate Control

• I2C or Pin Strap Programmable

• Supports Type-2 I2C-over-AUX to DDC Bridge

• Integrated TMDS Level Translator and CDR

• Active I2C[4] Buffer

• Input Swap on Main Lanes

• Low Power Consumption

– –435 mW Active at 6-Gbps and –10 mW at

Shutdown State

• Both Extended Commercial and Industrial

Temperature Device Options

• 40-pin, 0.4 mm Pitch, 5 mm x 5 mm, WQFN

Package, Pin Compatible to the TPD158 Redriver

• 40-pin, 0.5 mm Pitch, 7 mm x 7 mm, VQFN

Package

2 Applications

•Notebook, Desktop, All-in-Ones, Tablet, Gaming

and Industrial PC

•Audio/Video Equipment

•Blu-ray™ DVD

•Gaming Systems

•HDMI Adaptor or Dongle

•Docking Station

3 Description

The SNx5DP159 device is a dual mode[1]

DisplayPort to transition-minimized differential signal

(TMDS) retimer supporting digital video interface

(DVI) 1.0 and high-definition multimedia interface

(HDMI) 1.4b and 2.0b output signals. The

SNx5DP159 device supports the dual mode standard

version 1.1 type 1 and type 2 through the DDC link or

AUX channel. The SNx5DP159 device supports data

rate up to 6-Gbps per data lane to support Ultra HD

(4K × 2K / 60-Hz) 8-bits per color high-resolution

video and HDTV with 16-bit color depth at 1080p

(1920 × 1080 / 60-Hz). The SNx5DP159 device can

automatically configure itself as a re-driver at data

rates <1 Gbps, or as a retimer at more than this data

rate. This feature can be turned off through I2C[4]

programming.

For signal integrity, the SNx5DP159 device

implements several features. The SNx5DP159

receiver supports both adaptive and fixed

equalization to clean up inter-symbol interference

(ISI) jitter or loss from the bandwidth-limited board

traces or cables. When working as a retimer, the

embedded clock data recovery (CDR) cleans up the

input high frequency and random jitter from video

source. The transmitter provides several features for

passing compliance and reducing system-level

design issues like de-emphasis, which compensates

for the attenuation when driving long cables or high-

loss board traces. The SNx5DP159 device also

includes TMDS output amplitude adjust using an

external resistor on the Vsadj pin, source termination

selection, and output slew rate control. Device

operation and configuration can be programmed by

pin strapping or I2C[4].

The SNx5DP159 device implements several methods

for power management and active power reduction.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN65DP159

SN75DP159

VQFN (48) 7.00 mm × 7.00 mm

WQFN (40) 5.00 mm × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DP159 Mother Board Application Structure DP159 Dongle Application Structure

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Product Folder Links: SN65DP159 SN75DP159

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 5

6 Pin Configuration and Functions......................... 5

7 Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information.................................................. 9

7.5 Power Supply Electrical Characteristics ................. 10

7.6 Differential Input Electrical Characteristics ............. 11

7.7 HDMI and DVI TMDS Output Electrical

Characteristics ......................................................... 12

7.8 AUX, DDC, and I2C Electrical Characteristics ........ 13

7.9 HPD Electrical Characteristics................................ 13

7.10 HDMI and DVI Main Link Switching

Characteristics ......................................................... 14

7.11 AUX Switching Characteristics (Only for RGZ

Package).................................................................. 16

7.12 HPD Switching Characteristics ............................. 16

7.13 DDC and I2C Switching Characteristics................ 16

7.14 Typical Characteristics.......................................... 17

8 Parameter Measurement Information ................ 17

9 Detailed Description............................................ 25

9.1 Overview ................................................................. 25

9.2 Functional Block Diagram....................................... 25

9.3 Feature Description................................................. 26

9.4 Device Functional Modes........................................ 32

9.5 Register Maps......................................................... 33

10 Application and Implementation........................ 41

10.1 Application Information.......................................... 41

10.2 Typical Application ................................................ 46

10.3 System Example ................................................... 48

11 Power Supply Recommendations ..................... 49

11.1 Power Management.............................................. 49

12 Layout................................................................... 50

12.1 Layout Guidelines ................................................. 50

12.2 Layout Examples................................................... 51

12.3 Thermal Considerations........................................ 52

13 Device and Documentation Support ................. 53

13.1 Related Links ........................................................ 53

13.2 Documentation Support ........................................ 53

13.3 Receiving Notification of Documentation Updates 53

13.4 Community Resources.......................................... 53

13.5 Trademarks........................................................... 53

13.6 Electrostatic Discharge Caution............................ 53

13.7 Glossary................................................................ 53

14 Mechanical, Packaging, and Orderable

Information ........................................................... 54

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (May 2018) to Revision G Page

• Changed references to HDMI2.0a to HDMI2.0b ................................................................................................................... 1

• Added links to end equipment pages in Applications section. ............................................................................................... 1

Changes from Revision E (April 2018) to Revision F Page

• Changed From: "SN75DP159 is characterized from –40°C to 85°C" To "SN65DP159 is characterized from –40°C to

85°C" in the Description (continued) ...................................................................................................................................... 5

• Changed From: "SN65DP159 is characterized from 0°C to 85°C" To "SN75DP159 is characterized from 0°C to

85°C" in the Description (continued) ...................................................................................................................................... 5

Changes from Revision D (June 2017) to Revision E Page

• Changed the pinout images appearance in the Pin Configuration and Functions section..................................................... 5

Changes from Revision C (July 2016) to Revision D Page

• Changed the title From: " SNx5DP159 6-Gbps DP++ to HDMI Retimer" To: "SNx5DP159 6-Gbps AC-Coupled

TMDS™ to HDMI™ Level Shifter Retimer"............................................................................................................................ 1

• Changed the Features List ..................................................................................................................................................... 1

• Changed the Applications List................................................................................................................................................ 1

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• VSADJ: Added Note: "Best transmit eye ..", added MIN and MAx values in the Recommended Operating Conditions

table ....................................................................................................................................................................................... 9

• Changed the description of td1 in Table 1............................................................................................................................. 27

• Changed read procedures in the I2C Control Behavior section ........................................................................................... 35

• Added paragraph: "DP159 is designed..." to the Application and Implementation section.................................................. 41

• Added 2 paragraphs to the Application Information section................................................................................................. 41

• Added line item "Adding pre-emphasis will improve..." to the Detailed Design Procedure section ..................................... 47

Changes from Revision B (Arpil 2016) to Revision C Page

•Recommended Operating Conditions, Changed the CONTROL PINS section ..................................................................... 9

• Changed the AUX, DDC, and I2C Electrical Characteristics table ....................................................................................... 13

• Added text to Figure 31 Note: "The SCL_SRC and SDA_SRC pins must be pulled to ground."........................................ 43

Changes from Revision A (July 2015) to Revision B Page

• Added "Low-level input voltage at OE" to VIL in the Recommended Operating Conditions table.......................................... 9

• Added OE to VIH "High-level input voltage" in the Recommended Operating Conditions table ............................................ 9

• Changed Figure 22 .............................................................................................................................................................. 26

• Deleted the VDD_ramp and VCC_ramp MIN values in Table 1 ......................................................................................... 27

• Changed text "through the I2C interface" To: "through the I2C access on the DDC interface" in DDC Functional

Description............................................................................................................................................................................ 32

• Changed the HDMI and DVI value for 1Ah Table 3 ............................................................................................................ 33

• Added Note to 11–400-kbps in Table 7 ............................................................................................................................... 37

• Changed the note in the DEV_FUNC_MODE section of Table 7 ........................................................................................ 37

• Changed Note in the DDC_TRAIN_SET section of Table 8 ............................................................................................... 38

Changes from Original (July 2015) to Revision A Page

• Updated device status from product preview to production data .......................................................................................... 1

• Updated Typical Power Number ............................................................................................................................................ 1

• Removed Standby Power numbers ....................................................................................................................................... 1

• Changed From: Preview To: Production data ....................................................................................................................... 1

• Replaced SIG_EN with NC in pinout drawing and Pin Functions table ................................................................................. 5

• Removed lane swap from description of SWAP/POL = H .................................................................................................... 8

• Updated swing data ............................................................................................................................................................... 9

• Changed DDC link into its pin names between SNK and SRC and updated min value ....................................................... 9

• Added new line for SCL_SNK, SDA_SNK ............................................................................................................................. 9

• Removed standby power and standby current rows and updated active power and current numbers .............................. 10

• Changed term control to no source termination .................................................................................................................. 12

• Increased ILEAK max value from 10 µA to 45 µA................................................................................................................... 12

• Updated redriver mode max jitter value .............................................................................................................................. 14

• Clarified polarity swap to input signals ................................................................................................................................ 28

• Added more information on compliance in redriver mode ................................................................................................... 32

• Added note to DDC Functional Description section describing DDC snoop function ......................................................... 32

• Removed bit 4 SIG_EN and made reserved ....................................................................................................................... 37

• Removed SIG_EN Pin and added Note 1 for DDC Snoop ................................................................................................. 43

• Updated schematic to replace SIG_EN pin with NC ........................................................................................................... 44

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Product Folder Links: SN65DP159 SN75DP159

• Updated VID swing .............................................................................................................................................................. 47

• Changed Title to better match table. Removed Standby and redundant rows .................................................................... 49

• Updated drawing with pin 17 changed to NC ...................................................................................................................... 52

*9 TEXAS INSTRUMENTS ﬁ TL

48 VDD 13VCC

1SWAP/POL 36 TX_TERM_CTL

47 SDA_SRC14VDD

2IN_D2p 35 OUT_D2p

46 SCL_SRC15SCL_CTL

3IN_D2n 34 OUT_D2n

45 AUX_SRCp16SDA_CTL

4HPD_SRC 33 HPD_SNK

44 AUX_SRCn17NC

5IN_D1p 32 OUT_D1p

43 VCC 18CEC_EN

6IN_D1n 31 OUT_D1n

42 OE19GND

7GND 30 GND

41 GND20PRE_SEL

8IN_D0p 29 OUT_D0p

40 SLEW_CTL21EQ_SEL/A0

9IN_D0n 28 OUT_D0n

39 SDA_SNK22Vsadj

10I2C_EN/PIN 27 HDMI_SEL/A1

38 SCL_SNK23VDD

11IN_CLKp 26 OUT_CLKp

37 VDD 24VDD

12IN_CLKn 25 OUT_CLKn

Not to scale

Thermal

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5 Description (continued)

The SNx5DP159 receiver uses several methods to determine whether the application supports HDMI1.4b[2] or

HDMI2.0[3] data rates. The SNx5DP159 receiver comes in two packages: a 40-pin RSB supporting space-

constrained applications and a 48-pin RGZ version supporting the full feature set for DisplayPort dual-mode

standard version 1.1 in applications such as dongles.

The SN65DP159 device is characterized for an industrial operational temperature range from –40°C to 85°C.

The SN75DP159 device is characterized for an extended commercial operational temperature range from 0°C to

85°C.

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

l TEXAS INSTRUMENTS TL Ll Ll Ll Ll Ll Ll Ll Ll Ll Ll

40 VDD 11VCC

1IN_D2p 30 OUT_D2p

39 SDA_SRC12VDD

2IN_D2n 29 OUT_D2n

38 SCL_SRC13SCL_CTL

3HPD_SRC 28 HPD_SNK

37 VCC 14SDA_CTL

4IN_D1p 27 OUT_D1p

36 OE15GND

5IN_D1n 26 OUT_D1n

35 GND16PRE_SEL

6IN_D0p 25 OUT_D0p

34 SLEW_CTL17EQ_SEL/A0

7IN_D0n 24 OUT_D0n

33 SDA_SNK18Vsadj

8I2C_EN/PIN 23 HDMI_SEL/A1

32 SCL_SNK19VDD

9IN_CLKp 22 OUT_CLKp

31 VDD 20VDD

10IN_CLKn 21 OUT_CLKn

Not to scale

Thermal

Pad

SN65DP159

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SLLSEJ2G –JULY 2015–REVISED MARCH 2020

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(1) Blue pin names are only in the SNx5DP159 RGZ package.

(2) (H) Logic high (pin strapped to VCC through 65-kΩresistor); (L) logic low (pin strapped to GND through 65-kΩresistor); (for mid-level,

no connect)

RSB Package

40-Pin WQFN

Top View

Pin Functions

PIN(1) I/O DESCRIPTION(2)

SIGNAL NAME RGZ RSB

MAIN LINK INPUT PINS (FAIL SAFE)

IN_D2p 2 1 I Channel 2 differential input

IN_D2n 3 2

IN_D1p 5 4 I Channel 1 differential input

IN_D1n 6 5

IN_D0p 8 6 I Channel 0 differential input

IN_D0n 9 7

IN_CLKp 11 9 I Clock differential input

IN_CLKn 12 10

MAIN LINK OUTPUT PINS (FAIL SAFE)

OUT_D2n 34 29 O TMDS data 2 differential output

OUT_D2p 35 30

OUT_D1n 31 26 O TMDS data 1 differential output

OUT_D1p 32 27

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Pin Functions (continued)

PIN(1) I/O DESCRIPTION(2)

SIGNAL NAME RGZ RSB

OUT_D0n 28 24 O TMDS data 0 differential output

OUT_D0p 29 25

OUT_CLKn 25 21 O TMDS data clock differential output

OUT_CLKp 26 22

HOT PLUG DETECT PINS

HPD_SRC 4 3 O Hot plug detect output

HPD_SNK 33 28 I (Failsafe) Hot plug detect input

AUXILIARY/DDC DATA PINS

AUX_SRCp 45 N/A I/O Source side bidirectional DisplayPort auxiliary for I2C-over-AUX (DP159RGZ only)

AUX_SRCn 44 N/A

SDA_SRC 47 39 I/O (Failsafe) Source side TMDS port bidirectional DDC data line

SCL_SRC 46 38

SDA_SNK 39 33 I/O (Failsafe) Sink side TMDS port bidirectional DDC data lines

SCL_SNK 38 32

CONTROL PINS

OE 42 36 I

Operation enable/reset pin

OE = L: Power-down mode

OE = H: Normal operation

Internal weak pullup: Resets device when transitions from H to L

NC (1) 17 N/A I No connect

CEC_EN (1) 18 N/A O CEC control pin for Dongle applications

SLEW_CTL 40 34 I

level (2)

Slew rate control when I2C_EN/PIN = Low.

SLEW_CTL = H, fastest data rate

SLEW_CTL = L, 5 ps slow

SLEW_CTL = No Connect, 10 ps slow

When I2C_EN/PIN = High Slew rate is controlled through I2C[4]

PRE_SEL 20 16 I

level (2)

De-emphasis pin strap when I2C_EN/PIN = Low.

PRE_SEL = L: - 2 dB de-emphasis

PRE_SEL = No Connect: 0 dB

PRE_SEL = H: Reserved

EQ_SEL/A0 21 17 I

level (2)

Input Receive Equalization pin strap when I2C_EN/PIN = Low

EQ_SEL = L: Fixed EQ at 7.5 dB

EQ_SEL = No Connect: Adaptive EQ

EQ_SEL = H: Fixed at 14 dB

When I2C_EN/PIN = High

Address bit 1

Note: (3 level for pin strap programming but 2 level when I2C[4] address)

I2C_EN/PIN 10 8 I I2C_EN/PIN = High; puts device into I2C control mode

I2C_EN/PIN = Low; puts device into pin strap mode

SCL_CTL 15 13 I I2C clock signal

Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be

changed by I2C

SDA_CTL 16 14 I/O I2C data signal

Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be

changed by I2C

Vsadj 22 18 I TMDS-compliant voltage swing control nominal resistor to GND

HDMI_SEL/A1 27 23 I

HDMI_SEL when I2C_EN/PIN = Low

HDMI_SEL = High: Device configured for DVI

HDMI_SEL = Low: Device configured for HDMI (Adaptor ID block is readable through I2C[4]

or I2C-over-AUX.

When I2C_EN/PIN = High

Address bit 2

Note: Weak internal pull down

TX_TERM_CTL (1) 36 N/A I

level (2)

Transmit Termination Control when I2C_EN/PIN = Low

TX_TERM_CTL = H, No transmit termination

TX_TERM_CTL = L, Transmit termination impedance in 75 to about 150 Ω

TX_TERM_CTL = No Connect, automatically selects the termination impedance

Data rate (DR) > 3.4 Gbps – 75- to 150-Ωdifferential near end termination

2 Gbps < DR < 3.4 Gbps – 150- to 300-Ωdifferential near end termination

DR < 2 Gbps – no termination

Note: If left floating will be in automatic select mode.

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Pin Functions (continued)

PIN(1) I/O DESCRIPTION(2)

SIGNAL NAME RGZ RSB

SWAP/POL (1) 1 N/A I

level (2)

Input lane SWAP and polarity control pin when I2C_EN/PIN = Low

SWAP/POL = H receive lane polarity swap (retimer mode only)

SWAP/POL = L receive lanes swap (retimer and redriver mode)

SWAP/POL = No Connect normal working

SUPPLY AND GROUND PINS

VCC 13, 43 11, 37 P 3.3-V power supply

VDD 14, 23, 24,

37, 48 12, 19, 20,

31, 40 P 1.1-V power supply

GND 7, 19, 41,

30, 15, 35 G Ground

Thermal Pad Connected to ground

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (1)(2)

MIN MAX UNIT

Supply voltage(3) VCC –0.3 4 V

VDD –0.3 1.4 V

Voltage

Main link input (IN_Dx AC-coupled mode), AUX_SRCp, AUX_SRCn

differential voltage 1.56 V

TMDS outputs ( OUT_Dx) –0.3 4 V

HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, HDMI_SEL/A1, EQ_SEL/A0,

I2C_EN/PIN, SLEW_CTL, TX_TERM_CTL, SDA_SRC, SCL_SRC –0.3 4 V

HPD_SNK, SDA_SNK, SCL_SNK –0.3 6 V

Continuous power dissipation See Thermal Information

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V

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(1) Best transmit eye with minimum intra-pair skew, largest vertical and horizontal eye opening, maintaining HDMI compliant output swing

can be achieved with resistors around 6.4k. Using smaller resistors may lead to compliance failures.

(2) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the

internal bias to the proper voltage level which will not match the values shown here.

(3) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup

resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

GENERAL PARAMETERS

VCC Supply voltage 3 3.3 3.6 V

VDD 1.00 1.1 1.27

TCASE Case temperature for RSB package 93.5 °C

TCASE Case temperature for RGZ package 92.7 °C

TAOperating free-air temperature SN75DP159 0 85 °C

SN65DP159 –40 85

MAIN LINK DIFFERENTIAL PINS

VID_PP Peak-to-peak input differential voltage 75 1200 mv

VIC Input common mode voltage 0 2 V

CAC AC coupling capacitance 75 100 200 nF

dRData rate 0.25 5 Gbps

VSADJ TMDS-compliant swing voltage bias resistor (1) 4.5 7.06 7.5 kΩ

CONTROL PINS

VI-DC DC input voltage Control pins –0.3 3.6 V

VIL(2) Low-level input voltage at OE 0.8

Low-level input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL 0.3

VIM(2) No connect input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL 1 1.2 1.4 V

VIH (2) High-level input voltage at SLEW_CTL, OE(3) , PRE_SEL, EQ_SEL/A0,

TX_TERM_CTL, SWAP/POL 2.6 V

VOL Low-level output voltage 0.4 V

VOH High-level output voltage 2.4 V

IIH High-level input current –30 30 µA

IIL Low-level input current –10 10 µA

IOS Short circuit output current –50 50 mA

IOZ High impedance output current 10 µA

ROEPU Pullup resistance on OE pin 150 250 kΩ

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Test conditions for ΨJB and ΨJT are clarified in TI document Semiconductor and IC Package Thermal Metrics.

7.4 Thermal Information

THERMAL METRIC(1)

SNx5DP159 SNx5DP159

UNITRGZ (VQFN) RSB (WQFN)

48 PINS 40 PINS

RθJA Junction-to-ambient thermal resistance 31.1 37.3 °C/W

RθJC(top) Junction-to-case (top) thermal resistance (High-K board(2)) 18.2 23.1 °C/W

RθJB Junction-to-board thermal resistance (High-K board(2)) 8.1 9.9 °C/W

ψJT Junction-to-top characterization parameter 0.4 0.3 °C/W

ψJB Junction-to-board characterization parameter 8.1 3.8 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 3.2 °C/W

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(1) The typical rating is simulated at 3.3-V VCC and 1.1-V VDD and at 27°C temperature unless otherwise noted

(2) The maximum rating is simulated at 3.6-V VCC and 1.27-V VDD and at 85°C temperature unless otherwise noted

7.5 Power Supply Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT

PD1 Device power dissipation

(Retimer operation)

OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern, VI= 3.3 V,

I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H,

SDA_CTL/CLK_CTL = 0 V, VSadj = 7.06 kΩ

435 600 mW

PD2 Device power dissipation

(Redriver operation)

OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern, VI= 3.3 V,

I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H,

SDA_CTL/CLK_CTL = 0 V, VSadj = 7.06 kΩ

215 400 mW

PSD1 Device power in power

down OE = L, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V, VSadj = 7.06

kΩ10 30 mW

ICC1

VCC supply current

(TMDS 6Gpbs retimer

mode)

OE = H, VCC= 3.3 V/3.6 V, VDD = 1.1V/1.27 V, VSadj = 7.06

kΩ

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

35 50 mA

IDD1

VDD supply current

(TMDS 6Gpbs retimer

mode)

OE = H, VCC = 3.3 V/3.6 V, VDD = 1.1 V/1.27 V, VSadj = 7.06

kΩ

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

295 325 mA

ICC2

VCC supply current

(TMDS 6Gpbs redriver

mode)

OE = H, VCC = 3.3 V/3.465 V, VDD = 1.1 V/1.27 V, VSadj =

7.06 kΩ

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

8 20 mA

IDD2

VDD supply current

(TMDS 6Gpbs redriver

mode)

OE = H, VCC = 3.3 V/3.465 V, VDD = 1.1 V/1.27 V, VSadj =

7.06 kΩ

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

170 250 mA

ISD1 Power-down current OE = L, VCC = 3.3 V/3.465 V, VDD

= 1.1 V/1.27 V, VSadj = 7.06 kΩ3.3-V rail 2 5

ISD1 Power-down current OE = L, VCC = 3.3 V/3.465 V, VDD

= 1.1 V/1.27 V, VSadj = 7.06 kΩ1.1-V rail 3.5 10

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7.6 Differential Input Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DR_RX_DATA Ddata lanes data rate 0.25 6 Gbps

DR_RX_CLK Clock lanes clock rate 25 340 MHz

tRX_DUTY Input clock duty circle 40% 50% 60%

tCLK_JIT Input clock jitter tolerance 0.3 Tbit

tDATA_JIT Input data jitter tolerance Test the TTP2, see Figure 10 150 ps

TRX_INTRA Input intra-pair skew tolerance Test at TTP2 when DR = 1.6-Gbps, see

Figure 10 112 ps

TRX_INTER Input inter-pair skew tolerance 1.8 ns

EQH(D) Fixed EQ gain for data lane

IN_D(0,1,2)n/p EQ_SEL/A0 = H; Fixed EQ gain,

test at 6-Gbps 15 dB

EQL(D) Fixed EQ gain for data lane

IN_D(0,1,2)n/p EQ_SEL/A0 = L; Fixed EQ gain,

test at 6-Gbps 7.5 dB

EQZ(D) Adaptive EQ gain for data lane

IN_D(0,1,2)n/p EQ_SEL/A0 = Z; adaptive EQ 2 15 dB

EQ(c) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0 = H,L,NC 3

RINT Input differential termination impedance 80 100 120 Ω

VITERM Input termination voltage OE = H 0.7 V

VID_PP Input differential voltage (peak to peak) Tested at TTP2, check Figure 10 75 1200 mVPP

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7.7 HDMI and DVI TMDS Output Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH Single-ended high level output voltage

Data rate ≤1.65-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; DR = 750-

Mbps, VSadj = 7.06-kΩ

VCC – 10 VCC + 10

1.65-Gbps < Data rate ≤3.4-Gbps;

PRE_SEL = NC; TX_TERM_CTL =

H; SLEW_CTL = H; OE = H; DR =

2.97-Gbps, VSadj = 7.06-kΩ

VCC – 200 VCC + 10

VOH Single-ended high level output voltage

3.4-Gbps < Data rate < 6 Gbps;

PRE_SEL = NC; TX_TERM_CTL = L;

SLEW_CTL = H; OE = H; DR = 6-

Gbps, VSadj = 7.06-kΩ

VCC – 400 VCC + 10 mV

VOL Single-ended low level output voltage

Data rate ≤1.65-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; DR = 750-

Mbps, VSadj = 7.06-kΩ

VCC – 600 VCC – 400

1.65-Gbps < Data rate ≤3.4-Gbps;

PRE_SEL = NC; TX_TERM_CTL =

H; SLEW_CTL = H; OE = H; DR =

2.97-Gbps, VSadj = 7.06-kΩ

VCC – 700 VCC – 400

VOL Single-ended low level output voltage

3.4-Gbps < Data rate < 6-Gbps;

PRE_SEL = NC; TX_TERM_CTL = L;

SLEW_CTL = H; OE = H; DR = 6-

Gbps

VCC – 1000 VCC – 400 mV

VSWING_DA Single-ended output voltage swing on

data lane

PRE_SEL = NC; TX_TERM_CTL =

H/NC/L; SLEW_CTL = H; OE = H;

DR = 270-Mbs/2.97/6Gbps VSadj =

7.06-kΩ

400 500 600 mV

VSWING_CLK Single-ended output voltage swing on

clock lane

Data rate ≤3.4-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; VSadj =

7.06-kΩ

400 500 600

Data rate > 3.4-Gbps; PRE_SEL =

NC; TX_TERM_CTL = NC;

SLEW_CTL = H; OE = H; VSadj =

7.06-kΩ

200 300 400

ΔVSWING Change in single-end output voltage

swing per 100 Ω ΔVsadj 20 mV

ΔVOCM(SS) Change in steady state output common

mode voltage between logic levels –5 5 mV

VOD(PP) Output differential voltage before pre-

emphasis Vsadj = 7.06-kΩ; PRE_SEL = Z, See

Figure 8 800 1200 mV

VOD(SS) Steady-state output differential voltage Vsadj = 7.06-kΩ; PRE_SEL = L, See

Figure 9 600 1050 mV

ILEAK Failsafe condition leakage current VCC = 0-V; VDD = 0-V; output pulled

to 3.3 V through 50-Ωresistors 45 µA

IOS Short circuit current limit Main link output shorted to GND 50 mA

RTERM Source termination resistance for HDMI

2.0 75 150 Ω

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7.8 AUX, DDC, and I2C Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CIO Input capacitance AUX data rate = 1-MHz 10 pF

CAC AUX AC coupling capacitance 75 200 nF

DR(AUX) Data rate of the AUX channel input 0.8 1 1.2 Mbps

VI-DC(AUX)

DC input voltage on AUX channel,

AUX_SRCp/n: 100-kΩpull up to 3.6 V

but differential common mode is 2 V

or less.

-0.5 3.6 V

VAUX_DIFF_PP_TX Peak-to-peak differential voltage at

TX pins VAUX_DIFF_PP = 2 × |VAUXP – VAUXN| 0.29 1.38 V

VAUX_DIFF_PP_RX Peak-to-peak differential voltage at

RX pins VAUX_DIFF_PP = 2 × |VAUXP – VAUXN| 0.14 1.36 V

VAUX_DC_CM AUX channel DC common mode

voltage 0 2 V

IAUX_SHORT AUX channel short circuit current limit 90 mA

VI-DC

SCL/SDA_SNK DC input voltage –0.3 5.6 V

SCL/SDA_CTL, SCL/SDA_SRC DC

input voltage -0.3 3.6 V

VIL

SCL/SDA_SNK, SCL/SDA_SRC Low

level input voltage 0.3 x VCC V

SCL/SDA_CTL Low level input

voltage 0.3 x VCC V

VIH

SCL/SDA_SNK high level input

voltage 3 V

SCL/SDA_SRC high level input

voltage 0.7 x VCC V

SCL/SDA_CTL high level input

voltage 0.7 x VCC V

VOL SCL/SDA_CTL, SCL/SDA_SRC low-

level output voltage

I0= 3-mA and VCC > 2-V 0.4 V

I0= 3-mA and VCC < 2-V 0.2 VCC V

fSCL SCL clock frequency fast I2C mode

for local I2C control 400 kHz

Cbus Total capacitive load for each bus line

(DDC and local I2C pins) 400 pF

7.9 HPD Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH High-level input voltage HPD_SNK 2.1 V

VIL Low-level input voltage HPD_SNK 0.8 V

VOH High-level output voltage IOH = –500-µA; HPD_SRC 2.4 3.6 V

VOL Low-level output voltage IOL = 500-µA; HPD_SRC 0 0.1 V

ILEAK Failsafe condition leakage current VCC = 0-V; VDD = 0-V; HPD_SNK = 5-V 40 μA

IH_HPD High-level input current Device powered; VIH = 5-V;

IH_HPD includes RpdHPD resistor current 40 μA

IL_HPD Low-level input current Device powered; VIL = 0.8-V;

IL_HPD includes RpdHPD resistor current 30

RpdHPD HPD input termination to GND VCC = 0-V 150 190 220 kΩ

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7.10 HDMI and DVI Main Link Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REDRIVER MODE

DRData rate (Automatic Mode) 250 1000 Mbps

DRData rate (full redriver mode) 250 6000 Mbps

tPLH Propagation delay time (low to high) 250 600 ps

tPHL Propagation delay time (high to low) 250 800 ps

tT1

Transition time (rise and fall time);

measured at 20% and 80% levels for data

lanes. TMDS clock meets tT3 for all three

times.

SLEW_CTL = H; TX_TERM_CTL = L;

PRE_SEL = NC; OE = H; DR = 6 Gbps 45

tT2 SLEW_CTL = L; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H; DR = 6 Gbps 65

tT3

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; CLK 150MHz 100

tSK1(T) Intra-pair output skew SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; 40 ps

tSK2(T) Inter-pair output skew SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; 100 ps

tJITD1(1.4b) Total output data jitter

DR = 2.97 Gbps, HDMI_SEL/A1 = NC,

EQ_SEL/A0 = NC; PRE_SEL = NC;

SLEW_CTL = H OE = H.

See Figure 10 at TTP3

0.2 Tbit

tJITD1(2.0) Total output data jitter

3.4Gbps < Rbit ≤3.712Gps SLEW_CTL

= H; TX_TERM_CTL = NC; PRE_SEL =

NC; OE = H 0.4 Tbit

3.712Gbps < Rbit < 5.94Gbps

SLEW_CTL = H; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H

-0.033

2Rbit2

+0.23

Rbit +

0.1998

Tbit

5.94Gbps ≤Rbit ≤6.0Gbps SLEW_CTL

= H; TX_TERM_CTL = NC; PRE_SEL =

NC; OE = H 0.8 Tbit

tJITC1(1.4b) Total output clock jitter CLK = 297 MHz 0.25 Tbit

tJITC1(2.0) Total output clock jitter DR = 6Gbps: CLK = 150 MHz 0.3 Tbit

RETIMER MODE

dRData rate (Full retimer mode) 0.25 6 Gbps

dRData rate (Automatic mode) 1.0 6 Gbps

dXVR Automatic redriver to retimer crossover Measured with input signal applied from

0 to 200 mVpp .75 1.0 1.25 Gbps

fCROSSOVER Crossover frequency hysteresis 250 MHz

PLLBW Data retimer PLL bandwidth Default loop bandwidth setting .4 1 MHz

tACQ Input clock frequency detection and retimer

acquisition time 180 μs

IJT1 Input clock jitter tolerance Tested when data rate > 1.0 Gbps 0.3 Tbit

tT1

Transition time (rise and fall time);

measured at 20% and 80% levels for data

lanes. TMDS clock meets tT3 for all three

times.

SLEW_CTL = H; TX_TERM_CTL = L;

PRE_SEL = NC; OE = H; DR = 6 Gbps 45

tT2 SLEW_CTL = L; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H; DR = 6 Gbps 65

tT3

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; CLK = 150 MHz 100

tDCD OUT_CLK ± duty cycle 40% 50% 60%

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HDMI and DVI Main Link Switching Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) –0.0332Rbit2+ 0.2312 Rbit + 0.1998

(2) –19.66 × (Rbit2) + (106.74 × Rbit) + 209.58

tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew

adjust, HDMI_SEL/A1 = NC

0.2 Tch

tSK_INTRA 0.15 Tbit

tJITC1(1.4b) Total output clock jitter CLK = 297 MHz 0.25 Tbit

tJITC1(2.0) Total output clock jitter DR = 6Gbps: CLK = 150 MHz 0.3 Tbit

tJITD2 Total output data jitter

3.4 Gbps < Rbit ≤3.712 Gbps 0.4

Tbit3.712 Gbps < Rbit < 5.94 Gbps See

(1)

5.94 Gbps ≤Rbit ≤6.0 Gbps 0.6

VOD_range Total TMDS data lanes output differential

voltage

3.4 Gbps < Rbit ≤3.712 Gbps 335

mV3.712 Gbps < Rbit < 5.94 Gbps See

(2)

5.94 Gbps ≤Rbit ≤6.0 Gbps 150

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7.11 AUX Switching Characteristics (Only for RGZ Package)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UIMAN Manchester transaction unit interval 0.4 0.6 µs

tAUXjitter_TX Cycle-to-cycle jitter time at transmit pins 0.08 UIMAN

tAUXjitter_RX Cycle-to-cycle jitter time receive pins 0.05 UIMAN

7.12 HPD Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPD(HPD) Propagation delay from HPD_SNK to

HPD_SRC; rising edge and falling edge See Figure 14; not valid during switching

time 40 120 ns

tT(HPD) HPD logical disconnected timeout See Figure 15 2 ms

(1) Cb = total capacitance of one bus line in pF.

7.13 DDC and I2C Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

trRise time of both SDA and SCL signals Vcc = 3.3-V 300 ns

tfFall time of both SDA and SCL signals 300 ns

tHIGH Pulse duration, SCL high 0.6 μs

tLOW Pulse duration, SCL low 1.3 μs

tSU1 Setup time, SDA to SCL 100 ns

tST, STA Setup time, SCL to start condition 0.6 μs

tHD,STA Hold time, start condition to SCL 0.6 μs

tST,STO Setup time, SCL to stop condition 0.6 μs

t(BUF) Bus free time between stop and start condition. 1.3 μs

tPLH1 Propagation delay time, low-to-high-level output Source-to-sink: 100-kbps pattern;

Cb(Sink) = 400-pF(1);

See Figure 18 360 ns

tPHL1 Propagation delay time, high-to-low-level output 230 ns

tPLH2 Propagation delay time, low-to-high-level output Sink to Source: 100-kbps pattern;

Cb(Source) = 100-pF(1);

See Figure 19 250 ns

tPHL2 Propagation delay time, high-to-low-level output 200 ns

l TEXAS INSTRUMENTS 350 200 1 son /7

Driver

VTERM

50Q

Receiver

3.3V

50Q

D+

D-

VD+

VD-

VID

VID = VD+ - VD-

0.5 pF

VOD = VY - VZ

VICM = (VD+ + VD-)

VOC = (VY + VZ)

75-200nF

Vsadj (k:)

VOD (mVpp)

4 4.5 5 5.5 6 6.5 7 7.5 8

200

400

600

800

1000

1200

1400

1600

D003

VOD No Term

VOD 150 to 300 :

VOD 75 to 150 :

Data Rate (Gbps)

Current (mA)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

100

150

200

250

300

350

D001

1.1 V

3.3 V

Data Rate (Gbps)

Current (mA)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

100

120

140

160

180

200

D002

1.1 V

3.3 V

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7.14 Typical Characteristics

Figure 1. Current vs Data Rate in Retimer Mode Figure 2. Current vs Data Rate in Redriver Mode

Figure 3. VOD vs Vsadj

8 Parameter Measurement Information

Figure 4. TMDS Main Link Test Circuit

l TEXAS INSTRUMENTS 22v TMDS_OUTyn

VOC ûVOC(SS)

TMDS_OUTxp

TMDS_OUTxn

50%

tSK2(T)

TMDS_OUTyp

TMDS_OUTyn

tSK1(T) tSK1(T)

VTERM

VID+

tPHL

20%

0 V

80%

2.2 V

1.8 V

VID±

VID(pp)

VID

0 V

tPLH

80%

20%

VOD(pp)

VOD

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Parameter Measurement Information (continued)

Figure 5. Input and Output Timing Measurements

Figure 6. HDMI and DVI Sink TMDS Output Skew Measurements

Figure 7. TMDS Main Link Common Mode Measurements

l TEXAS INSTRUMENTS Kn PRE_SEL= Z ...... .....-.........-.........-... ----J --......-..-......-..-......-J

VOD(SS)

VOD(PP)

1st bit 2nd to N bit

PRE_SEL = Z

Vsadj = 7.06 lQ

PRE_SEL = L

Vsadj = 7.06 lQ

VOD(PP)

PRE_SEL=Z

Vsadj = 7.06<Q

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Parameter Measurement Information (continued)

Figure 8. Output Differential Waveform 0 dB De-Emphasis

Figure 9. PRE_SEL = L for –2-dB De-Emphasis

l TEXAS INSTRUMENTS T T T T T T TTP1 'I'I'P2'I'I'P27EQ TTF'3 I I I I I I I I

0.5

DP159 Post EQ Eye Mask

t20

t75

(mV)

0.7

0.3

33.7t33.7

Tbit

(ps) 25t25

HDMI Mask

Coax

Device

SMA

Avcc(4)

RTRT(5)

AVcc

RTRT

Jitter Test

Instrument(2,3)

TTP4

TTP2TTP1

FR4 PCB trace(1)

and AC coupling

capacitors

FR4 PCB trace

+EQ OUT

SMA

TTP3

Jitter Test

Instrument(2,3)

Data +

Data ±

Clk+

Clk±

Parallel(6)

BERT

[No Pre-

emphasis]

REF

Cable

REF

Cable

TTP4_EQ

TTP2_EQ

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Parameter Measurement Information (continued)

(1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap, connector and another

1-2” of FR4. Trace width – 4 mils. 100-Ωdifferential impedance.

(2) All jitter is measured at a BER of 10-9.

(3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.

(4) AVCC = 3.3-V

(5) RT = 50-Ω

(6) The input signal from parallel bit error rate tester (BERT) does not have any pre-emphasis. Refer to Recommended

Operating Conditions.

Figure 10. TMDS Output Jitter Measurement

Figure 11. Post EQ Input Eye Mask at TTP2_EQ

‘5‘ TEXAS INSTRUMENTS

0.5

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Parameter Measurement Information (continued)

TMDS DATA RATE (Gbps) H (Tbit) V (mV)

3.4 < DR < 3.712 0.6 335

3.712 < DR < 5.94 –0.0332Rbit2+ 0.2312Rbit + 0.1998 –19.66Rbit2+ 106.74Rbit + 209.58

5.94 ≤DR ≤6.0 0.4 150

Figure 12. Output Eye Mask at TTP4_EQ

‘5‘ TEXAS INSTRUMENTS

50%

HPD_SNK

Vcc

HPD Logical Disconnect

Timeout

tT(HPD)

HPD_SRC

Device Logically

Connected

Logically

Disconnected

VCC

0 V

VCC

0 V

tPD(HPD)

HPD_SNK

HPD_SRC

50%

100K190K

HPD_SNK HPD_SRC

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Figure 13. HPD Test Circuit

Figure 14. HPD Timing Diagram Number 1

Figure 15. HPD Logic Disconnect Timeout

‘5‘ TEXAS INSTRUMENTS

SCL

SDA

tHIGH tLOW

tSU1

tST,STA

SCL

SDA

START STOP

tHD,STA

t(BUF)

trtf

tST,STO

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Figure 16. Start and Stop Condition Timing

Figure 17. SCL and SDA Timing

l TEXAS INSTRUMENTS

SDA_SNK/

SCL_SNK

INPUT

SDA_SRC/

SCL_SRC

OUTPUT

½ Vcc

tPHL2

tPLH2

80%

20%

tftr

SDA_SRC/

SCL_SRC

INPUT

SDA_SNK/

SCL_SNK

OUTPUT

½ Vcc

tPHL1 tPLH1

20%

80%

tftr

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Figure 18. DDC Propagation Delay – Source to Sink

Figure 19. DDC Propagation Delay – Sink to Source

l TEXAS INSTRUMENTS

IN_CLKp

IN_CLKn

IN_D[2:0]p

IN_D[2:0]n

50Q

50Q50Q

50Q

Control Block, I2C Registers

Local I2C

Control

I2C_EN/PIN

EQ_SEL/A0

PRE_SEL

Data Registers

SWAP

PLL

PLL Control

SERDES

VBIAS

EQ_SEL

HDMI_SEL

OUT_CLKp

OUT_D[2:0]p

OUT_CLKn

OUT_D[2:0]n

SWAP

Polarity

PLL BW

STBY

PWR DN

EQ_CTL

SDA_CTL

SCL_CTL

VSADJ

SWAP/POL

TX_TERM_CTL

SLEW_CTL

HDMI_SEL/A1

TERM_SEL

SLEW_SEL

PRE_SEL

Enable

TMDS

ACTIVE DDC BLOCK

HPD_SNK

HPD_SRC

190<Q

SDA_SRC

SCL_SRC

SDA_SNK

SCL_SNK

DDC Snoop Block

I2C over AUX

DDC

Bridge

AUX_SRCp

AUX_SRCn

CEC_EN

GND

VDD

VCC

1.1V

3.3V

VREG

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9 Detailed Description

9.1 Overview

The SNx5DP159 device is a Dual Mode[1] DisplayPort retiming level shifter that supports data rates up to 6-

Gbps for HDMI2.0b. The device takes in AC coupled HDMI/DVI signals and level shifts them to TMDS signals

while compensating for loss and jitter through its receiver equalizer and retiming functions. The SNx5DP159 in

default configuration should meet most system needs but also provides features that allow the system

implementer flexibility in design. Programming can be accomplished through I2C[4] or pin strapping.

9.2 Functional Block Diagram

NOTE: Black pin names are common to both packages.

Blue pin names are only in the SNx5DP159 RGZ package.

iiiiiiiiiiiiiiiiii

td2

td1

VCC / VDD

VDD / VCC

RRST = 200 KŸ

GPO OE

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9.3 Feature Description

9.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the Dual Mode[1] DisplayPort inputs and outputs are

high impedance. It is critical to transition the OE input from a low level to a high level after the VCC supply has

reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE

input, or by an external capacitor connected between OE and GND. To ensure that the SNx5DP159 device is

properly reset, the OE pin must be de-asserted for at least 100-μs before being asserted. When OE is toggled in

this manner the device is reset. This requires the device to be reprogrammed if it was originally programmed

through I2C for configuration. When implementing the external capacitor, the size of the external capacitor

depends on the power-up ramp of the VCC supply, where a slower ramp-up results in a larger value external

capacitor. Refer to the latest reference schematic for SNx5DP159; consider approximately 200-nF capacitor as a

reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in Figure 20

and Figure 21.

SPACE

Figure 20. External Capacitor Controlled OE Figure 21. OE Input from Active Controller

9.3.2 Operation Timing

SNx5DP159 starts to operate after the OE signal goes high (see Figure 22,Figure 23, and Table 1). Keeping OE

low until VDD and VCC become stable avoids any timing requirements as shown in Figure 22.

Figure 22. Power-Up Timing for SSNx5DP159

l TEXAS INSTRUMENTS ﬂ 1 E; Red river mode

Retimer mode

CDR Active

td3

td4

OE De-assert or

HPD_SNK De-assert or

Redriver mode

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Feature Description (continued)

Figure 23. CDR Timing for SNx5DP159

Table 1. SNx5DP159 Operation Timing

MIN MAX UNIT

td1 VDD/VCC stable before VCC/VDD 0 200 µs

td2 VDD and VCC stable before OE deassertion 100 µs

td3 CDR active operation after retimer mode initial 15 ms

td4 CDR turn off time after retimer mode de-assert 120 ns

VDD_ramp VDD supply ramp-up requirements 100 ms

VCC_ramp VCC supply ramp-up requirements 100 ms

9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)

The SNx5DP159 device incorporates the I2C-over-AUX to DDC bridge to support the DisplayPort Dual-Mode

standard version 1.1. It enables the communication between source device and sink device through AUX

channel. The bridge receives the request from source device in the I2C-over-AUX format and transfers it into

DDC signal to sink device. When the sink device responds, the request in the DDC channel and bridge packages

it into I2C-over-AUX and sends it back to the source device.

9.3.4 Input Lane Swap and Polarity Working

The SNx5DP159 device incorporates the swap function, which can set the input lanes in swap mode. The IN_D2

routes to the OUT_CLK position. The IN_D1 swaps with IN_D0. The swap function only changes the input pins;

EQ setup follows new mapping. The SWAP/POL is pin 1 in the 48-pin RGZ package.For the RSB version, the

user needs to control the register 0x09h bit 7 for SWAP enable. Lane swap is operational in both redriver and

retimer mode.

(1) The output lanes never change. Only the input lanes change. See Figure 24 and Figure 25.

Table 2. Lane Swap(1)

NORMAL OPERATION SWAP = L OR CSR 0x09h BIT 7 IS 1’b1

IN_D2 →OUT_D2 IN_D2 →OUT_CLK

IN_D1 →OUT_D1 IN_D1 →OUT_D0

IN_D0 →OUT_D0 IN_D2 →OUT_D1

IN_CLK →OUT_CLK IN_CLK →OUT_D2

*9 TEXAS INSTRUMENTS

I2C_EN/GPIO

HPD_SRC

OUT_CLKp

OUT_CLKn

OUT_D0p

OUT_D0n

OUT_D1p

OUT_D1n

OUT_D2p

OUT_D2n

HPD_SNK

IN_CLKn

IN_CLKp

IN_D1n

IN_D1p

IN_D2n

IN_D2p

IN_D0n

IN_D0p

HDMI_SEL

40-Pin RSB

In Normal Working

40-Pin RSB

In Swap Working

CLOCK LANE

DATA LANE0

DATA LANE1

DATA LANE2 CLOCK LANE

DATA LANE0

DATA LANE1

DATA LANE2 OUT_CLKp

OUT_CLKn

OUT_D0p

OUT_D0n

OUT_D1p

OUT_D1n

OUT_D2p

OUT_D2n

HPD_SNK

HDMI_SEL

I2C_EN/GPIO

HPD_SRC

IN_CLKn

IN_CLKp

IN_D1n

IN_D1p

IN_D2n

IN_D2p

IN_D0n

IN_D0p

HPD_SRC

GND

OUT_D0p

OUT_D0n

TERM_CTL

I2C_EN/PIN

HPD_SNK

IN_D1n

IN_D1p

IN_D2n

IN_D2p

IN_D0n

IN_D0p

IN_CLKn

IN_CLKp

OUT_D2p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_CLKp

OUT_CLKn

SWAP/POL

GND

36 TERM_CTL

SWAP = Z

In Normal Working SWAP = L

In Swap Working

CLOCK LANE

DATA LANE0

DATA LANE1

DATA LANE2

OUT_D0p

OUT_D0n

HPD_SNK

OUT_D2p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_CLKp

OUT_CLKn

GND

CLOCK LANE

DATA LANE0

DATA LANE1

DATA LANE2

HPD_SRC

GND

I2C_EN/PIN

IN_D1n

IN_D1p

IN_D2n

IN_D2p

IN_D0n

IN_D0p

IN_CLKn

IN_CLKp

SWAP/POL

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Figure 24. SNx5DP159 Swap Function for 48 Pins

Figure 25. SNx5DP159 Swap Function for 40 Pins

The SNx5DP159 can also change the polarity of the input signals. When SWAP/POL is high, the n and p pins on

each lane will swap.Use Register 0x9h bit 6 to swap polarity using I2C. Polarity swap only works for retimer

mode. When the device is in automatic redriver to retimer mode this only works when device is in retimer stage.

If set and data rate falls below 1.0-Gbps in this mode the polarity function will be lost.

l TEXAS INSTRUMENTS 1.0907 1.0900 1.0909 1.0910 Fruuencyle)

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9.3.5 Main Link Inputs

Standard Dual Mode[1] DisplayPort terminations are integrated on all inputs with expected AC coupling

capacitors on board prior to input pins. External terminations are not required. Each input data channel contains

an adaptive or fixed equalizer to compensate for cable or board losses. The voltage at the input pins must be

limited below the absolute maximum ratings. The input pins have incorporated failsafe circuits. The input pins

can be polarity changed through the local I2C register or pin strapping.

9.3.6 Main Link Inputs Debug Tools

There are two methods for debugging a system making sure the inputs to the SNx5DP159 are valid. A TMDS

error checker is implemented that will increment an error counter per data lane. This allows the system

implementer to determine how the link between the source and SNx5DP159 is performing on all three data

lanes. See CSR Bit Field Definitions – RX PATTERN VERIFIER CONTROL/STATUS register in Table 10.

If a high error count is evident, the SNx5DP159 has the ability to provide the general eye quality. A tool is

available that uses the I2C[4] link to download data that can be plotted for an eye diagram. This is available per

data lane.

9.3.7 Receiver Equalizer

Equalizers are used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board

traces or cables. The SNx5DP159 device supports both fixed receiver equalizer (redriver and retimer mode) and

adaptive receive equalizer (retimer mode) by setting the EQ_SEL/A0 pin or through I2C using reg0Ah[5]. When

the EQ_SEL/A0 pin is high, the EQ gain is fixed to 14-dB. The EQ gain will be 7.5-dB if the EQ_SEL/A0 pin is

set low. The SNx5DP159 device operates in adaptive equalizer mode when EQ_SEL/A0 left floating. Using

adaptive equalization the gain will be automatically adjusted based on the data rate to compensate for variable

trace or cable loss. Using the local I2C[4] control, reg0Dh[5:1], the fixed EQ gain can be selected for both data

and clock.

Figure 26. Adaptive EQ Gain Curve

9.3.8 Termination Impedance Control

HDMI2.0[3] standard requires the transmitter termination impedance should be between 75 to 150-Ω. Older

versions of the HDMI standard required no source termination. For HDMI1.4b[2] when data rate over 2 Gbps, the

output performance could be better if the termination value between 150 to 300-Ωwhich was allowed. The

SNx5DP159 supports three different source termination impedances for HDMI1.4b[2] and HDMI2.0[3]. Pin 36,

TX_TERM_CTL, offers a selection option to choose the output termination impedance value. This can be

adjusted by I2C[4]; reg0Bh[4:3] TX_TERM_CTL.

l TEXAS INSTRUMENTS I||—

TMDS DRIVER TMDS RECEIVER

Zo=RT

AVCC

Vcc

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9.3.9 TMDS Outputs

An 1% precision resistor, 7.06-kΩ, is recommended to be connected from Vsadj pin to ground to allow the

differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-

mA current sink capability when no source term is enabled, which provides a typical 500-mV voltage drop across

a 50-Ωtermination resistor. As compliance testing is system dependant this resistor value can be adjusted.

Figure 27. TMDS Driver and Termination Circuit

Referring to Figure 27, if both VCC (device supply) and AVCC (sink termination supply) are powered, the TMDS

output signals are high impedance when OE = low. The normal operating condition is that both supplies are

active. A total of 33-mW of power is consumed by the terminations independent of the OE logical selection.

When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power

source of the device is off and the power source to termination is on, the IO(off) (output leakage current)

specification ensures the leakage current is limited 45-μA or less.

The clock and data lanes VOD can be changed through I2C[4] (see VSWING_CLK and VSWING_DATA in

Table 8 for details). Figure 3 shows the different output voltage based on different Vsadj resistor values.

9.3.9.1 Pre-Emphasis/De-Emphasis

The SNx5DP159 provides De-emphasis as a way to compensate for the ISI loss between the TMDS outputs and

the receiver it is driving. There are two methods to implement this function. When in pin strapping mode the

PRE_SEL pin controls this. The PRE_SEL pin provides –2-dB, or 0-dB de-emphasis, which allows output signal

pre-conditioning to offset interconnect losses from the SNx5DP159 device outputs to a TMDS receiver. TI

recommends setting PRE_SEL at 0 dB while connecting to a receiver through a short PCB route. When pulled to

ground with a 65-kΩresistor –2-dB can be realized, see Figure 9. When using I2C, Reg0Ch[1:0] is used to make

these adjustments.

As there are times true pre-emphasis may be the best solution there are two ways to accomplish this. If pin

strapping is being use the best method is to reduce the Vsadj resistor value increasing the VOD and then pulling

the PRE_SEL pin to ground using the 65-kΩresistor, see Figure 28. If using I2C this can be accomplished using

two methods. First is similar to pin strapping by adjusting the Vsadj resistor value and then implementing –2-dB

de-emphasis. Second method is to set Reg0Ch[7:5] = 011 and the set Reg0Ch[1:0] = 01 which accomplishes the

same pre-emphasis setting. See Figure 29.

*9 TEXAS INSTRUMENTS PRE_SEL= Z

VOD(SS) = 1020mVpp

VOD(PP) = 1200mVpp

1st bit 2nd to N bit

PRE_SEL = Z

Vsadj = 7.06<Q

I2C Reg0Ch[7:5] = 011

Reg0C[1:0] = 01

VOD(SS) = 1150mVpp

VOD(PP) = 1400mVpp

1st bit 2nd to N bit

PRE_SEL = Z

Vsadj = 7.06<Q

PRE_SEL = L

Vsadj = 4.5<Q

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Figure 28. Pre-Emphasis Using Pin Strapping Method

Figure 29. Pre-Emphasis Using I2C Method

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9.4 Device Functional Modes

9.4.1 Retimer Mode

Clock and data recovery circuits (CDR) are used to track, sample and retime the equalized data bit streams. The

CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the

TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1-MHz, will be transferred to the TMDS outputs.

Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce

the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock

above approximately 100-MHz when jitter cleaning is needed for robust operation. The retimer operates at about

1.0 to 6-Gbps DR supporting HDMI2.0[3]. At pixel clock frequency below about 100 MHz, the SNx5DP159

automatically bypasses the internal retimer and operates as a redriver. When the video source changes

resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire

lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period

(that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to

avoid sending invalid clock or data to the downstream receiver.

9.4.2 Redriver Mode

The SNx5DP159 also has a redriver mode that can be enabled through I2C[4]; at offset address 0Ah bits 1:0

DEV_FUNC_MODE. When in this mode, the CDR and PLL are shut off, thus reducing power. Jitter performance

is degraded as the device will now only compensate for ISI loss in the link. In redriver mode HDMI2.0[3]

compliance is not guaranteed as skew compensation and retiming functions are disabled. Excessive random or

phase jitter will not be compensated.

9.4.3 DDC Training for HDMI2.0 Data Rate Monitor

As part of discovery, the source reads the sink’s E-EDID information to understand the sink’s capabilities. Part of

this read is HDMI forum vendor specific data block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine

the data rate supported. Depending upon the value, the source will write to slave address 0xA8 offset 0x20 bit1,

TMDS_CLOCK_RATIO_STATUS. The SNx5DP159 snoops this write to determine the TMDS clock ratio and

thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is 1/40

of TMDS bit period. If a 0 is written, then the TMDS clock is 1/10 of TMDS bit period. The SNx5DP159 will

always default to 1/10 of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. When

HPD_SNK is de-asserted, this bit is reset to default values. If the source does not write this bit the SNx5DP159

will not be configured for TMDS clock 1/40 mode in support of HDMI2.0. As the SNx5DP159 is in link but not

recognized as part of the link it is possible that the source could read the sink EDID where this bit is set and

does not re-write this bit. If the SNx5DP159 has entered a power down state this bit is cleared and does not re-

set on a read. To work properly the bit has to be set again with a write by the source.

9.4.4 DDC Functional Description

The SNx5DP159 solves sink- or source-level issues by implementing a master/slave control mode for the DDC

bus. When the SNx5DP159detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will

transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK

detects the feedback from the downstream device, the SNx5DP159 will pull up or pull down the SDA_SRC bus

and deliver the signal to the source.

The DDC link defaults to 100 kbps, but can be set to various values including 400 kbps by setting the correct

value to address 22h (see Table 3) through the I2C access on the DDC interface. The DDC lines are 5-V

tolerant. The HPD_SRC goes to high impedance when VCC is under low power conditions, < 1.5-V.

NOTE

The SNx5DP159 uses clock stretching for DDC transactions. As there are sources and

sinks that do no perform this function correctly a system may not work correctly as DDC

transactions are incorrectly transmitted/received. To overcome this a snoop configuration

can be implemented where the SDA/SCL from the source is connected directly to the

SDA/SCL sink. The SNx5DP159 will need its SDA_SNK and SCL_SNK pins connected to

this link in order to the SNx5DP159 to configure the TMDS_CLOCK_RATIO_STATUS bit.

Care must be taken when this configuration is being implemented as the voltage levels for

DDC between the source and sink may be different, 3.3 V vs 5 V.

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9.5 Register Maps

9.5.1 DP-HDMI Adaptor ID Buffer

The SNx5DP159 device includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by

the VESA DisplayPort Dual-Mode Standard Version 1.1, accessible by standard I2C[4] protocols through the

DDC interface when the HDMI_SEL/A1 pin is low. The DP-HDMI adapter buffer and extended DDC register for

Type 2 capability is accessed at target addresses 80h (Write) and 81h (Read).

The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII

characters, as shown in Table 3, and supports the WRITE command procedures (accessed at target address

80h) to select the subaddress, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor

Checklist Version 1.0 section 2.3.

Table 3. SNx5DP159 DP-HDMI Adaptor ID Buffer and Extended DDC

Address Description Value HDMI Value DVI Read or

Read/Write

00h

HDMI ID code

44h 00h

Read only

01h 50h 00h

02h 2Dh 00h

03h 48h 00h

04h 44h 00h

05h 4Dh 00h

06h 49h 00h

07h 20h 00h

08h 41h 00h

09h 44h 00h

0Ah 41h 00h

0Bh 50h 00h

0Ch 54h 00h

0Dh 4Fh 00h

0Eh 52h 00h

0Fh 04h 00h

10h

Video Adaptor Identifier

Bit 2:0 ADAPTOR_REVISION 0 0

Read only

Bit 3 Reserved: but 0 for type 2 0 0

Bits 7:4 1010 = Dual mode defined by dual mode[1]

standard 1010 0

11h IEE_OUI first two hex digits 08h 08h Read only

12h IEE_OUI second two hex digits 00h 00h Read only

13h IEE_OUI third two hex digits 28h 28h Read only

14h

Device ID

44h 44h

Read only

15h 50h 50h

16h 31h 31h

17h 35h 35h

18h 39h 39h

19h 00h 00h

1Ah

Hardware revision 02h 02h

Read onlyBits 7:4 major revision 00h 00h

Bits 3:0 minor revision 02h 02h

1Bh Firmware or software major revision 00h 00h Read only

1Ch Firmware or software minor revision 00h 00h Read only

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Table 3. SNx5DP159 DP-HDMI Adaptor ID Buffer and Extended DDC (continued)

Address Description Value HDMI Value DVI Read or

Read/Write

1Dh

Max TMDS clock rate

Default value is F0h in HDMI column

Note: Value determined by taking clock rate and dividing by

2.5 and converting to HEX. For HDMI2.0 extend as if the

clock rate extended instead of its actual method, clock 1/10

DR and not 1/40 DR.

F0h 42h Read only

1Eh

If I2C_DR_CTL = 0 the value is 0Fh →If

DDC_AUX_DR_SEL = 0 the value is 0Fh

If I2C_DR_CTL = 1 the value is 1Fh →If

DDC_AUX_DR_SEL = 1 then value is 1Fh

If I2C_DR_CTL = 0 the value is 0Fh

If I2C_DR_CTL = 1 the value is 1Fh

0Fh 0Fh Read only

1Fh Reserved 00h 00h Write/Read

20h

TMDS_OE

Bit 0: 0 = TMDS_ENABLED (default)

Bit 0: 1 = TMDS_DISABLED

Bits 7:1 Reserved

00h 00h Write/Read

21h

HDMI Pin Control

Bit 0 = CEC_EN

Enables connection between the HDMI CEC pin connected

to the sink and the

CONFIG2 pin to the upstream device + 27-kΩpullup.

0 = CEC_ DISABLED (default)

1 = CEC_ ENABLED

Bits 7:1 = RESERVED

00h 00h Write/Read

22h

Writing a bit pattern to this register that is not defined above

may result in an unpredictable I2C speed selection, but the

adaptor must continue to otherwise work normally. Only

applicable when using I2C-over-AUX transport

01h = 1-Kbps

02h = 5-Kbps

04h = 10-Kbps

08h = 100-kbps

10h = 400-Kbps (RSVD in Dual Mode STND)

On read, the dual-mode cable adaptor returns a value to

indicate the speed currently in use. The default I2C speed

prior to software writing to this register is 100-Kbps.

Illegal write value shall write register default (08h). This

straight DDC

08h 08h Write/Read

23h-FFh Reserved 00h 00h Read

9.5.2 Local I2C Interface Overview

The SCL_CTL and SDA_CTL pins are used for I2C clock and I2C data respectively. The SNx5DP159 I2C

interface conforms to the 2-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000),

and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the start condition from the master device. The 7-bit

device address for the SNx5DP159 device decides by the combination of EQ_SEL/A0 and HDMI_SEL/A1.

Table 4 clarifies the SNx5DP159 device target address.

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Table 4. I2C Device Address Description

A1/A0 SNx5DP159 I2C Device Address ADD

7 (MSB) 6 5 4 3 2 1 0 (W/R)

00 1 0 1 1 1 1 0 0/1 BC/BD

01 1 0 1 1 1 0 1 0/1 BA/BB

10 1 0 1 1 1 0 0 0/1 B8/B9

11 1 0 1 1 0 1 1 0/1 B6/B7

9.5.3 I2C Control Behavior

Follow this procedure to write to the SNx5DP159 device I2C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP159 device

7-bit address and a zero-value W/R bit to indicate a write cycle.

2. The SNx5DP159 device acknowledges the address cycle by combination of A0 and A1.

3. The master presents the subaddress (I2C register within SNx5DP159 device) to be written, consisting of one

byte of data, MSB-first.

4. The SNx5DP159 device acknowledges the subaddress cycle.

5. The master presents the first byte of data to be written to the I2C register.

6. The SNx5DP159 device acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the SNx5DP159 .

8. The master terminates the write operation by generating a stop condition (P).

Follow this procedure to read the SNx5DP159 I2C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP159 7-bit

address and a zero-value W/R bit to indicate a write cycle.

2. The SNx5DP159 device acknowledges the address cycle by combination of A0 and A1.

3. The master presents the subaddress (I2C register within SNx5DP159 device) to be read, consisting of one

byte of data, MSB-first.

4. The SNx5DP159 device acknowledges the subaddress cycle.

5. The master initiates a read operation by generating a start condition (S), followed by the SNx5DP159 7-bit

address and a one-value W/R bit to indicate a read cycle.

6. The SNx5DP159 device acknowledges the address cycle.

7. The SSNx5DP159 device transmit the contents of the memory registers MSB-first starting at the written

subaddress.

8. The SNx5DP159 device will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the

master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.

9. If an ACK is received, the SNx5DP159 device transmits the next byte of data.

10. The master terminates the read operation by generating a stop condition (P).

NOTE

Upon reset, the SNx5DP159 sub-address will always be set to 0x00. When no subaddress

is included in a read operation, the SNx5DP159 subaddress increments from previous

acknowledged read or write data byte. If it is required to read from a subaddress that is

different from the SNx5DP159 internal subaddress, a write operation with only a

subaddress specified is needed before performing the read operation.

Refer to Table 6 for the SNx5DP159 device local I2C register descriptions. Reads from reserved fields return 0s

and writes are ignored.

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9.5.4 I2C Control and Status Registers

Reads from reserved fields return 0, and writes to read-only reserved registers are ignored. Writes to reserved

registers, which are marked with ‘W’, produce unexpected behavior. All addresses not defined by this

specification are considered reserved. Reads from these addresses return 0 and writes will be ignored.

9.5.4.1 Bit Access Tag Conventions

A table of bit descriptions is typically included for each register description that indicates the bit field name, field

description, and the field access tags. The field access tags are described in Table 5.

Table 5. Field Access Tags

ACCESS TAG NAME DESCRIPTION

R Read The field is read by software

W Write The field is written by software

S Set The field is set by a write of one. Writes of 0 to the field have no effect

C Clear The field is cleared by a write of 1. Writes of 0 to the field have no

effect

U Update Hardware may autonomously update this field

NA No access Not accessible or not applicable

9.5.4.2 CSR Bit Field Definitions

9.5.4.2.1 ID Registers

Table 6. ID Registers

ADDRESS BIT DESCRIPTION ACCESS

00h:07h 7:0 DEVICE_ID

These fields return a string of ASCII characters “DP159” followed by three space characters.

Address 0x00 – 0x07 = {0x44”D”, 0x50”P”, 0x31”1”, 0x35”5”, 0x39”9”, 0x20, 0x20, 0x20} R

08h 7:0 REV _ID. This field identifies the device revision.

0000001 – DP159 revision 1 R

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9.5.4.2.2 Misc Control

Table 7. Misc Control

ADDRESS BIT DEFAULT DESCRIPTION ACCESS

09h

7 1’b0

SWAP_EN: This field enables swapping the input main link lanes

0 – Disable (default)

1 – Enable

Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0

RWU

6 1’b0

LANE_POLARITY: swaps the input data and clock lanes polarity.

0 – Disabled: No polarity swap

1 – Swaps the input data and clock lane polarity

Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0. This

feature is only valid when in retimer mode.

RWU

5:4 2'b00 Reserved R

3 1’b0 PD_EN

0 – Normal working (default)

1 – Forced power-down by I2C, lowest power state RW

2 1’b0 HPD_AUTO_PWRDWN_DISABLE

0 – Automatically enters power down mode based on HPD_SNK (default)

1 – Will not automatically enter power mode based upon HPD_SNK RW

1:0 2’b10

I2C_DR_CTL. I2C data rate supported for configuring device

00 – 5-kbps

01 – 10-kbps

10 – 100-kbps (default)

11 – 400-kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling 400

Kbps mode)

0Ah

7 1’b0 Application Mode Selection

0 – Source (default) - Set the adaptive EQ mid point to between 6.5-dB and 7.5-dB

1 – Sink - Sets the adaptive EQ starting point to between 12-dB and 13-dB RW

6 1’b0

HPDSNK_GATE_EN: This field sets the functional relationship between HPD_SNK and

HPD_SRC.

0 – HPD_SNK passed through to the HPD_SRC (default)

1 – HPD_SNK will not pass through to the HPD_SRC.

5 1’b1

EQ_ADA_EN: this field enables the equalizer working state.

0 – Fixed EQ

1 – Adaptive EQ (default)

Writes are ignored when I2C_EN/PIN = 0

RWU

4 1’b1 EQ_EN: this field enables the receiver equalizer.

0 – EQ disabled

1 – EQ enable (default) RW

3 1’b1

AUX_BRG_EN: this field enable the AUX bridge working.This is only valid for the 48-pin

package.

0 – AUX bridge disable

1 – AUX bridge enable (default)

RWU

2 1’b0

APPLY_RXTX_CHANGES , Self clearing write-only bit. Writing a 1 to this bit will apply new

slew, tx_term, twpst1, eqen, eqadapten, swing, eqftc, eqlev settings to the clock and data

lanes. Writes to the respective registers do not take immediate effect. This bit does not need

to be written if I2C configuration occurs while OE or hpd_sink are low, I2C power down is

active.

1:0 2’b01

DEV_FUNC_MODE: This field selects the device working function mode.

00 – Redriver mode across full range 250 Mbps to 6-Gbps

01 - Automatic redriver to retimer crossover at 1.0 Gbps (default)

10 - Automatic retimer for HDMI2.0

11 - Retimer mode across full range 250 Mbps to 6-Gbps

When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.

Mode Selection Definition: This bit lets the receiver know where the device is located in a system for the

purpose of centering the AEQ point. The SNx5DP159 is targeting the source application, so the default value is

0, which will center the EQ at 6.5 to 7.5-dB depending upon TMDS_CLOCK_RATIO_STATUS value, see

Table 9. If the SNx5DP159 is in a dock or sink application, the value should be changed to a value of 1, which

will center the EQ at 12 to 13-dB depending upon TMDS_CLOCK_RATIO_STATUS value.

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9.5.4.2.3 HDMI Control

Table 8. HDMI Control

ADDRESS BIT DEFAULT DESCRIPTION ACCESS

0Bh

7:6 2’b00 SLEW_CTL. Slew rate control.2’00 is fastest and 2’b11 is slowest

Writes ignored when I2C_EN/PIN = 0 RWU

5 1’b0 HDMI_SEL: Contro; Writes ignored when I2C_EN/PIN = 0l

0 – HDMI (default)

1 – DVI RWU

4:3 2’b00

TX_TERM_CTL: Controls termination for HDMI TX

00 – No termination

01 – 150 to 300-Ω

10 – Reserved

11 – 75 to 150-Ω

Note: Reflects the value of the TX_TERM_CTL pin; Writes ignored when I2C_EN/PIN = 0

RWU

2 1’b0 Reserved R

1 1’b0

TMDS_CLOCK_RATIO_STATUS: This field is updated from snoop of I2C write to slave

address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC interface. When

bit 1 of address 0xA8 offset 0x20 is written to a 1’b1, then this field will be set to a 1’b1.

When bit 1 of address 0xA8 offset 0x20 is written to a 1’b0, then this field will be set to a

1’b0. This field is reset to the default value whenever HPD_SNK is de-asserted for greater

than 2 ms.

0 – TMDS clock is 1/10 of TMDS bit period (default)

1 – TMDS clock is 1/40 of TMDS bit period

RWU

0 1’b0

DDC_TRAIN_SET: This field indicates the DDC training block function status. If disabled,

the device can only work at the HDMI1.4b[2] or DVI mode

0 – DDC training enable (default)

1 – DDC training disable

Note: To force TMDS_CLOCK_RATIO_STATUS to 1, this register bit must be set to 1

which will force the 1/40 mode for HDMI2.0.

0Ch

7:5 3’b000

VSWING_DATA: Data output swing control

000 – Vsadj set

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

4:2 3’b000

VSWING_CLK: Clock Output Swing Control

000 – Vsadj set

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

Note: Default is set by DR, which means standard based swing values but this allows for

the swing to be overridden by selecting one of these values

1:0 2’b00

HDMI_TWPST1. HDMI de-emphasis FIR post-cursor-1 signed tap weight.

00 – No de-emphasis

01 – 2-dB de-emphasis

10 – Reserved

11 – Reserved

RWU

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9.5.4.2.4 Equalization Control Register

Table 9. Equalization Control Register

ADDRESS BIT DEFAULT DESCRIPTION ACCESS

0Dh

7:6 2’b00 Reserved RW

5:3 1’b000

Data Lane EQ – Sets fixed EQ values

HDMI1.4b[2]

000 – 0-dB

001 – 4.5-dB

010 – 6.5-dB

011 – 8.5-dB

100 – 10.5-dB

101 – 12-dB

110 – 14-dB

111 – 16.5-dB

HDMI2.0[3]

000 – 0-dB

001 – 3-dB

010 – 5-dB

011 – 7.5-dB

100 – 9.5-dB

101 – 11-dB

110 – 13-dB

111 – 14.5-dB

2:1 1’b00

Clock Lane EQ - Sets fixed EQ values

HDMI1.4b[2]

00 – 0-dB

01 – 1.5-dB

10 – 3-dB

11 – RSVD

HDMI2.0[3]

00 – 0-dB

01 – 1.5-dB

10 – 3-dB

11 – 4.5-dB

0 1’b0

0 – Clock VOD is half the set value when TMDS_CLOCK_RATIO_STATUS

states in HDMI2.0 mode

1 – Disables TMDS_CLOCK_RATIO_STATUS control of the clock VOD so the

output swing is full swing

9.5.4.2.5 EyeScan Control Register

Table 10. EyeScan Control Register

ADDRESS BITS DEFAULT DESCRIPTION ACCESS

0Eh

7:4 4’b0000 PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once

every cycle of the PRBS generator. 1 bit per lane. R

3:0 4’b0000

PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted

high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are

enabled into the corresponding RX lane. These values are then latched

and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane.

RWU

0Fh 7:4 4’b0000 PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane. RU

3:0 4’b0000 PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane. RU

10h

7 1’b0 PV_CP20. Customer pattern length 20 or 16 bits.

0 – 16 bits

1 – 20 bits RW

6 1’b0 Reserved R

5:3 3’b000

PV_LEN[2:0]. PRBS pattern length

000 – PRBS7

001 – PRBS11

010 – PRBS23

011 – PRBS31

100 – PRBS15

101 – PRBS15

110 – PRBS20

111 – PRBS20

2:0 3’b000

PV_SEL[24:0]. Pattern select control

000 – Disabled

001 – PRBS

010 – Clock

011 – Custom

1xx – Timing only mode with sync pulse spacing defined by PV_LEN

11h 7:0 ‘h00 PV_CP[7:0]. Custom pattern data. RW

12h 7:0 ‘h00 PV_CP[15:8]. Custom pattern data. RW

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Table 10. EyeScan Control Register (continued)

ADDRESS BITS DEFAULT DESCRIPTION ACCESS

13h 7:4 4’b0000 Reserved R

3:0 4’b0000 PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1. RW

14h 7:3 5’b00000 Reserved R

2:0 3’b000 PV_THR[2:0]. Pattern-verifier retain threshold. RW

15h

7 1'b0 DESKEW_CMPLT: Indicates TMDS lane deskew has completed when

high R

6:5 2’b00 Reserved R

4 1’b0 BERT_CLR. Clear BERT counter (on rising edge). RSU

3 1’b0 TST_INTQ_CLR. Clear latched interrupt flag. RSU

2:0 3’b000 TST_SEL[2:0]. Test interrupt source select. RW

16h

7:4 4’b0000 PV_DP_EN[3:0]. Enabled datapath verified based on DP_TST_SEL, 1 bit

per lane. RW

3 1’b0 Reserved R

2:0 3'b000

DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0],

TST_INT[0] and TST_INTQ[0]. PV_DP_EN is non-zero

000 – TMDS disparity or data errors

001 – FIFO errors

010 – FIFO overflow errors

011 – FIFO underflow errors

100 – TMDS deskew status

101 – Reserved

110 – Reserved

111 – Reserved

17h 7:4 4’b0000 TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane RU

3:0 4’b0000 TST_INT[3:0]. Test interrupt flag. 1 bit per lane. RU

18h 7:0 ‘h00 BERT_CNT[7:0]. BERT error count. Lane 0 RU

19h 7:4 4’b0000 Reserved R

3:0 4’b0000 BERT_CNT[11:8]. BERT error count. Lane 0 RU

1Ah 7:0 ‘h00 BERT_CNT[19:12]. BERT error count. Lane 1 RU

1Bh 7:4 4’b0000 Reserved R

3:0 4’b0000 BERT_CNT[23:20]. BERT error count. Lane 1 RU

1Ch 7:0 ‘h00 BERT_CNT[31:24]. BERT error count. Lane 2 RU

1Dh 7:4 4’b0000 Reserved R

3:0 4’b0000 BERT_CNT[35:32]. BERT error count. Lane 2 RU

1Eh 7:0 ‘h00 BERT_CNT[19:12]. BERT error count. Lane 3 RU

1Fh 7:4 4’b0000 Reserved R

3:0 ‘h00 BERT_CNT[23:20]. BERT error count. Lane 3 RU

20h

7:4 4’b0000 Reserved R

3 1'b1 AUX_TX_SR Slew Rate Control for AUX Output RW

2:0 3'b010

AUX_SWING; Swing Control for AUX Output

000 – 270 mV

001 – 355 mV

010 – 450 mV

011 – 535 mV

100 – 625 mV

101 – 710 mV

110 – 800 mV

111 – Not allowed

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

DP159 is designed to accept AC coupled HDMI input signals. The device provides signal conditioning and level

shifting functions to drive a compliant HDMI source connector. DP159 can be used as an DP1.2 retimer, follow

application note SLLA358 for required additional configuration. In many major PC or gaming platforms APU/GPU

can provide AC coupled HDMI 2.0 signals, DP159 is suitable for such platforms.

10.1 Application Information

The DP159 was defined to work in mainly in source applications such as gaming systems, Blu-Ray DVD player,

desktop, notebook or VR. The following sections provide design consideration for various types of applications.

10.1.1 Use Case of SNx5DP159

SNx5DP159 can be used on the motherboard and dongle applications. The following use case diagrams show

the connection of AUX and DDC between source side and sink side. The control pin pull up and pull down

resistors are shown from reference. If a high is needed only use the pull up. If a low is needed only use the pull

down. If mid level is to be selected do not use either resistors and leave the pin floating/No connect. The 6.5-KΩ

Vsadj resistor value shown is explained further in the compliance section, for the RSB package.

The DP159 was defined to work in mainly in source applications such as gaming systems, Blu-Ray DVD player,

Desktop, Notebook or VR. The following sections provide design consideration for various types of applications.

Figure 30 shows the original connection of SNx5DP159 on motherboard through the DDC channel. The DDC DR

default is 100-kHz and is capable to adjust to 400-kHz.

‘5‘ TEXAS INSTRUMENTS E LE9

40-Pin

Dual Mode GPU/DP TX

or AC coupled HDMI TX

HDMI/DVI

Receptacle

IN_CLKp OUT_CLKp

IN_D1p OUT_D1p

IN_D0p OUT_D0p

OUT_D2n

IN_D2p

HPD_SNK

SDA_SNK

SCL_SNK

VSADJ

0.1uF

6.5<Q

ML0p

ML1p

ML2p

ML3p

65lQ

0.1uF

HPD HPD_SRC

2<Q

Optional

TMDS_D2p

HPD

DDC_SDA

DDC_SCL

IN_D2n

0.1uF

ML0n

0.1uF

ML1n

ML2n

ML3n IN_CLKn

IN_D1n

IN_D0n

2<Q

DDC_SCL

DDC_SDA

2<Q

SDA_SRC

SCL_SRC

OUT_D2p

OUT_CLKn

OUT_D1n

OUT_D0n

TMDS_D2n

TMDS_D0p

TMDS_D0n

TMDS_D1p

TMDS_D1n

TMDS_CLKp

TMDS_CLKn

GND1

GND3

GND6

GND2

GND4

GND5

0.01uF

65lQ

65lQ65lQ

I2C_EN/PIN

PRE_SEL

EQ_SEL/A0

HDMI_SEL/A1

SLEW_CTL

2<Q

I2C_SCL

I2C_SDA SDA_CTL

SCL_CTL

100<Q

CAD_DET

0.1uF0.1uF 10uF

VCC

CECCEC

VDD

12 19 20 31 40

VCC

VDD

VCC

VDD

GND

THERMAL PAD

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

3.3V

VCC

0.1uF 0.01uF0.01uF 10uF

VDD

0.1uF0.1uF0.1uF

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Application Information (continued)

Figure 30. Implementation for Motherboard 1

‘5‘ TEXAS INSTRUMENTS < iii”="">

SNx5DP159RGZ

Dual Mode GPU/DP TX

or AC coupled HDMI TX

HDMI/DVI

Receptacle

IN_CLKp OUT_CLKp

IN_D1p OUT_D1p

IN_D0p OUT_D0p

OUT_D2n

IN_D2p

HPD_SNK

SDA_SNK

SCL_SNK

VSADJ

0.1uF

7<Q

ML0p

ML1p

ML2p

ML3p

65lQ1DQ

0.1uF

AUXp

AUXn

HPD HPD_SRC

2<Q

Optional

TMDS_D2p

HPD

DDC_SDA

DDC_SCL

IN_D2n

0.1uF

ML0n

0.1uF

ML1n

ML2n

ML3n IN_CLKn

IN_D1n

IN_D0n

2<Q

0.1uF

2<Q

DDC_SCL

DDC_SDA

2<Q

AUX_SRCp

AUX_SRCn

SDA_SRC

SCL_SRC

OUT_D2p

OUT_CLKn

OUT_D1n

OUT_D0n

34 TMDS_D2n

TMDS_D0p

TMDS_D0n

TMDS_D1p

TMDS_D1n

TMDS_CLKp

TMDS_CLKn

46 39

GND1

GND3

GND6

GND2

GND4

GND5

0.01uF

65lQ

SWAP/POL

I2C_EN/PIN

PRE_SEL

EQ_SEL/A0

HDMI_SEL/A1

TX_TERM_CTL

SLEW_CTL

2<Q

I2C_SCL

I2C_SDA SDA_CTL

SCL_CTL

100<Q

CAD_DET

0.1uF0.1uF 10uF

VCC_3.3V

CECCEC

VDD_1.1V

14 23 24 37 48

VCC_3.3V

GND

VCC

VDD

VCC

VDD

GND

THERMAL PAD

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

VCC_3.3V

0.1uF 0.01uF0.01uF 10uF

VDD_1.1V

0.1uF0.1uF0.1uF

Note 1

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Application Information (continued)

Figure 31 shows the connection for both DDC and AUX GPU connections with the SNx5DP159RGZ. Only one

can be implemented at a time. Only the RGZ package supports the I2C-over-AUX implementation. The control

pin pull up and pull down resistors are shown for reference. If a high is needed only use the pull up. If a low is

needed only use the pull down. If mid level is to be selected do not use either resistors and leave the pin

floating/No connect.

Note 1: For applications where the GPU or Sink does not support clock stretching the DDC lines from the GPU/DP TX

should bypass the SCL_SRC and SDA_SRC but still connect to the SCL_SNK and SDA_SNK pins on the DP159.

The SCL_SRC and SDA_SRC pins must be pulled to ground. Note that if the GPU/DP TX cannot support the 5V

DDC lines from the connector, a level shifter is needed to step down the 5V signals to the voltage level the GPU/DP

TX can support.

Figure 31. Implementation for Motherboard 2

{L} TEXAS INSTRUMENTS Dongle

SNx5DP159RGZ

DisplayPort

Plug

HDMI/DVI

Receptacle

IN_CLKp OUT_CLKp

IN_D1p OUT_D1p

IN_D0p OUT_D0p

OUT_D2n

IN_D2p

HPD_SNK

SDA_SNK

SCL_SNK

VSADJ

0.1uF

7.06<Q

ML0p

ML1p

ML2p

ML3p

65lQ

1DQ

0.1uF

HPD HPD_SRC

2<Q

TMDS_D2p

HPD

DDC_SDA

DDC_SCL

IN_D2n

0.1uF

ML0n

0.1uF

ML1n

ML2n

ML3n IN_CLKn

IN_D1n

IN_D0n

2<Q

AUX_CHp/DDC_CLK

2<Q

AUX_SRCp

AUX_SRCn

SDA_SRC

SCL_SRC

OUT_D2p

OUT_CLKn

OUT_D1n

OUT_D0n

34 TMDS_D2n

TMDS_D0p

TMDS_D0n

TMDS_D1p

TMDS_D1n

TMDS_CLKp

TMDS_CLKn

433

GND1

GND3

GND6

GND2

GND4

GND5

0.01uF

65lQ

65lQ65lQ

SWAP/POL

I2C_EN/PIN

PRE_SEL

EQ_SEL/A0

HDMI_SEL/A1

TX_TERM_CTL

SLEW_CTL

DP_PWR

3.3V

100<Q

SDA_CTL

SCL_CTL

100<Q

CONFIG1

(CAD_DET)

0.1uF0.1uF 10uF

DP_PWR

3.3V

CEC

CONFIG2

(CEC)

VDD_1.1V

14 23 24 37 48

DP_PWR

3.3V

VCC

VDD

VCC

VDD

GND

THERMAL PAD

Dongle

AUX_CHn/DDC_DATA

DP_PWR

DP_PWR_RTN

DP_PWR

3.3V

DP_PWR

3.3V

V-REG

VDD_1.1V 5V

DP_PWR

3.3V

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

GND1

GND3

DP_PWR_RTN

GND2

GND4

GND5

CEC_EN

HDMI Adaptor Only

CEC_EN CEC_EN

CEC

1DQ0.01uF

GND

DP_PWR

3.3V

5VCC 18

DP_PWR

3.3V

27<Q

NC for DVI

27K installed for

HDMI

0.1uF 0.01uF0.01uF 10uF

VDD_1.1V

0.1uF0.1uF0.1uF

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Application Information (continued)

Figure 32 shows the SNx5DP159 in the dongle application. It uses the unified structure on DisplayPort

connector. SNx5DP159 has to identify if the signal comes from DDC or from AUX in I2C-over-AUX format. Due to

the AUX channel needed, use only the RGZ package for this application.

Figure 32. SNx5DP159 in Dongle Application

10.1.2 DDC Pullup Resistors

NOTE

This section is for information only and subject to change depending upon system

implementation.

TEXAS INSTRUMENTS R 7 “ Isink T : ><>

V(t) VCC 1 e

æ ö

ç ÷

= ´ -

ç ÷

è ø

T k RC= ´

up(min)

VCC

RIsink

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Application Information (continued)

The pullup resistor value is determined by two requirements:

A. The maximum sink current of the I2C buffer:

The maximum sink current is 3-mA or slightly higher for an I2C driver supporting standard-mode I2C[4]

operation.

(1)

B. The maximum transition time on the bus:

The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pullup resistor

value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by solving

for t, the times at which certain voltage thresholds are reached. Different input threshold combinations

introduce different values of t. Table 11 summarizes the possible values of k under different threshold

combinations.

(2)

(3)

Table 11. Value k Upon Different Input Threshold Voltages

Vth–\Vth+ 0.7 VCC 0.65 VCC 0.6 VCC 0.55 VCC 0.5 VCC 0.45 VCC 0.4 VCC 0.35 VCC 0.3 VCC

0.1 VCC 1.0986 0.9445 0.8109 0.6931 0.5878 0.4925 0.4055 0.3254 0.2513

0.15 VCC 1.0415 0.8873 0.7538 0.6360 0.5306 0.4353 0.3483 0.2683 0.1942

0.2 VCC 0.9808 0.8267 0.6931 0.5754 0.4700 0.3747 0.2877 0.2076 0.1335

0.25 VCC 0.9163 0.7621 0.6286 0.5108 0.4055 0.3102 0.2231 0.1431 0.0690

0.3 VCC 0.8473 0.6931 0.5596 0.4418 0.3365 0.2412 0.1542 0.0741

From Equation 1, Rup(min) = 5.5-V / 3-mA = 1.83-kΩto operate the bus under a 5-V pullup voltage and provide

less than 3-mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA,

is allowed, Rup(min) can be as low as 1.375-kΩ.

If DDC is working at a standard mode of 100-Kbps, the maximum transition time, T, is fixed, 1 μs, and using the

k values from Table 11, the recommended maximum total resistance of the pullup resistors on an I2C bus can be

calculated for different system setups. If DDC is working in a fast mode of 400-kbps, the transition time should be

set at 300 ns, according to I2C[4] specification.

To support the maximum load capacitance specified in the HDMI specification, Ccable(max) = 700-pF, Csource = 50-

pF, Ci= 50-pF, and R(max) can be calculated as shown in Table 12.

Table 12. Pullup Resistor Upon Different Threshold Voltages and 800-pF Loads

Vth–\Vth+ 0.7 VCC 0.65 VCC 0.6 VCC 0.55 VCC 0.5 VCC 0.45 VCC 0.4 VCC 0.35 VCC 0.3 VCC UNIT

0.1 VCC 1.14 1.32 1.54 1.8 2.13 2.54 3.08 3.84 4.97 kΩ

0.15 VCC 1.2 1.41 1.66 1.97 2.36 2.87 3.59 4.66 6.44 kΩ

0.2 VCC 1.27 1.51 1.8 2.17 2.66 3.34 4.35 6.02 9.36 kΩ

0.25 VCC 1.36 1.64 1.99 2.45 3.08 4.03 5.6 8.74 18.12 kΩ

0.3 VCC 1.48 1.8 2.23 2.83 3.72 5.18 8.11 16.87 — kΩ

To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support

a maximum 800-pF load capacitance for a standard-mode I2C bus.

l TEXAS INSTRUMENTS A if : ,J—T ,,,,,, l 7 — if /\ I 7 i ’ f; 1‘: : , ;;l;

40-Pin

Dual Mode GPU/DP TX

or AC coupled HDMI TX

HDMI/DVI

Receptacle

IN_CLKp OUT_CLKp

IN_D1p OUT_D1p

IN_D0p OUT_D0p

OUT_D2n

IN_D2p

HPD_SNK

SDA_SNK

SCL_SNK

VSADJ

0.1uF

6.5<Q

ML0p

ML1p

ML2p

ML3p

65lQ

0.1uF

HPD HPD_SRC

2<Q

Optional

TMDS_D2p

HPD

DDC_SDA

DDC_SCL

IN_D2n

0.1uF

ML0n

0.1uF

ML1n

ML2n

ML3n IN_CLKn

IN_D1n

IN_D0n

2<Q

DDC_SCL

DDC_SDA

2<Q

SDA_SRC

SCL_SRC

OUT_D2p

OUT_CLKn

OUT_D1n

OUT_D0n

TMDS_D2n

TMDS_D0p

TMDS_D0n

TMDS_D1p

TMDS_D1n

TMDS_CLKp

TMDS_CLKn

GND1

GND3

GND6

GND2

GND4

GND5

0.01uF

65lQ

65lQ65lQ

I2C_EN/PIN

PRE_SEL

EQ_SEL/A0

HDMI_SEL/A1

SLEW_CTL

2<Q

I2C_SCL

I2C_SDA SDA_CTL

SCL_CTL

100<Q

CAD_DET

0.1uF0.1uF 10uF

VCC

CECCEC

VDD

12 19 20 31 40

VCC

VDD

VCC

VDD

GND

THERMAL PAD

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

3.3V

VCC

0.1uF 0.01uF0.01uF 10uF

VDD

0.1uF0.1uF0.1uF

SN65DP159

SN75DP159

SLLSEJ2G –JULY 2015–REVISED MARCH 2020

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Product Folder Links: SN65DP159 SN75DP159

10.2 Typical Application

Figure 33. Implementation for Motherboard 1 Schematic

10.2.1 Design Requirements

The SNx5DP159 can be designed into many types of applications. All applications have certain requirements for

the system to work properly. Two voltage rails are required to support the lowest possible power consumption.

The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a processor but the pin needs to

change states after voltage rails have stabilized. Configure the device by using I2C. Pin strapping is provided as

I2C is not available in all cases. Because sources may have different naming conventions, confirm the link

between the source and the SNx5DP159 is correctly mapped. A swap function is provided for the input pins in

case signaling is reversed between the source and the device. For the control pins the values provided below are

when they are being controlled by a micro-controller. If this is not the case then using the 65-kΩfor a pull up for

high, pulled down for low, and left floating for mid level.

{L} TEXAS INSTRUMENTS

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Table 13. Design Parameters

DESIGN PARAMETER VALUE

VCC 3.3 V

VDD 1.1 V

Main link input voltage VID = 75 mVpp to 1.2 Vpp

Control pin Low 65-kΩpulled to GND

Control pin Mid No Connect

Control pin High 65-kΩpulled to 3.3-V

Vsadj resistor 7.06-kΩ

Main link AC decoupling capacitor 75 to 200 nF, recommend 100 nF

10.2.2 Detailed Design Procedure

The SNx5DP159 is a signal conditioner that provides AC coupling to DC coupling level shifting, to support Dual

Mode DisplayPort-capable GPUs or GPUs with AC-coupled drive capability to support HDMI or DVI connectors

and compliance. Signal conditioning is accomplished using receive equalization, retiming, and output driver

configurability. The transmitter drives 2 to 3 inches of board trace and connector.

Designing in the SNx5DP159 requires the following:

• Determine the loss profile between the GPU and the HDMI/DVI connector.

• Based upon the loss profile and signal swing, determine the optimal location for the SNx5DP159, to pass

electrical compliance.

• Use the typical application drawings in Use Case of SNx5DP159 for information on using the AC coupling

capacitors and control pin resistors.

• The DP159 has a receiver adaptive equalizer by default but can also be configured for fixed value

equalization using the EQ_SEL control pin.

• Set the VOD, pre-emphasis, termination, and edge rate levels to support compliance by using the appropriate

Vsadj resistor value and by setting the PRE_SEL, SLEW_CTL, and TX_TERM_CTL control pins.

• Adding pre-emphasis will improve performance on bandwidth limited channels and make steeper transitions.

VOD can be increased to compensate for DC losses and have a sheerer slope. SLEW_CTL handle transition

inclination. Making the transition sharper will improve skew performance.

• The thermal pad must be connected to ground.

• See the schematics in Application Information on recommended decouple capacitors from VCC pins to

ground.

10.2.3 Application Curve

Figure 34. 5.94 Gbps Compliance Eye Mask

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10.3 System Example

10.3.1 Compliance Testing

Compliance testing is very system design specific. Properly designing the system and configuring the DP159 can

help pass transmitter compliance for the system. The following information is the starting point to help prepare for

compliance test. As each system is different there are many features in the DP159 to help tune the circuit. These

include VOD adjust by changing the Vsadj resistor value or using I2C. Other knobs to turn are pre/de-emphasis

and slew rate control. Passing both HDMI2.0 and HDMI1.4b compliance is easier to accomplish when using I2C

as this provides more fine tuning capability.

For the SNx5DP159RGZ:

Pin Strapping

HDMI2.0 & HDMI1.4b

Vsadj Resistor = 7.06-kΩ

PRE_SEL = NC for 0-dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

I2C Control

HDMI2.0 & HDMI1.4b

Vsadj Resistor = 7.06 kΩ

PRE_SEL = Reg0Ch[1:0] = 00 (labeled HDMI_TWPST)

TX_TERM_CTL =

• Reg0Bh[4:3] = 00 →No term; HDMI1.4b < 2Gbps (This may be best value for all HDMI1.4b)

• Reg0Bh[4:3] = 01 →150 to 300 Ω; HDMI1.4b > 2Gbps

• Reg0Bh[4:3] = 11 →75 to 150 Ω; HDMI2.0

SLEW_CTL = Reg0Bh[7:6] = 10

For the SNx5DP159RSB:

Pin Strapping

HDMI2.0 and HDMI1.4b

Vsadj Resistor = 6.5 kΩ

PRE_SEL = L for –2 dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

I2CHDMI2.0

Vsadj Resistor = 6.5 kΩ

PRE_SEL = Reg0Ch[1:0] = 01 (labeled HDMI_TWPST)

TX_TERM_CTL = Reg0Bh[4:3] = 11

SLEW_CTL = Reg0Bh[7:6] = 10

HDMI1.4b

Vsadj Resistor = 6.5 kΩ

VSWING_DATA & VSWING_CLK to -7% = Reg0Ch[7:2] = 111111

PRE_SEL = Reg0Ch[1:0] = 00: (Labeled HDMI_TWPST)

TX_TERM_CTL: Reg0Bh[4:3]

• <2 Gbps = 00 for no termination (This may be best value for all HDMI1.4b)

• >2 Gbps and < 3.4 Gbps = 01 for 150 to 300 Ω

SLEW_CTL = Reg0Bh[7:6] = 10

l TEXAS INSTRUMENTS

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(1) L = LOW, H = HIGH

11 Power Supply Recommendations

11.1 Power Management

To minimize the power consumption of customer application, SNx5DP159 uses dual power supply. VCC is 3.3-V

with 10% range to support the I/O voltage. The VDD is 1.00-V to 1.27-V range to supply the internal digital control

circuit. v operates in two different working states. See Table 14 for conditions for each mode. When OE is

deasserted and then reasserted the device will rest to its default configurations. If different configurations were

programmed using I2C then the device will have to be reprogrammed.

• Power-down mode:

– OE = Low puts the device into its lowest power state by shutting down all function blocks

– When OE is re-asserted the transitions from L →H will create a reset and if the device is programmed

through I2C it will have to be reprogrammed.

– OE = High, HPD_SNK = Low

– Writing a 1 to register 09h[3]

• Normal operation: Working in redriver or retimer

• When HPD asserts, the device CDR and output will enable based on the signal detector circuit result

• HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when VCC over 3-V.

NOTE

When the SNx5DP159 is put into a power down state using the OE pin the I2C registers

are cleared. The TMDS_CLOCK_RATIO_STATUS bit will be cleared in all power down

states. If cleared and HDMI2.0 resolutions are to be supported, the SNx5DP159 expects

the source to write a 1 to this bit location. If this does not happen the PLL will not be set

properly and no video may be evident.

Table 14. Control Logic and Mode of Operation

INPUTS(1) STATUS

MODE

HPD_SNK OE Mode of

Operation HPD_SRC IN_Dx SDA_CTL

SCL_CTL OUT_Dx

OUT_CLK DDC AUX_SRC±

(48 PIN ONLY)

H L X H High-Z Disabled High-Z Disabled Disable Power-down

mode

L H X L High-Z Active High-Z Disabled Disable Power-down

mode

H H X H High-Z Active High-Z Disabled Disable Power-down

mode when a one

is written to 09h[3]

H H Redriver H RX active Active TX active Active Active Normal operation

H H Retimer H RX active Active TX active Active Active Normal operation

(1) L = LOW, H = HIGH

TMDS output termination control impacts the operating power.

Table 15. Control Logic and Mode of Operation

INPUTS(1) STATUS

MODE

HPD_SNK OE Mode of Operation HPD_SRC IN_Dx SDA_CTL

SCL_CTL OUT_Dx

OUT_CLK DDC

H L X H High-Z Disabled High-Z Disabled Power-down mode

L H X L High-Z Active High-Z Disabled Power-down mode

H H X H High-Z Active High-Z Disabled Power-down mode

when a one is written

to 09h[3]

H H Redriver H RX active Active TX active Active Normal operation

H H Retimer H RX active Active TX active Active Normal operation

Layer 1: TMDS signal layer

Layer 2: Ground plane

Layer 3: Power plane

Layer 4: Control signal layer

5 to 10 mils

20 to 40 mils

5 to 10 mils

Layer 1: TMDS signal layer

Layer 2: Ground

Layer 6: Control signal layer

Layer 3: VCC

Layer 4: VDD

Layer 5: Ground

SN65DP159

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TMDS output termination control impacts the operating power.

12 Layout

12.1 Layout Guidelines

TI recommends to use at a minimum a four layer stack up to accomplish a low-EMI PCB design. TI recommends

six layers because the SNx5DP159 is a two voltage rail device.

• Routing the high-speed input DisplayPort traces and TMDS output traces on the top layer avoids the use of

vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the repeater

inputs and from the repeater output to the subsequent receiver circuit. It is important to match the electrical

length of these high speed traces to minimize both inter-pair and intra-pair skew.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

• If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to

the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also

the power and ground plane of each power system can be placed closer together, thus increasing the high-

frequency bypass capacitance significantly.

• The control pin pullup and pulldown resistors are shown in application section for reference. If a high is

needed only use the pull up. If a low is needed only use the pull down. If mid level is to be selected do not

use either resistors and leave the pin floating/No connect.

Figure 35. Recommended 4- or 6-Layer Stack for a Receiver PCB Design

l TEXAS INSTRUMENTS From Source SCL_SRC sm_snc lN_D2p/n HPD_SRC "Lona/n INjnp/n |2C_EN/PIN 6ND , |N_CLKp/n 9:1er VLE Vcc swan Match high spemhricas Ia nglh as dose as possibla w m I: skew. u u: mam EQSEL/AD 5v sDAjNK 5v SCL_SNK speed vases length as close as pusswble m mmmuza skew. DULDZD/n H PDjN K ouLDlp/n OUT_DD p/n Voc 6 ND HDMI_EN/Al ouLchp/n wacevsa and vm decauvlmg up: as close to vi: and van pins as posswlﬂe To Connector

SN65DP159

SN75DP159

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12.2 Layout Examples

Figure 36. Layout Example for the DP159RSB

‘5‘ TEXAS INSTRUMENTS BEES}; ﬂ muium Eu:

100nF

GND

VCC

VDD

VCC

2kQ

65kQ

VCC

100nF

2kQ

65kQ

VCC

GND

From Source

To Sink/Connector

Place VCC and VDD decoupling

caps as close to VCC and VDD

pins as possible

Match High Speed traces

length as close as possible to

minimize Skew

Match High Speed traces

length as close as possible to

minimize Skew

HPD_SRC HPD_SNK

IN_D2p/n

IN_D1p/n

IN_D0p/n

OUT_D2p/n

I2C_EN/PIN

OUT_D1p/n

SDA_SRC

SDA_CTL

SCL_SRC

SCL_CTL

VSADJ

7.06kQ

EQ_SEL/A0

PRE_SEL

100nF

65kQ

VCC

GND

IN_CLKp/n

VDD

2kQ

SDA_SNK

SCL_SNK

VDD

GND

VCC

65kQ

TEST/A1

OUT_D0p/n

OUT_CLKp/n

SWAP/POL

65kQ

VCC

GND

SLEW_CTL

GND

VCC

65kQ

TX_TERM_CTL

NOTE 1

AUX_SRCn

AUX_SRCp

100nF

GND GND

GND

100nF

Note 1: CEC_EN

This pin is either NC or can be

routed to control a CEC enable

FET

SN65DP159

SN75DP159

SLLSEJ2G –JULY 2015–REVISED MARCH 2020

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Product Folder Links: SN65DP159 SN75DP159

Layout Examples (continued)

Figure 37. Layout Example for the DP159RGZ

12.3 Thermal Considerations

On a high-K board: TI recommends to solder the PowerPAD™ onto the thermal land. A thermal land is the area

of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the SNx5DP159 device can

operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.

On a low-K board: For the device to operate across the temperature range on a low-K board, a 1-oz Cu trace

connecting the GND pins to the thermal land must be used. A simulation shows RθJA = 100.84°C/W allowing 545-

mW power dissipation at 70°C ambient temperature.

A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package,

SLMA002.

l TEXAS INSTRUMENTS Am

SN65DP159

SN75DP159

www.ti.com

SLLSEJ2G –JULY 2015–REVISED MARCH 2020

Product Folder Links: SN65DP159 SN75DP159

13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 16. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

SN65DP159 Click here Click here Click here Click here Click here

SN75DP159 Click here Click here Click here Click here Click here

13.2 Documentation Support

13.2.1 Related Documentation

The documents identified in this section are referenced within this data sheet. Most references within the data

sheet use the text identified within the brackets [Document Tag], instead of the complete document title to

simplify the text.

(1) [Dual Mode] VESA DisplayPort Dual-Mode Standard Version 1.1, February 8, 2013

(2) [HDMI1.4b] High-Definition Multimedia Interface Specification Version 1.4b, October, 2011

(3) [HDMI2.0] High-Definition Multimedia Interface Specification Version 2.0a, March, 2015

(4) [I2C] The I2C-Bus specification version 2.1, January, 2000

(5) [HDMI1.4b CTS] High-definition Multimedia Interface CTS for Version 1.4b October, 2011

(6) [HDMI2.0 CTS] High-definition Multimedia Interface CTS for Version 2.0k June, 2015

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

Blu-ray is a trademark of Blu-ray Disc Accociation.

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN65DP159RGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DP159

SN65DP159RGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DP159

SN65DP159RSBR ACTIVE WQFN RSB 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DP159

SN65DP159RSBT ACTIVE WQFN RSB 40 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DP159

SN75DP159RGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 85 75DP159

SN75DP159RGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 85 75DP159

SN75DP159RSBR ACTIVE WQFN RSB 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 75DP159

SN75DP159RSBT ACTIVE WQFN RSB 40 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 75DP159

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+Ko '«Pt» Reel DlameIer A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component Iength K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier Iape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE DOODOOOD ,,,,,,,,,,, ‘ User Direcllon 0' Feed SprockeI Hoies Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN65DP159RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2

SN65DP159RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2

SN65DP159RSBR WQFN RSB 40 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

SN65DP159RSBT WQFN RSB 40 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

SN75DP159RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2

SN75DP159RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2

SN75DP159RSBR WQFN RSB 40 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

SN75DP159RSBT WQFN RSB 40 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Mar-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65DP159RGZR VQFN RGZ 48 2500 367.0 367.0 38.0

SN65DP159RGZT VQFN RGZ 48 250 210.0 185.0 35.0

SN65DP159RSBR WQFN RSB 40 3000 367.0 367.0 35.0

SN65DP159RSBT WQFN RSB 40 250 210.0 185.0 35.0

SN75DP159RGZR VQFN RGZ 48 2500 367.0 367.0 38.0

SN75DP159RGZT VQFN RGZ 48 250 210.0 185.0 35.0

SN75DP159RSBR WQFN RSB 40 3000 367.0 367.0 35.0

SN75DP159RSBT WQFN RSB 40 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Mar-2020

Pack Materials-Page 2

www.ti.com

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

VQFN - 1 mm max heightRGZ 48

PLASTIC QUADFLAT PACK- NO LEAD

7 x 7, 0.5 mm pitch

4224671/A

ﬂTf ﬂfﬂ m_ ﬂ/ \4cﬁL $ t C g i u cccccgccg i uuuuuu nnmmnn ﬂﬂﬂﬂﬂﬂ 48 wuuuuu

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PACKAGE OUTLINE

48X 0.30

0.18

4.1 0.1

48X 0.5

0.3

1 MAX

(0.2) TYP

0.05

0.00

44X 0.5

5.5

2X 5.5

B7.15

6.85 A

7.15

6.85

VQFN - 1 mm max heightRGZ0048B

PLASTIC QUAD FLATPACK - NO LEAD

4218795/B 02/2017

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

12 25

13 24

48 37

(OPTIONAL)

PIN 1 ID

0.1 C B A

0.05

EXPOSED

THERMAL PAD

49 SYMM

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 2.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

48X (0.24)

48X (0.6)

( 0.2) TYP

VIA

44X (0.5)

(6.8)

(1.115)

TYP

( 4.1)

(R0.05)

TYP

(0.685)

TYP

(1.115) TYP

(0.685)

TYP

VQFN - 1 mm max heightRGZ0048B

PLASTIC QUAD FLATPACK - NO LEAD

4218795/B 02/2017

SYMM

13 24

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED METAL

/ 7 £3? “““ VF ﬂﬂﬁgﬂﬂB L r; :E rh {7 ED

www.ti.com

EXAMPLE STENCIL DESIGN

48X (0.6)

48X (0.24)

44X (0.5)

(6.8)

(1.37)

TYP

(R0.05) TYP

(1.17)

(1.37)

TYP

VQFN - 1 mm max heightRGZ0048B

PLASTIC QUAD FLATPACK - NO LEAD

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

SYMM

13 24

GENERIC PACKAGE VIEW RSB 40 WQFN - 0.8 mm max heigm 5 X 5 mm o 4 mm pitch PLASTIC QUAD FLATPACKV N0 LEAD , . Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 4207132/D I TEXAS INSTRI IMFNTS

imam Q --I f 5—1 ﬂ wuuuuiuuuuw E. *3 C 3 ‘ C 3 1 / E 2 7,4 ,,,,, , 9,1 3 ‘ C j ‘ C 3 ‘ C j ‘ C; *3 C mmmmmm‘ 7 D

www.ti.com

PACKAGE OUTLINE

40X 0.25

0.15

40X 0.5

0.3

0.8 MAX

(0.2) TYP

0.05

0.00

36X 0.4

3.6

2X 3.6

3.15 0.1

A5.1

4.9 B

5.1

4.9

WQFN - 0.8 mm max heightRSB0040E

PLASTIC QUAD FLATPACK - NO LEAD

4219096/A 11/2017

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

10 21

11 20

40 31

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.05

EXPOSED

THERMAL PAD

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 2.700

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

40X (0.2)

40X (0.6)

( 0.2) TYP

VIA

36X (0.4)

(4.8)

(1.325)

( 3.15)

(R0.05)

TYP

(1.325)

WQFN - 0.8 mm max heightRSB0040E

PLASTIC QUAD FLATPACK - NO LEAD

4219096/A 11/2017

SYMM

11 20

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

ﬂﬂiﬂﬂﬁ Cb L T 1

www.ti.com

EXAMPLE STENCIL DESIGN

40X (0.6)

40X (0.2)

36X (0.4)

(4.8)

4X ( 1.37)

(0.785)

(R0.05) TYP

(0.785)

WQFN - 0.8 mm max heightRSB0040E

PLASTIC QUAD FLATPACK - NO LEAD

4219096/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 41

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

11 20

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SN65DP159, SN75DP159 Datasheet by Texas Instruments

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