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EVAL-AD5686RSDZ User Guide Datasheet by Analog Devices Inc.
ANALOG
DEVICES
EVAL-AD5686RSDZ User Guide
UG-725
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the AD5686R 16-Bit, Quad Channel, Voltage Output DAC
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B | Page 1 of 13
FEATURES
Full featured evaluation board for the AD5686R
On-board references
Various link options
PC control in conjunction with the Analog Devices, Inc., SDP
EVALUATION KIT CONTENTS
EVAL-AD5686RSDZ board
HARDWARE REQUIRED
EVAL-SDP-CB1Z (SDP-B) board or EVAL-SDP-CS1Z (SDP-S)
board, must be purchased separately
SOFTWARE REQUIRED
ACE evaluation software available for download from the
EVAL-AD5686RSDZ product page
GENERAL DESCRIPTION
This user guide details the operation of the EVAL-
AD5686RSDZ evaluation board for the AD5686R quad-
channel, voltage output, digital-to-analog converter (DAC).
The EVAL-AD5686RSDZ evaluation board is designed to help
users quickly prototype AD5686R circuits and reduce design
time. The AD5686R operates from a single 2.7 V to 5.5 V
supply. The AD5686R incorporates an internal 2.5 V reference
to give an output voltage of 2.5 V or 5 V. The evaluation board
also incorporates additional voltage references.
The EVAL-AD5686RSDZ evaluation board interfaces to the
USB port of a PC via a system demonstration platform (SDP)
board. The analysis control evaluation (ACE) software is
available for download from the EVAL-AD5686RSDZ product
page to use with the evaluation board to allow the user to
program the AD5686R. A PMOD connection is also available to
allow the connection of microcontrollers to the evaluation
board without the SDP board. Note that when a microcontroller
is used through the PMOD connection, the SDP board must be
disconnected, and the user is unable to operate the ACE
software.
The EVAL-AD5686RSDZ evaluation board is compatible with any
Analog Devices SDP board, which can be purchased separately. A
typical connection between the EVAL-AD5686RSDZ and the
EVAL-SDP-CS1Z board (SDP-S controller board) is shown in
Figure 1.
For full details, see the AD5686R data sheet, which must be
consulted in conjunction with this user guide when using the
evaluation board.
EVAL-AD5686RSDZ CONNECTED TO THE SDP-S BOARD
12474-001
Figure 1.
UG-725 EVAL-AD5686RSDZ User Guide
Rev. B | Page 2 of 13
TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents ................................................................... 1
Hardware Required .......................................................................... 1
Software Required ............................................................................ 1
General Description ......................................................................... 1
EVAL -AD5686RSDZ Connected to the SDP-S Board ................ 1
Revision History ............................................................................... 2
Evaluation Board Quick Start Procedures .................................... 3
Installing the Software ................................................................. 3
Initial Setup ................................................................................... 3
Block Diagram And Description .................................................... 4
Memory Map .................................................................................5
Evaluation Board Hardware .............................................................6
Power Supplies ...............................................................................6
LDO Recommendation ................................................................6
Test Points ......................................................................................6
Voltage References.........................................................................6
Link Options ..................................................................................6
Evaluation Board Schematics and Artwork ...................................8
Ordering Information .................................................................... 12
Bill of Materials ........................................................................... 12
REVISION HISTORY
7/2017—Rev. A to Rev. B
Reorganized Layout ............................................................ Universal
Added Evaluation Board Quick Start Procedures Section,
Figure 2, and Figure 3; Renumbered Sequentially ....................... 3
Moved Installing the Software Section and Initial Setup
Section ................................................................................................ 3
Changes to Installing the Software Section and Initial Setup
Section ................................................................................................ 3
Added Block Diagram and Description Section, Figure 4, and
Table 1; Renumbered Sequentially ................................................. 4
Deleted Evaluation Board Software Section, Figure 2, Figure 3
Figure 4, and Figure 5 ...................................................................... 5
Added Memory Map Section, Figure 5, and Figure 6 ................. 5
Deleted Figure 6, Software Operation Section, Write to Input
Register Section, Write to Input and DAC Register Section,
Update DAC Register from Input Register Section, LDAC
Control Section, GAIN Control Section, Reference Control
Section and Power-Down Control Section ................................... 6
Moved Evaluation Board Hardware Section, Power Supplies
Section, LDO Recommendation Section, Test Points Section,
Voltage References Section, Link Options Section, Table 2,
Table 3, and Table 4 ........................................................................... 6
Changes to Table 2 and Table 4 ....................................................... 6
Deleted LDAC Mask Register Section and Full SPI Command
Section ................................................................................................. 7
Moved Table 5 .................................................................................... 7
1/2016—Rev.0 to Rev. A
Changes to Title ................................................................................. 1
Changes to Running the Software Section ..................................... 5
Added Figure 5; Renumbered Sequentially ................................... 5
Changes to Figure 6 ........................................................................... 6
Added LDAC Mask Register Section .............................................. 7
Changes to Figure 7 ........................................................................... 8
Changes to Figure 8 ........................................................................... 9
Changes to Figure 9 and Figure 10 ............................................... 10
Changes to Figure 11 ...................................................................... 11
Changes to Table 5 .......................................................................... 12
5/2015—Revision 0: Initial Version
EVAL-AD5686RSDZ User Guide UG-725
Rev. B | Page 3 of 13
EVALUATION BOARD QUICK START PROCEDURES
INSTALLING THE SOFTWARE
The EVAL-AD5686RSDZ evaluation board uses the ACE
evaluation software, a desktop software application that allows
the evaluation and control of multiple evaluation systems.
The ACE installer installs the necessary SDP drivers and the
Microsoft® .NET Framework 4 by default. The ACE software is
available for download from the EVAL-AD5686RSDZ product
page and must be installed before connecting the SDP board to
the USB port of the PC, to ensure that the SDP board is
recognized with it connects to the PC. For full instructions on
how to install and use this software, see the ACE software pages
on the Analog Devices website.
After the installation is finished, the EVAL-AD5686RSDZ
evaluation board plug in appears when the ACE software is
opened.
INITIAL SETUP
To set up the evaluation board, take the following steps:
1. Connect the evaluation board to the SDP board, and then
connect a USB cable between the SDP board and the PC.
2. Run the ACE application. The EVAL-AD5686RSDZ board
plug-ins appear in the attached hardware section of the
Start tab.
3. Double-click the board plug-in to open the board view
seen in Figure 2.
4. Double-click the AD5686R chip to access the chip block
diagram. This view provides a basic representation of
functionality of the board. The main function blocks of the
board are labeled in Figure 3.
12474-102
Figure 2. Board View of the EVAL-AD5686RSDZ
12474-103
Figure 3. Chip Block Diagram View of the AD5686R
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UG-725 EVAL-AD5686RSDZ User Guide
Rev. B | Page 4 of 13
BLOCK DIAGRAM AND DESCRIPTION
The EVAL-AD5686RSDZ software is organized to appear
similar to the functional block diagram shown in the AD5686R
data sheet. Therefore, correlating the functions on the EVAL-
AD5686RSDZ board with the description in the AD5686R data
sheet is simplified.
A full description of each block, register, and its settings is given
in the AD5686R data sheet.
Some of the blocks and their functions are described in this
section as they pertain to the evaluation board. The block
diagram is shown in Figure 4. Table 1 describes the
functionality of each block.
12474-104
J
ACI
BFDGE H
Figure 4. AD5686R Block Diagram with Labels
Table 1. Block Diagram Functions (See Figure 4 for Labels)
Label
Button/Function
Name Function
A CONFIGURATION
wizard
Used to set the initial configuration of the board. Select the reference gain case from the Output Gain
dropdown box. A gain of 1 is the default. After setting up the initial configuration, click Apply to apply the
values. These settings can be modified at any stage while evaluating the board.
B LDAC and RESET
(GPIO buttons)
Act as external GPIO pulses to the LDAC and RESET pins. The LDAC button transfers data from the input
registers (D) to the DAC registers (E). The RESET button clears all data from the input registers and DAC
registers. These buttons are live; therefore, there is no need to click Apply Changes (J).
C Select a Command The command option dropdown box selects how the data being transferred to the device affects the input
and DAC registers. After a data value is entered in an input register (D), this menu determines the internal
DAC registers affected by updating the input register (D). After a new value is written in the input register
(D), the data can be transferred to the DAC input register or to the DAC input register and the DAC register
simultaneously. If the data is transferred to both registers, the channel DAC register (E) reflects the new value.
D Input Register 0 to
Input Register 3
16-bit data word to be transferred to the device. Click Apply Changes (J) to transfer this 16-bit data word
to the device.
E DAC Register 0 to
DAC Register 3
Displays the value that is currently present in the DAC register on the device. Update the DAC registers by
selecting the appropriate command option or by toggling LDAC (B).
F Software RESET Returns the evaluation board and software to default values. This button is live; therefore, there is no need
to click Apply Changes.
G Load DAC The user can individually control which channel loads the values from the input registers to the DAC registers.
H DAC DAC configuration options provide access to individual channel configuration options such as power-
down options and hardware LDAC mask enable/disable settings.
I Internal Reference Select Enable from this setting to enable the on-chip reference for the board. If Disable is selected, an
external reference must be applied. This control is only available on the AD5686R.
J Apply Changes Applies all modified values to the device. Note that if an evaluation board is not connected, values entered
into the input registers are not transferred to the DAC registers.
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EVAL-AD5686RSDZ User Guide UG-725
Rev. B | Page 5 of 13
MEMORY MAP
All registers are fully accessible from the AD5686R Memory
Map tab, as shown in Figure 5. To navigate to this tab, click
Proceed to Memory Map, shown in Figure 4. This tab allows
registers to be edited at a bit level. The bits shaded in dark gray
are read only bits and cannot be accessed from the ACE
software. All other bits are toggled.
Clicking Apply Changes transfers data to the device. All
changes in this tab correspond to the block diagram. For
example, if the internal register bit is enabled, it displays as
enabled on the block diagram. Any bits or registers that are
shown in bold in the memory map tab are modified values that
have not been transferred to the board (see Figure 6). Click
Apply Changes to transfer the data to the evaluation board.
12474-105
Figure 5. AD5686R Memory Map Tab
12474-106
Figure 6. AD5686R Memory Map with Unapplied Changes in the
DAC0_Input Register
UG-725 EVAL-AD5686RSDZ User Guide
Rev. B | Page 6 of 13
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL -AD5686RSDZ evaluation board provides an on-board,
3.3 V regulator powered through the USB supply. If a different
supply is required or if the board is controlled through the
PMOD, an external supply must be provided via the EXTSUP
connector. See Table 2 for more details.
Both AGND and DGND inputs are provided on the board. The
AGND and DGND planes are connected at one location close to
the AD5686R. To avoid ground loop problems, it is recommended
that AGND and DGND not be connected elsewhere in the system.
All supplies are decoupled to ground with 10 µF tantalum and
0.1 µF ceramic capacitors.
LDO RECOMMENDATION
The ADP7118 low dropout (LDO) linear regulator (maximum
VIN = 20 V) is recommended to power the VDD rail for maximal
performance. A 4.7 Ω resistor in series with the input capacitor
of the ADP7118 adds additional rejection at higher frequencies
to reduce any power supply ripple artifacts below the noise floor.
The ADP162 is recommended for powering the VLOGIC rail.
TEST POINTS
The evaluation board has various test points for debugging and
monitoring purposes. These test points are described in Table 5.
VOLTAGE REFERENCES
The AD5686R provides an internal voltage reference. The
evaluation board provides external references with values of
2.5 V and 5 V. Note that using the ADR3450 requires the use of
an external supply through the EXTSUP connector (see Table 4).
LINK OPTIONS
A number of link options are incorporated in the EVA L-
AD5686RSDZ evaluation board and must be set for the
required operating conditions before using the board. The
functions of these link options are described in Tabl e 4.
Table 3 lists the positions of the different links controlled by the
PC via the USB port. An SDP board operating in single-supply
mode is required.
Table 2. Power Supply Connectors
Connector Label External Voltage Supplies Description
EXTSUP, Pin 1 EXTSUP External analog power supply from 2.7 V to 5.5 V, VDD.
EXTSUP, Pin 2 EXTSUP Analog ground.
EXTREF, Pin 1 EXTREF External voltage reference, VLOGIC. It is 3.3 V when the evaluation board is controlled through the SDP board. It
is 1.8 V to 5.5 V when the evaluation board is controlled through an external connector.
EXTREF, Pin 2 EXTREF Analog ground.
Table 3. Link Options Setup for SDP Control (Default)
Link
Option
PWRSEL 3.3 V
REF Not connected
P1 Not connected
Table 4. Link Functions
Link Description
PWRSEL This link selects the DAC analog voltage source. There are three options, as follows.
The 3.3V option selects the on-board voltage source from the ADP121.
The USB_SUP option selects the USB supply from Pin 5 of the 120-pin connector of the SDP board.
The EXT_SUP option selects an external supply voltage (EXTSUP connector).
REF This link selects the reference source. There are four options, as follows.
The not connected option uses the 2.5 V internal reference.
The EXT_REF option selects an external reference source (EXTREF connector).
The 2.5V option selects the on-board reference from the REF192.
The 5V option selects the on-board reference from the ADR3450. This reference requires an external supply.
P1 The P1 link selects the DAC digital voltage source. There are two options, as follows.
The connected option shorts V
DD
and V
LOGIC
. Use this option only when the SDP board is not connected.
The not connected option opens the connection of VDD and VLOGIC. Use this option when using the SDP board.
EVAL-AD5686RSDZ User Guide UG-725
Rev. B | Page 7 of 13
Table 5. Test Point Descriptions
Test Point Description
AGND Analog ground.
DGND Digital ground.
SCLK/A0 Serial clock input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 50 MHz. This signal is named SCLK_A0 in Figure 7.
SDO/SDA Serial data output. This output daisy-chains a number of AD5686R/AD5685R/AD5684R devices together, or it can be
used for read back. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
This signal is named SDO_SDA in Figure 7.
SYNCB/SCL Active low control input. This is the frame synchronization signal for the input data. When SYNCB goes low, data is
transferred in on the falling edges of the next 24 clocks. This signal is named SYNCB_SCL in Figure 7.
SDIN/A1
Serial data input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the
serial clock input. This signal is named SDIN_A1 in Figure 7.
VOUTA to VOUTD Analog output voltage from DAC A to DAC D, respectively. The output amplifier has rail-to-rail operation.
UG-725 EVAL-AD5686RSDZ User Guide
Rev. B | Page 8 of 13
EVALUATION BOARD SCHEMATICS AND ARTWORK
12474-006
21
E2 1
AGND
1
SCLK_A0
1
SYNCB_SCL
1
SDIN_A1
1
SDO_SDA
R16
R15
R14
R17
R9
R4
R5
R8
5432
1VOUT_D
1
VOUTD
C16 R11
5432
1VOUT_B
1
VOUTB
C15 R10
R6C11
1
VOUTC
5432
1VOUT_C
1
DGND
1
VOUTA
R7C12 5432
1VOUT_A
C6
NP
C8
NP
C3
C1
1
7
6
2
3
115
13 8
14
12
16
15
9
4
10
U4
RESETB
1UF
VREF
SCLK_A0
10UF
AD5686RBRUZ
VOUTD
SDIN_A1
SYNCB_SCL
A1
0
DNI
SDO
0
SDA_0
0
DNI
SDIN
0
SCLK
0
SCL_0
0
DNI
0
A0
0
DNI
DNI
DNI
0.1UF0.1UF
BLK BLK
RED
VOUTA
VREF
VOUTA
SDO_SDA
VDD
VOUTC
VOUTB
RSTSEL
GAIN
LDACB
VOUTC
VDD
VIO
SYNCB_SCL
SCLK_A0
SDO_SDA
SDIN_A1
WHT
WHT
WHT
WHT
RED
DNI
2.0K
330OHM
DNI
1-1337482-0
RED
200PF 2.0K
DNI
VOUTB
DNI
1-1337482-0
DNI
DNIDNI
200PF
DNI
VOUTD
1-1337482-0
DNI
200PF
DNI
200PF
2.0K
SYNCB
RED 1-1337482-0
2.0K
AGND
AGND
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGNDAGND
VOUTB
VREF
RSTSEL
RESET_N
SDIN
SYNC_N
SCLK
VLOGIC
GAIN
LDAC_N
SDO
VOUTD
VOUTC
VDD
GND
VOUTA
5-6: EXT_SUP
5-6: 5V
1-2: EXT_REF
3-4: 2.5V
LABEL LINKS:
LABEL LINKS:
3-4: USB_SUP
1-2: 3.3V
C9
C13
NP
C10
NP
C7
C19
C17
51
4
2
3
U2
2
1
P1
C4
C5
C2
65 43 21
REF
5
64
21
3
U5
65 43 21
PWRSEL
C18
2
1
EXTREF
2
1
EXTSUP
2
5
1
36
4
U3
NP
C20
OSTTC022162
10UF
REF192ESZ
0.1UF
0.1UF 1UF
0.1UF
1UF
10UF
VDD
0.1UF ADR3450ARJZ
VREF
OSTTC022162
TSW-103-08-G-D
TSW-102-08-G-S
VIO
VDD
USB_SUPPLY VDD
TSW-103-08-G-D
USB_SUPPLY
2.2UF
ADP7118AUJZ-3.3
2.2UF
VDD
0.1UF
AGND
AGND AGN D
VOUT
SENSE/ADJEN
GND
VIN
AGNDAGND AGN D
VOUT_FORCE
VOUT_SENSE
VIN
ENABLE
GND_SENSEGND_FORCE
AGNDAGND
AGND
AGND
AGND
AGND AGN D
AGND
SLEEP_N VS
OUTPUT
GND
TP
AGND
Figure 7. EVAL-AD5686RSDZ Schematic—Power Supply and Signal Routes
EVAL-AD5686RSDZ User Guide UG-725
Rev. B | Page 9 of 13
12474-007
AN ACTIVE LOW CHIP SELECT. ENSURE ALSO THAT THE SPI CLK LINE IS NOT HELD
WHEN USING SPI INTERFACE, BE AWARE OF ADDING A PULL UP
HIGH OR LOW BY YOUR BOARD AT POWER UP. FAILURE TO MEET THIS
ON THE SPI_SEL_A/B/C LINES THAT ARE ACTIVE LOW ENABLED
THE SDP CONNECTOR IMPLEMENTS THE E13 CONNECTOR SPECIFICATIONS STANDARD. THIS IS A STANDARD FOR USE ACROSS ADI AND CANNOT BE MODIFIED
REQUIRED (CONNECTED TO BLACKFIN
CONNECTORS ON SDP - PULL UP RESISTORS TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD
BMODE1: PULL UP WITH A 10K RESISTOR TO SET SDP12C BUS 1 IS COMMON ACROSS BOTH
GPIO - USE 12C_0 FIRST)
VIN: USE THIS PIN TO POWER
THE SDP REQUIRES 5V 300MA
WITH EXTERNAL SPI FLASH
SPI_SEL1/SPI_SS MUST BE ONLY USED
RESULT TO A NON-FUNCTIONAL SYSTEM.
VIO: USE TO SET IO VOLTAGE MAX DRAW 20MA
: USE ONLY TO POWER THE EEPROM(3MA MAX DRAW)
MAIN 12C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NOT REQUIRED
BOARD ID EEPROM (24LC32) MUST BE ON I2C BUS 0
SINCE SPI IS A SHARED BUS, ENSURE THAT ANY SPI DEVICE ON DAUGHTER BOARD
IS NOT ACTIVELY DRIVING THE MISO DATA LINE UNLESS PROPERLY ADDRESSED WITH
R13
R20
21
E1
C23C22
C21
R12
NP
C24 C25
R1
R3
R2
7
4
8
5
6
3
2
1
U1
65
116
1
5
6259
7249
7348
87
89
30
29 92
90
32
88
31
91
38
37
85
39
84
83
34
33
82
64
35
41 80
42 79
57
60
10021
99
26 95
27
7114
8113
9112
10 111
110
12
13 108
14 107
15 106
16 105
18 103
19 102
20 101
22
94
24 97
25 96
120
119
70
68
67
6655
54
53
51
50
2
7447
7645
7744
7843
118
117
115
109
104
98
93
86
81
75
69
6358
52
46
40
36
28
23
17
11
6
4
3
56
71
61
SDP
1.8
VIO
DNI
R0603
TOL=1
100K
R0603
TOL=1
100K
R0603
TOL=1
100K
DNI
R0603
100K
4.7UF
0.1UF
0.1UF
USB_SUPPLY
SYNCB
SDIN
FX8-120S-SV(21)
24LC32A-I/ST
TSSOP8
EEPROM
10UF
600OHM
SDP CONNECTOR
VIO
GAIN
RESETB
A0 A1
LDACB
RSTSEL
SCLK
SCL_0
SDO
SDA_0
10UF
0
VIO
DGND
DGND DGND
DGND
AGND AGND
VSS
VCC
WP
A2
A1
A0
SCL
SDA
DGND
DGND
DGND
SPI_SEL_A
CLKOUT
NC
NC
GND
GND
VIO(+3.3V)
GND
PAR_D22
PAR_D20
PAR_D18
PAR_D16
PAR_D15
GND
PAR_D12
PAR_D10
PAR_D8
PAR_D6
GND
PAR_D4
PAR_D2
PAR_D0
PAR_WR_N
PAR_INT
GND
PAR_A2
PAR_A0
PAR_FS2
PAR_CLK
GND
SPORT_RSCLK
SPORT_DR0
SPORT_RFS
SPORT_TFS
SPORT_DT0
SPORT_TSCLK
GND
SPI_MOSI
SPI_MISO
SPI_CLK
GND
SDA_0
SCL_0
GPIO1
GPIO3
GPIO5
GND
GPIO7
TMR_B
TMR_D
NC
GND
NC
NC
NC
WAKE_N
SLEEP_N
GND
UART_TX
BMODE1RESET_IN_N
UART_RX
GND
RESET_OUT_N
EEPROM_A0
NC
NC
NC
GND
NC
NC
TMR_C
TMR_A
GPIO6
GND
GPIO4
GPIO2
GPIO0
SCL_1
SDA_1
GND
SPI_SEL1/SPI_SS_N
SPI_SEL_C_N
SPI_SEL_B_N
GND
SERIAL_INT
SPI_D3
SPI_D2
SPORT_DT1
SPORT_DR1
SPORT_TDV1
SPORT_TDV0
GND
PAR_FS1
PAR_FS3
PAR_A1
PAR_A3
GND
PAR_CS_N
PAR_RD_N
PAR_D1
PAR_D3
PAR_D5
GND
PAR_D7
PAR_D9
PAR_D11
PAR_D13
PAR_D14
GND
PAR_D17
PAR_D19
PAR_D21
PAR_D23
GND
USB_VBUS
GND
GND
NC
VIN
IF VCC WILL BE USED TO POWER THE MODULE, PROVIDE PROTECTION CIRCUIT BLOCK IF POSSIBLE
CONNECT VCC TO 3.3V DIGITAL REFERENCE OR LEAVE FLOATING
CONNECT P1-P4 AND P7-P10 TO SIGNAL BUSES FOR SPI
PMOD INTERFACE TYPE 2A (EXPANDED SPI)
126
10
9
8
7
4
3
2
1
115
PMOD
SDO_SDA
SYNCB_SCL GAIN
RSTSEL
SDIN_A1
SCLK_A0
TSW-106-08-G-D
DNI
LDACB
RESETB
VDD VIO
DGND VCC
GND
P10
P9
P8
P7
VCC
GND
P4
P3
P2
P1
DGND
Figure 8. EVAL-AD5686RSDZ Schematic—SDP Connector
UG-725 EVAL-AD5686RSDZ User Guide
Rev. B | Page 12 of 13
ORDERING INFORMATION
BILL OF MATERIALS
Table 6.
Quantity Reference Designator Description
Supplier/Part
Number1
1 U1 32 kb, I2C serial EEPROM (24LC32) FEC/1331330
1 U2 150 mA, low quiescent current, CMOS linear regulator Analog Devices/ADP121
1 U3 2.5 V, precision micropower, low dropout, low voltage reference Analog Devices/REF192
1 U4 Quad, 16-bit nanoDAC+ with 2 ppm/°C on-chip reference and SPI interface Analog Devices/AD5686R
1 U5 Micropower, high accuracy, 5.0 V voltage reference Analog Devices/ADR3450
6 C1, C2, C5, C6, C18, C25 Capacitors, 0.1 µF, 16 V, 0402 Generic
3 C4, C17, C19 Capacitors, 1 µF, 25 V, X5R Generic
3
C3, C20, C24
Capacitors, 10 µF, 10 V, tantalum
Generic
1 C8 Capacitor, 1 µF, 16 V, tantalum Generic
1 C21 Capacitor, 10 µF, 25 V, X5R Generic
1 C22 Capacitor, 4.7 µF, 25 V, X5R Generic
1 C23 Capacitor, 0.1 µF, 25 V, X8R Generic
1 E1 Ferrite bead, 600 Ω Generic
1
E2
Ferrite bead, 330 Ω
Generic
2 EXTREF, EXTSUP 2-pin terminal blocks Generic
1 P1 2-pin link/jumper Generic
2 REF, PWRSEL 6-pin link/jumpers Generic
1 R12 Resistor, 1.8 Ω, 5%, 1/10 W, thick film chip Generic
1 R13 Resistor, 0 Ω, SMD Generic
4 R4, R8, R14, R16 Resistors, 0 Ω, 5%, 1/16 W, 0603 Generic
2 R2, R3 Resistors, 100 kΩ, 1%, 1/10 W Generic
1 SDP 120-pin female connector FEC/ 1324660 or
Digi-Key H1219-ND
2 AGND, DGND Black test points Generic
4
SCLK_A0, SDIN_A1,
SDO_SDA, SYNCB_SCL
White test points
Generic
4 VOUTA to VOUTD Red test points Generic
19 PMOD, C11, C12, C15,
C16, R1, R5 to R7, R9 to
R11, R15, R17, R20,
VOUT_A to VOUT_D
Do not insert/do not populate Not inserted
1 Generic indicates that any part with the specified value, size, and rating can be used.
ANALOG
DEVICES
www.3nalug.cnm
EVAL-AD5686RSDZ User Guide UG-725
Rev. B | Page 13 of 13
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
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THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
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registered trademarks are the property of their respective owners.
UG12474-0-7/17(B)
