MUN5211DW1, NSBC114EDxx Datasheet by onsemi

0N Semiconductor® www.0nsemi.com nerwork consisting of we resisrors; a series base resistor and a E bascrcminer r islur. The BRT eliminaic these individual ' componcms by imcgmling them in“: n ingle deyice. The use old BRT can reduce borh r yslcm cost and board space. Fealu res f - Simpli es circuil Design - Reduces Board Space - Reduces Component Coum - s and NSV Prefix for Aummoiivc and Other Applicaiions Requiring Unique sire and Comml Change Requirenienls; AECrQlUl Qualified and PPAP Capablc' n H n I These Devices arc PbrFrcc, Halogen FrcC/BFR Free and am RuHs Cunipliunl m o MAXIMUM RATINGS U U U ('rA : 2500, common for Or and 02, unless otherwise noled) Railng Symbol Max Unli W H n ColleciovrBase Vellage Vega 50 Vde ColleciolrEmlfler Vollage V050 50 Vdc ‘L U U Colleclor Cullen! — Conllnuous lc loo mAdc lnpur Forward Voltage VWM, 40 Vde m lnpur Reverse Voltage vmuev, 10 Vde Q Slresses exceedlng Ihose lisied in me Maxlmum Railings lable may damage Ihe ’ o g. devrce. ll any oi mese limus are exceeded deviee luncuonaluy should nol be assumed damage may occur and rellahility may be affected, ORDERING INFORMATION Devlce Package Shlpplng' Muwszllnwme, so‘r—asa 3,000 / Tape 0. Reel SMUNSZHDWWTIG" NSVMUNSZlIDWlTZG' so‘r—asa 3,000 /Tape 0. Reel NSVMUNSZlIDWlTBG' so‘r—asa 10,000/Tape & Reel NSBCHAEDXVSTlG, SOT-563 4,000 /Tape 0. Reel NSVECWHEDXVGTIG' NSBCHAEDXVSTSG SOT-563 5,000 /Tape 0. Reel NSBCHAEDPSTSG SOT-963 5,000 /Tape 0. Reel 1For inlermauon on tape and reel speeilicarions, lncludlng pan orlemafiorl and lape sizes, please reler to our Tape and Reel Packaging Specmcatiorls Brochure, BRDBml/D. m SemieendnelerCempenenu lndnslnee rm mm 1 Pu Aprll. 2019 — Rev. 6
© Semiconductor Components Industries, LLC, 2016
April, 2019 − Rev. 6
1Publication Order Number:
DTC114ED/D
MUN5211DW1,
NSBC114EDXV6,
NSBC114EDP6
Dual NPN Bias Resistor
Transistors
R1 = 10 kW, R2 = 10 kW
NPN Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
•Simplifies Circuit Design
•Reduces Board Space
•Reduces Component Count
•S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable*
•These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Rating Symbol Max Unit
Collector-Base Voltage VCBO 50 Vdc
Collector-Emitter Voltage VCEO 50 Vdc
Collector Current − Continuous IC100 mAdc
Input Forward Voltage VIN(fwd) 40 Vdc
Input Reverse Voltage VIN(rev) 10 Vdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device Package Shipping†
MUN5211DW1T1G,
SMUN5211DW1T1G*
SOT−363 3,000 / Tape & Reel
NSVMUN5211DW1T2G* SOT−363 3,000 / Tape & Reel
NSVMUN5211DW1T3G* SOT−363 10,000 / Tape & Reel
NSBC114EDXV6T1G,
NSVBC114EDXV6T1G*
SOT−563 4,000 / Tape & Reel
NSBC114EDXV6T5G SOT−563 8,000 / Tape & Reel
NSBC114EDP6T5G SOT−963 8,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.onsemi.com
MARKING DIAGRAMS
PIN CONNECTIONS
7A M G
G
1
7A/A = Specific Device Code
M = Date Code*
G= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending up-
on manufacturing location.
SOT−363
CASE 419B
SOT−563
CASE 463A
Q1
Q2
(1)(2)(3)
(6)(5)(4)
R1
R2
R2
R1
SOT−963
CASE 527AD
M
1
A
7A MG
G
1
6
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MUN5211DW1, NSBC114EDXV6, NSBC114EDP6
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
MUN5211DW1 (SOT−363) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 1)
(Note 2)
Derate above 25°C (Note 1)
(Note 2)
PD187
256
1.5
2.0
mW
mW/°C
Thermal Resistance, (Note 1)
Junction to Ambient (Note 2)
RqJA 670
490
°C/W
MUN5211DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation
TA = 25°C (Note 1)
(Note 2)
Derate above 25°C (Note 1)
(Note 2)
PD250
385
2.0
3.0
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1)
(Note 2)
RqJA 493
325
°C/W
Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)
RqJL 188
208
°C/W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
NSBC114EDXV6 (SOT−563) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
PD357
2.9
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1)
RqJA 350
°C/W
NSBC114EDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
PD500
4.0
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1)
RqJA 250
°C/W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
NSBC114EDP6 (SOT−963) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 4)
(Note 5)
Derate above 25°C (Note 4)
(Note 5)
PD231
269
1.9
2.2
MW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 4)
(Note 5)
RqJA 540
464
°C/W
NSBC114EDP6 (SOT−963) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation
TA = 25°C (Note 4)
(Note 5)
Derate above 25°C (Note 4)
(Note 5)
PD339
408
2.7
3.3
MW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 4)
(Note 5)
RqJA 369
306
°C/W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 ×1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
4. FR−4 @ 100 mm2, 1 oz. copper traces, still air.
5. FR−4 @ 500 mm2, 1 oz. copper traces, still air.
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3
ELECTRICAL CHARACTERISTICS (TA=25°C, common for Q1 and Q2, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(VCB =50V, I
E=0)
ICBO
− − 100
nAdc
Collector-Emitter Cutoff Current
(VCE =50V, I
B=0)
ICEO
− − 500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC=0)
IEBO
− − 0.5
mAdc
Collector-Base Breakdown Voltage
(IC=10mA, IE=0)
V(BR)CBO 50 − −
Vdc
Collector-Emitter Breakdown Voltage (Note 6)
(IC= 2.0 mA, IB=0)
V(BR)CEO 50 − −
Vdc
ON CHARACTERISTICS
DC Current Gain (Note 6)
(IC= 5.0 mA, VCE =10V)
hFE 35 60 −
Collector-Emitter Saturation Voltage (Note 6)
(IC= 10 mA, IB= 0.3 mA)
VCE(sat)
− − 0.25
V
Input Voltage (Off)
(VCE = 5.0 V, IC= 100 mA)
Vi(off)
−1.2 −
Vdc
Input Voltage (On)
(VCE = 0.2 V, IC= 10 mA)
Vi(on)
−2.0 −
Vdc
Output Voltage (On)
(VCC = 5.0 V, VB= 2.5 V, RL= 1.0 kW)
VOL
− − 0.2
Vdc
Output Voltage (Off)
(VCC = 5.0 V, VB= 0.5 V, RL= 1.0 kW)
VOH 4.9 − −
Vdc
Input Resistor R1 7.0 10 13 kW
Resistor Ratio R1/R20.8 1.0 1.2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤2%.
Figure 1. Derating Curve
AMBIENT TEMPERATURE (°C)
1251007550250−25−50
0
50
100
150
200
250
300
PD, POWER DISSIPATION (mW)
150
(1) (2)
(1) SOT−363; 1.0 ×1.0 Inch Pad
(2) SOT−563; Minimum Pad
(3) SOT−963; 100 mm2, 1 oz. Copper Trace
350
400
(3)
MUN5211DW1, NSBC114EDXV6, NSBC114EDP6
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4
TYPICAL CHARACTERISTICS
MUN5211DW1, NSBC114EDXV6
Figure 2. VCE(sat) vs. IC
1002030
IC, COLLECTOR CURRENT (mA)
10
1
0.1
40 50
Figure 3. DC Current Gain
Figure 4. Output Capacitance
1
0.1
0.01
0.001
020 4050
IC, COLLECTOR CURRENT (mA)
1000
100
10 1 10 100
IC, COLLECTOR CURRENT (mA)
Figure 5. Output Current vs. Input Voltage
100
10
1
0.1
0.01
0.001 01234
Vin, INPUT VOLTAGE (V)
56 78 910
Figure 6. Input Voltage vs. Output Current
50
010 203040
3.6
2.8
0.4
1.2
0
VR, REVERSE VOLTAGE (V)
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
IC/IB = 10
TA = −25°C
75°C
25°C
VCE = 10 V
TA = 75°C
−25°C
25°C
hFE, DC CURRENT GAIN
f = 10 kHz
IE = 0 A
TA = 25°C
0.8
1.6
2.0
2.4
3.2
Cob, OUTPUT CAPACITANCE (pF)
VO = 5 V
TA = 75°C−25°C
25°C
IC, COLLECTOR CURRENT (mA)
VO = 0.2 V
Vin, INPUT VOLTAGE (V)
TA = 75°C
−25°C
25°C
MUN5211DW1, NSBC114EDXV6, NSBC114EDP6
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TYPICAL CHARACTERISTICS
NSBC114EDP6
Figure 7. VCE(sat) vs. ICFigure 8. DC Current Gain
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
403020 50100
0.01
0.1
1
1001010.1
1
10
100
1000
Figure 9. Output Capacitance Figure 10. Output Current vs. Input Voltage
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
50403020100
0
0.4
0.8
1.2
1.6
2.0
2.4
65743210
0.01
0.1
1
10
100
Figure 11. Input Voltage vs. Output Current
IC, COLLECTOR CURRENT (mA)
4030 5020100
0.1
1
10
100
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
hFE, DC CURRENT GAIN
Cob, OUTPUT CAPACITANCE (pF)
IC, COLLECTOR CURRENT (mA)
Vin, INPUT VOLTAGE (V)
IC/IB = 10
150°C
−55°C
25°C
VCE = 10 V
150°C
−55°C
25°C
f = 10 kHz
IE = 0 A
TA = 25°C
VO = 5 V
150°C
−55°C
25°C
VO = 0.2 V
150°C
−55°C
25°C
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MUN5211DW1, NSBC114EDXV6, NSBC114EDP6
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6
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
Cddd M
123
A1
A
c
654
E
b
6X DIM MIN NOM MAX
MILLIMETERS
A−−− −−− 1.10
A1 0.00 −−− 0.10
ddd
b0.15 0.20 0.25
C0.08 0.15 0.22
D1.80 2.00 2.20
−−− −−− 0.043
0.000 −−− 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.10 0.004
E1 1.15 1.25 1.35
e0.65 BSC
L0.26 0.36 0.46
2.00 2.10 2.20
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.078 0.082 0.086
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.66
6X
DIMENSIONS: MILLIMETERS
0.30
PITCH
2.50
6X
RECOMMENDED
TOP VIEW
SIDE VIEW END VIEW
bbb H
B
SEATING
PLANE
DETAIL A E
A2 0.70 0.90 1.00 0.027 0.035 0.039
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
A-B D
aaa C
2X 3 TIPS
D
E1
D
e
A
2X
aaa H D
2X
D
L
PLANE
DETAIL A
H
GAGE
L2
C
ccc C
A2
6X
777+ 7 + "+77 mchez L www.cnsemi.com
MUN5211DW1, NSBC114EDXV6, NSBC114EDP6
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7
PACKAGE DIMENSIONS
HE
DIM MIN NOM MAX
MILLIMETERS
A0.50 0.55 0.60
b0.17 0.22 0.27
C
D1.50 1.60 1.70
E1.10 1.20 1.30
e0.5 BSC
L0.10 0.20 0.30
1.50 1.60 1.70
0.020 0.021 0.023
0.007 0.009 0.011
0.059 0.062 0.066
0.043 0.047 0.051
0.02 BSC
0.004 0.008 0.012
0.059 0.062 0.066
MIN NOM MAX
INCHES
SOT−563, 6 LEAD
CASE 463A
ISSUE G
eM
0.08 (0.003) X
b6 5 PL
A
C
−X−
−Y−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
D
E
Y
12 3
45
L
6
1.35
0.0531
0.5
0.0197
ǒmm
inchesǓ
SCALE 20:1
0.5
0.0197
1.0
0.0394
0.45
0.0177
0.3
0.0118
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
HE
0.08 0.12 0.18 0.003 0.005 0.007
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MUN5211DW1, NSBC114EDXV6, NSBC114EDP6
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PACKAGE DIMENSIONS
SOT−963
CASE 527AD
ISSUE E
DIM MIN NOM MAX
MILLIMETERS
A0.34 0.37 0.40
b0.10 0.15 0.20
C0.07 0.12 0.17
D0.95 1.00 1.05
E0.75 0.80 0.85
e0.35 BSC
0.95 1.00 1.05
HE
E
D
C
A
HE
123
456
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
X
Y
TOP VIEW
SIDE VIEW
e
b
X0.08
6X
Y
BOTTOM VIEW
6X
0.35
PITCH
1.20
0.20
DIMENSIONS: MILLIMETERS
RECOMMENDED
PACKAGE
OUTLINE
MOUNTING FOOTPRINT*
L0.19 REF
L2 0.05 0.10 0.15
L
6X
L2
6X
6X
0.35
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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