MC14490 Datasheet by onsemi

M01 4490 0N Semimnductor® nnr'll'lr'lr'lfil'l o uuuuwnwu Fe flflflflflflfi > . . 4 r " SIX Debtiulieersperpuekage $th “557519 Imcmal Pullups on All Data Inputs 0 Can Be Used as a Digjml Integrator, System Synelimnizer, or Delay Linc u u u u u u u U lntor (R—C), or External Clock Souree TTL Compatible Dam lnputs/Outputs Single Linc lnput, Denounces Roth “Make" and “Break" Contacts Does Not Require “Form c" (Single Pole Double Thmw) Input Signal Cnseudable fur Longer Tirne Delays Selimitt Trigger on Clock Input (Pin 7) Supply Voltage Range = 3.0 v to 1:; v Chip Complexity: 54o FETS or 136.5 Equivalent crates re Pb—Frcc and am Rnl-lS Compliant NLV Prefix fut Automotive and Other Applieations Requiring Unique Site and Control Change Requirements; AEC—QIUU Qualified and PPAP Capable MAXIMUM RATINGS (Voltages Referenced lo v55) Imcmal 0t nnnnnnnn o uuuuuuuu Thcsc Dcvic Parameter Symbol Value DC Supply Voltage Range VDD —o,5 lo +1a.o Input ol Output Voltage Range Vin» Van. —n.5 to VDD me or Transient) + 0.5 Input Curlent (DC or TranSlenI) per Pm Im :10 Power Dissipation per Package (Note 1) PD 500 Ambient Temperature Range TA —55 to +125 Storage Temperature Range 15.9 — 65 to +150 Lead Temperature (B—Second Solderlng) TL 260 Stresses exceedlng Maxlmum Ratlngs may damage lne devlce. Maxlmum Ratings are slress ratlngs only. Functional oper Recommended Operatlng Condltlons is nol lmplied. Extended exposure to stresses above me Recommended Operating Cond devlce rellability. 1 Temperature Deralmg, Plastie “P and D/DW“ Packages, , 7,0 mW/”C From 6535 To 12st This devlce contains protection cllcunry to guard against damage due to high slallc voltages or electric fields. However, prec taken to avald appliealions of any voltage hlgher than maxlmum rated voltages to this hlgh—lmpedanoe circuit. For proper opera should be constrained to the range v55 5 (VW or VOL“) 5 vDD. Unused lnpuls must always he lied lo an approprlate logic voltage level (9 g,, ellhel v55 or vDD). Unused oulpuls musl be e senrednduelarcenioenenls lnduskles. 1.th 21m 1 Publication May, 2013 — Rev. 10
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 10
1Publication Order Number:
MC14490/D
MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS enhancement
mode devices, and is used for the elimination of extraneous level changes
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact
and generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the
“make” and the “break” of a contact closure. The clock for operation of
the MC14490 is derived from an internal R−C oscillator which requires
only an external capacitor to adjust for the desired operating frequency
(bounce delay). The clock may also be driven from an external clock
source or the oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after powerup, the outputs of the MC14490 are in
indeterminate states.
Features
•Diode Protection on All Inputs
•Six Debouncers Per Package
•Internal Pullups on All Data Inputs
•Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line
•Internal Oscillator (R−C), or External Clock Source
•TTL Compatible Data Inputs/Outputs
•Single Line Input, Debounces Both “Make” and “Break” Contacts
•Does Not Require “Form C” (Single Pole Double Throw) Input Signal
•Cascadable for Longer Time Delays
•Schmitt Trigger on Clock Input (Pin 7)
•Supply Voltage Range = 3.0 V to 18 V
•Chip Complexity: 546 FETs or 136.5 Equivalent Gates
•These Devices are Pb−Free and are RoHS Compliant
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout −0.5 to VDD
+ 0.5
V
Input Current (DC or Transient) per Pin Iin ±10 mA
Power Dissipation, per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
SOIC−16
DW SUFFIX
CASE 751G
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16
1
14490
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14490
ALYWG
16
1
MC14490P
AWLYYWWG
1
1
1
H
MC14490
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Din
Cout
Bin
VDD
OSCout
Fin
Eout
Dout
Cin
Bout
Ain
VSS
OSCin
Fout
Ein
Aout
BLOCK DIAGRAM
Ain1
OSCin7
OSCout9
Bin14
Cin3
Din12
Ein5
Fin10
+VDD
φ1
φ2
OSCILLATOR
AND
TWO-PHASE
CLOCK GENERATOR
DATA
SHIFT LOAD
4-BIT STATIC SHIFT REGISTER 1/2-BIT
DELAY
φ1φ2
φ1φ2
15 Aout
VDD = PIN 16
VSS = PIN 8
φ1φ2
φ1φ2
φ1φ2
φ1φ2
φ1φ2
2Bout
13Cout
4Dout
11Eout
6Fout
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) “1 Level”
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
Oscillator Output Source
(VOH = 2.5 V) Pin 9
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
Debounce Outputs
(VOH = 2.5 V) Pins 2, 4, 6,
(VOH = 4.6 V) 11, 13, 15
(VOH = 9.5 V)
(VOH = 13.5 V)
Oscillator Output Sink
(VOL = 0.4 V) Pin 9
(VOL = 0.5 V)
(VOL = 1.5 V)
Debounce Outputs
(VOL = 0.4 V) Pins 2, 4, 6,
(VOL = 0.5 V) 11, 13, 15
(VOL = 1.5 V)
IOH
5.0
5.0
10
15
– 0.6
– 0.12
– 0.23
– 1.4
−
−
−
−
– 0.5
– 0.1
– 0.2
– 1.2
– 1.5
– 0.3
– 0.8
– 3.0
−
−
−
−
– 0.4
– 0.08
– 0.16
– 1.0
−
−
−
−
mAdc
5.0
5.0
10
15
– 0.9
– 0.19
– 0.6
1.8
−
−
−
−
– 0.75
– 0.16
– 0.5
– 1.5
– 2.2
– 0.46
– 1.2
– 4.5
−
−
−
−
– 0.6
– 0.12
– 0.4
– 1.2
−
−
−
−
IOL
5.0
10
15
0.36
0.9
4.2
−
−
−
0.3
0.75
3.5
0.9
2.3
10
−
−
−
0.24
0.6
2.8
−
−
−
mAdc
5.0
10
15
2.6
4.0
12
−
−
−
2.2
3.3
10
4.0
9.0
35
−
−
−
1.8
2.7
8.1
−
−
−
Input Current
Debounce Inputs (Vin = VDD)
IIH 15 −2.0 −0.2 2.0 −11 mAdc
Input Current Oscillator — Pin 7
(Vin = VSS or VDD)
Iin 15 −± 620 −± 255 ± 400 −± 250 mAdc
Pullup Resistor Source Current
Debounce Inputs
(Vin = VSS)
IIL 5.0
10
15
210
400
600
425
840
1250
140
280
415
190
380
570
255
500
750
70
145
215
225
440
660
mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
Quiescent Current
(Vin = VSS or VDD, Iout = 0 mA)
ISS 5.0
10
15
−
−
−
150
280
840
−
−
−
40
90
225
100
225
650
−
−
−
90
180
550
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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MC14490
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SWITCHING CHARACTERISTICS (Note 3) (CL = 50 pF, TA = 25_C)
Characteristic Symbol
VDD
Vdc Min
Typ
(Note 4) Max Unit
Output Rise Time
All Outputs
tTLH 5.0
10
15
−
−
−
180
90
65
360
180
130
ns
Output Fall Time Oscillator Output
Debounce Outputs
tTHL
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
tTHL 5.0
10
15
−
−
−
60
30
20
120
60
40
Propagation Delay Time
Oscillator Input to Debounce Outputs
tPHL 5.0
10
15
−
−
−
285
120
95
570
240
190
ns
tPLH 5.0
10
15
−
−
−
370
160
120
740
320
240
Clock Frequency (50% Duly Cycle)
(External Clock)
fcl 5.0
10
15
−
−
−
2.8
6
9
1.4
3.0
4.5
MHz
Setup Time (See Figure 1) tsu 5.0
10
15
100
80
60
50
40
30
−
−
−
ns
Maximum External Clock Input
Rise and Fall Time
Oscillator Input
tr, tf5.0
10
15
No Limit
ns
Oscillator Frequency
OSCout
Cext ≥ 100 pF*
Note: These equations are intended to be a design guide.
Laboratory experimentation may be required. Formulas are typically
± 15% of actual frequencies.
fosc, typ
5.0
10
15
1.5
Cext (in mF)
4.5
Cext (in mF)
6.5
Cext (in mF)
Hz
3. The formulas given are for the typical characteristics only at 25_C.
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
*POWER−DOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turn−off time of the power supply must not be faster than t = (VDD − VSS) Cext /(10 mA). For example, If VDD − VSS = 15
V and Cext = 1 mF, the power supply must turn off no faster than t = (15 V) (1 mF) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this
possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
Figure 1. Switching Waveforms Figure 2. Discharge Protection During Power Down
OSCin
Aout
Aout
OSCin
Ain
VDD
0 V
VDD
0 V
VDD
0 V
50%
90%
50% 10%
tr
tf
tPHL
90%
10% 50%
50%
tsu
50%
D1 D2Cext
9
7
OSCin OSCout
MC14490
tPLH
VDD VDD
MC14490
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5
THEORY OF OPERATION
The MC14490 Hex Contact Bounce Eliminator is
basically a digital integrator. The circuit can integrate both
up and down. This enables the circuit to eliminate bounce on
both the leading and trailing edges of the signal, shown in the
timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
4−1/2−bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in
Figure 4. The shift register requires a series of timing pulses
in order to shift the input signal into each shift register
location. These timing pulses (the clock signal) are
represented in the upper waveform of Figure 3. Each of the
six Bounce Eliminator circuits has an internal resistor as
shown in Figure 4. A pullup resistor was incorporated rather
than a pulldown resistor in order to implement switched
ground input signals, such as those coming from relay
contacts and push buttons. By switching ground, rather than
a power supply lead, system faults (such as shorts to ground
on the signal input leads) will not cause excessive currents
in the wiring and contacts. Signal lead shorts to ground are
much more probable than shorts to a power supply lead.
When the relay contact is closed, (see Figure 4) the low
level is inverted, and the shift register is loaded with a high
on each positive edge of the clock signal. To understand the
operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the shift
register to be reset to lows in all four bits — thus starting the
timing sequence over again.
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 3−1/2 to 4−1/2 clock
period delay between the clean input signal and output
signal. In this example there is a delay of 3.8 clock periods
from the beginning of the clean input signal.
After some time period of N clock periods, the contact is
opened and at N + 1 a low is loaded into the first bit. Just after
N+1, when the input bounces low, all bits are set to a high.
At N+2 nothing happens because the input and output are
low and all bits of the shift register are high. At time N+3
and thereafter the input signal is a high, clean signal. At the
positive edge of N+ 6 the output goes high as a result of four
lows being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and
output signals is a function of the difference in bounce
characteristics on the edges of the input signal and the clock
frequency. Since most relay contacts have more bounce
when making as compared to breaking, the overall delay,
counting bounce period, will be greater on the leading edge
of the input signal than on the trailing edge. Thus, the output
signal will be shorter than the input signal — if the leading
edge bounce is included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state.
Referring to Figure 3, a false state is seen to occur three times
at the beginning of the input signal. The input signal goes
low three times before it finally settles down to a valid low
state. The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper
frequency, it may be used by connecting it to the oscillator
input (pin 7). However, if an external clock is not available
the user can place a small capacitor across the oscillator
input and output pins in order to start up an internal clock
source (as shown in Figure 4). The clock signal at the
oscillator output pin may then be used to clock other
MC14490 Bounce Eliminator packages. With the use of the
MC14490, a large number of signals can be cleaned up, with
the requirement of only one small capacitor external to the
Hex Bounce Eliminator packages.
Figure 3. Timing Diagram
OSCin OR OSCout
INPUT
OUTPUT
CONTACT
OPEN
CONTACT
BOUNCING
CONTACT CLOSED
(VALID TRUE SIGNAL) CONTACT
BOUNCING
CONTACT OPEN
N + 7N + 5N + 3N + 1654321
% I ‘— »:>D—T” ” _. f c L_CF T—o— Figure 4. Typical “Form A” Contact Debounce Circuit (Only One Debouncer Shown) F't>:> G i} hllp://onsemi.com 6
MC14490
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Figure 4. Typical “Form A” Contact Debounce Circuit
(Only One Debouncer Shown)
1/2 BIT
DELAY
OSCILLATOR
AND
TWO-PHASE
CLOCK GENERATOR
Cext
OSCout
OSCin
“FORM A”
CONTACT
Ain
1
9
7φ1
φ2
DATA
SHIFT LOAD
4-BIT STATIC SHIFT REGISTER
φ1φ2
φ1φ2
15
Aout
+VDD PULLUP RESISTOR
(INTERNAL)
OPERATING CHARACTERISTICS
The single most important characteristic of the MC14490
is that it works with a single signal lead as an input, making
it directly compatible with mechanical contacts (Form A
and B).
The circuit has a built−in pullup resistor on each input.
The worst case value of the pullup resistor (determined from
the Electrical Characteristics table) is used to calculate the
contact wetting current. If more contact current is required,
an external resistor may be connected between VDD and the
input.
Because of the built−in pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when VDD is
below 5 V. At this voltage, the input should be driven with
paralleled standard gates or by the MC14049 or MC14050
buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow
clock edges, eliminating any need for clock preshaping. In
addition, other MC14490 oscillator inputs can be driven
from a single oscillator output buffered by an MC14050 (see
Figure 5). Up to six MC14490s may be driven by a single
buffer.
The MC14490 is TTL compatible on both the inputs and
the outputs. When VDD is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as
a result of the internal input pullup resistors.
Figure 5. Typical Single Oscillator Debounce System
FROM CONTACTS MC14490 TO SYSTEM
LOGIC
OSCin OSCout
Cext 1/6 MC14050
97
OSCin7 9OSCout
NO CONNECTION
FROM
CONTACTS
TO SYSTEM
LOGIC
MC14490
NO CONNECTION
9OSCout
OSCin7
FROM CONTACTS MC14490 TO SYSTEM
LOGIC
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TYPICAL APPLICATIONS
ASYMMETRICAL TIMING
In applications where different leading and trailing edge
delays are required (such as a fast attack/slow release timer.)
Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be
interchanged. The clock out lead can then be used to feed
clock signals to the other MC14490 packages where the
asymmetrical input/output timing is required.
Figure 6. Fast Attack/Slow Release Circuit
IN OUT
OSCout
MC14011B
OSCin
AB
fC/N
EXTERNAL
CLOCK ÷N
fC
MC14490
LATCHED OUTPUT
The contents of the Bounce Eliminator can be latched by
using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes
low. This will hold the output low even though the input has
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier.
Figure 7. Latched Output Circuit
IN OUT
OSCout
MC14011B
OSCin
MC14490
CLOCK
LATCH = 1
UNLATCH = 0
MULTIPLE TIMING SIGNALS
As shown in Figure 8, the Bounce Eliminator circuits can
be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
One application of the above is shown in Figure 9, where
it is required to have a single pulse output for a single
operation (make) of the push button or relay contact. This
only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in order
to generate the signal AB as shown in Figures 9 and 10. The
signal AB is four clock periods in length. If the inverter is
switched to the A output, the pulse AB will be generated
upon release or break of the contact. With the use of a few
additional parts many different pulses and waveshapes may
be generated.
Figure 8. Multiple Timing Circuit Connections
10
5
12
3
14
1
79
6
11
4
13
2
15 Aout
Bout
Cout
Dout
Eout
Fout
OSCin CLOCK
B.E. 6
B.E. 5
B.E. 4
B.E. 3
B.E. 2
B.E. 1
OSCout
Ain
Bin
Cin
Din
Ein
Fin
MC14490
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Figure 9. Single Pulse Output Circuit
IN
IN
A
OUT
OUT
B
A
BAB
A ≡ACTIVE LOW
B ≡ACTIVE LOW
BE 2
BE 1
Figure 10. Multiple Output Signal Timing Diagram
OSCin OR
OSCout
INPUT
A
B
C
D
E
F
AB
AB
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9
ORDERING INFORMATION
Device Package Shipping†
MC14490DWG SOIC−16
(Pb−Free) 47 Units / Rail
NLV14490DWG*
MC14490DWR2G SOIC−16
(Pb−Free) 1000 / Tape & Reel
NLV14490DWR2G*
MC14490FG SOEIAJ−16
(Pb−Free) 50 Units / Rail
MC14490FELG SOEIAJ−16
(Pb−Free) 2000 Units / Tape & Reel
MC14490PG PDIP−16
(Pb−Free) 500 Units / Rail
NLV14490PG*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14490 PACKAGE DIMENSIONS I—I I_I hf‘wl’fif‘lf‘lf‘lfifl «a.» O ULALAUUUAALI AL 7 e » r—I i \_l ffi: H GILD‘HL ’K 4? * I-QIE {y w IE GIIIHH WWWWWi h‘“ \/ EflL hllp://onsemi.com Io NOTES I 2 a o 5 DIMENSIONINO AND IOLERANCING RER ANSI wow Isaz CONTROLLING DIMENSION INCH DIMENSION LTo CENTER 0E LEADS WHEN FORMED PARALLEL DIMENSION B DOES NoT INCLUDE MOLD FLASH RouNDED CORNERS OPTIONAL DIM MW
MC14490
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10
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
Sufi-54:1 fix IHHHH‘HHHHs *H+ DDDDDDDD7’ L Tmuugmguu
MC14490
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11
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G−03
ISSUE D
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
11.00
16X 0.58
16X
1.62 1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
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