The ADC12 module supports fast, 12-bit analog-to-digital conversions at a rate in excess of 200ksps. The module implements a 12-bit SAR (successive approximation register) core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. A sequence of channels is sampled and converted once with the results written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS (end-of-string) bit.