The blue arrow shows that the general DMA controller can move data from a peripheral, like the ADC, into SRAM by arbitrating access of SRAM with the Ethernet DMA controller. There is plenty of bandwidth on Internal Main Bus 2 because it is 32-bits wide and operates at 50MHz. This interleaved access of SRAM has very little impact on either the Ethernet or the ADC transfers. And finally, the yellow arrow shows how the Data Transfer Controller can move data from a timer over to a DAC output by using the peripheral busses. Again, there is minor arbitration needed on the peripheral bus, but the bandwidth is more than sufficient to minimize interference. So in the end, here are 4 completely independent high-speed transfers occurring, plus 2 more interleaved transfers, showing the use of all five bus masters in the chip: the CPU, Ethernet DMAC, DMAC, DTC, and EXDMA.