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Looking back at the bus matrix, one can see here that the CPU can fetch instructions from any of the three sources while simultaneously accessing data (or operands) from any of the three slaves. This is “enhanced” Harvard architecture, meaning the CPU can execute code from SRAM and access data from Flash if desired. This option allows for very flexible operation, such as accessing data tables in Flash, or downloading code into SRAM and executing it.
PTM Published on: 2012-05-15
