In this slide one can see the operation as a timing diagram. After the master has been started the slave also starts counting automatically and both count registers start down-counting from the initial value. When the slave reaches zero the output will be toggled and an interrupt will be generated. Then the slave channel counter stops and is reloaded with the initial value again, meanwhile the count register of the master still counts down to zero. When this has also reached zero the output pin will be toggled once more. In this PWM mode one does not have to take care about timing issues when re-writing the registers for the duty cycle and the master period. Also, values of 100% and 0% PWM output can be generated easily just by writing in zero or 0xff into the compare registers.