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Timer-Slide11

The TMR register at the bottom of the block diagram is the timer’s mode register. Here one can select which input clock is used, whether the channel should work as a master or as a slave, additional mode settings such as interval or PWM mode, settings for switching the output on or off, and so on. One can also see all the connections to the slave master controller (at the top of the block diagram) to the other channels, which are needed for combined operation mode.

PTM Published on: 2012-04-17