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Timer-Slide16

Here is a block diagram of the PWM mode; at the top is the master channel responsible for the period of the PWM cycle and at the bottom is the slave channel. Both are connected together using internal signals to trigger each other. The master channel defines the period and a complete PWM cycle will be started by triggering the master channel via the TS0n bit, starting the timer count register TCR0. The timer counter register of the slave will be started at the same time, also using the internal trigger. When the timer slave count register reaches zero the duty is over and the output will be toggled from high to low level or vice-versa, however the master channel will still count down to zero. When the master channel reaches zero the complete period is over and the output port is set to one again. The logic of the output port can also be inverted if necessary for a given application.

PTM Published on: 2012-04-17