Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Slide 20 Slide 21 Slide 22 Slide 23 Slide 24 Slide 25 Slide 26 Slide 27 Slide 28 Slide 29 Product List
Timer-Slide10

This slide shows a block diagram of a single channel. In the TAU up to 8 of these single channels are available. There is a selector in the input path which determines the input clock to be used; in this case the choice can be made between input signals CK00 or CK01. On other channels it is possible to select from a maximum of four clocks. The selected clock will be used internally by the channel. Next is the timer counter register “TCR” and the compare register “TDR”, both of which are 16-bits wide. Depending on the mode, a match between these registers or an underflow will directly affect the output controller of each timer channel to generate a square wave output or to simply generate an internal interrupt, one of which is available for each timer channel. On the other side of the input path is the timer input pin with an edge detection circuit inside. Because of the synchronous design of the whole Timer Array Unit, one always needs an internal clock signal fMCK to count external pulses or to do pulse width measurement from the input pin TI0n.

PTM Published on: 2012-04-17