There are counters on the device that monitor the input clock signal to make sure that it is operating correctly. If this logic detects that the clock signal is missing, the logic will automatically bypass the PLL and switch to an internal 10 MHz clock signal. At the same time, the trip input (TZ5) to the ePWM module is pulled low. This trip zone can be enabled in each of the ePWMs to shut down the modules in a safe manner on a missing clock signal detection. The missing clock signal to the detection logic will send an NMI interrupt to both the Master subsystem and the Control subsystem. At the same time, the NMI Watchdog counter is started on both of the subsystems. Ideally, the Control subsystem C28x will respond before the NMI Watchdog times out. This response should be an error handling routine followed by going into an idle mode. If the C28x does not respond in time and the C28x NMI Watchdog times out, then the Control subsystem will be reset. The response for the Master subsystem is quite the same. The biggest difference is if the master NMI Watchdog times out, it will reset the whole device. The missing clock signal detection can be disabled by the M3, should it be desired.