The Control subsystem clock is directly fed from the PLL system clock signal and has a maximum rate of 150 MHz. The M3 can turn off the clock signal to the Control subsystem to conserve power. As in other C2000 devices, the system clock signal out from the CPU is fed to most of the peripherals. This includes the control peripherals, the DMA and the I2C. In the case of Concerto, the NMI Watchdog on the Control subsystem is also clocked by the C28x system clock out signal. Derived from system clock out is the low speed clock signal which is fed to the McBSP, the SCI and the SPI as on C2000 generation devices. A high speed clock signal is used to stretch the external ADC start of conversion signal. Finally, the C28x can disable the clock signal to any module that is not being used to conserve power. Next, what happens if the system clock signal should go missing, this will be presented on the next slide.