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Concerto System Agenda Slide 5

The input to the system clock can be either a single ended clock source on the X1 pin or an external crystal of 4 to 20 MHz on the X1 X2 pins. If a single ended clock source is used, then this can be up to 30 MHz. This clock is then fed into the system PLL. The configuration of the system PLL clock is done by the master or the M3. This includes all PLL controls such as bypass, multiplier, on-off and divider from the PLL output. The control C28x CPU can read these values if it needs to know how the PLL is configured. The C28x can also request write permission to the PLL multiplier and divider using a clock control semaphore. This is typically only done during Flash programming in development when the M3 may not be in use. For example, by Code Composer Studio Flash plug-in programmer. Everything is configurable only by the M3. The output from the PLL sys clock can be monitored on an external pin. By default, this clock is one-fourth of the PLL system clock. The M3 can change this divider, if desired. The output from the PLL system clock is also fed to the Master subsystem through a divider. The divider's default is set to one-quarter of the PLL system clock. The M3 can change this divider but it must not exceed the maximum frequency of 100 MHz. The control system is directly clocked by the PLL system clock. The control subsystem clock is always equal to the PLL system clock. The clock to the control system can, however, be disabled by M3. This might be done to save power, for example. For safety, the registers that can be configured by the M3 are protected by a write protection mechanism and can only be written in privileged mode. The next divider can only be changed by the C28x. The analog subsystem is closely related to the Control subsystem, thus the divider to the ADC clock is controlled by the C28x. The default value at reset is one-eighth of the PLL system clock. The C28x can change this as long as it does not exceed the maximum frequency of 37.5 MHz. On the next slide, different system clock configurations for the device will be shown.

PTM Published on: 2012-07-31