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The dominant failure mechanism of GaN transistors of all types under DC high temperature reverse bias stress is a dynamic upward shift of the on-resistance. The shifting increases with drain bias, and, at high enough bias, the part will eventually parametrically fail when the resistance exceeds the datasheet limits. This effect is caused by electron trapping near the conductive channel, or 2DEG, as well as in the deep buffer layers of the GaN epitaxial film. To quantify this effect, EPC conducted a matrix of HTRB tests at accelerated drain voltages and at three different temperatures. Each leg consisted of 32 eGaN FETs, and the drain voltage during stress ranged from 100 V to 130 V in 10 V increments. A total of 18 such temperature/voltage legs were included in the study. During the HTRB stress, the RDS(on) of each part was monitored in situ at regular intervals in time. RDS(on) has a predictable dependence on time, increasing proportionally to the logarithm of the stress time. A Weibull method was used to calculate various statistical quantities such as the mean time to failure, and the time at which a certain percentage of the parts are expected to fail. The latter is shown in the graph on the right side of this slide for three different failure percentages: 1%, 0.01% and 1 ppm. The diamonds indicate the maximum likelihood estimate, while the error bars give the uncertainty resulting from the 90% confidence intervals on the Weibull parameters. At 100 V, the max rated VDS, the expected time for 1 ppm failure rate from RDS(on) shift exceeds 20 years.
