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The eGaN FETs tested are produced in a wafer level chipscale, or “flipchip” format that eliminates the inefficiencies of conventional semiconductor packaging. All reliability testing is conducted on devices mounted to PCB boards constructed out of FR5 or polyimide. Therefore, test results reflect both the intrinsic reliability of the device as well as its packaging. A conventional power package such as a TO220, LFPAK, or SO8 is needed to protect a silicon-based vertical power device from the environment. EPC’s eGaN FETs chipscale format eliminates the inefficiencies of conventional semiconductor packaging. Package-related parasitic resistance and inductance are eliminated. There are also fewer thermal interfaces that improve the thermal resistance of the eGaN FET compared with comparable MOSFETs. Thermal cycling related wear out is a serious reliability concern for power electronics. Owing to thermal coefficient of expansion mismatch between the semiconductor and the surrounding package materials, mechanical fatigue accumulates at interfaces over time, leading to cracks and ultimate failure. With lower thermal resistance from junction to board, eGaN FETs experience smaller temperature shifts from power cycling, and therefore have a reliability advantage against thermo-mechanical aging. Flipchip mounting eliminates most of the packaging related reliability problems that have been experienced over the lifetime of the silicon power MOSFET. Wirebonds are gone, along with the issues of lift off and heel cracking. Epoxy delamination is gone. Die cracking experienced during the package molding and trimming process is gone. The designer now has a product with minimum waste and fewer mechanical elements to fail.
