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Intel® has two demonstration systems available that highlight the full WDR IP camera reference design, plus just the front-end WDR sensor to DVI output design. These designs both highlight the Aptina MT9M033, the 720p60 WDR CMOS image sensor. Intel® has taken Apical’s (acquired by Arm®) sensor processing IP, including the full image sensor pipeline, and implemented it in a Cyclone® III FPGA used in the Cyclone® III FPGA Development Kit. At this time this is the only available demonstration system for this new WDR CMOS image sensor operating at its full resolution and frame rate. Also, this is a full image sensor pipeline for an HD WDR sensor has been implemented in an FPGA. Again, since this cannot be done on an ASSP or DSP, the FPGA in this case is enabling rapid adoption of the WDR market trend. Even before the MT9M033 sensor was released, Apical (acquired by Arm®) and Intel® partnered to bring this ready-to-implement solution to market. In the DVI output version of this design, all of the image processing has been married to Bitec’s DVI output card and images from this sensor are displayed on a flat-screen monitor with 1280x720 resolution at 60 frames per second. This same system is also the platform for Intel's® full IP camera reference design, which also includes H.264 compression from Eyelytics and an embedded Intel® 10/100/1000 Ethernet controller along with a software real time protocol (RTP) stack running on Intel’s® Nios® II soft-core processor. Finally, also available now is a similar demo/evaluation kit for the AltaSens 1080p sensor. For a camera design which requires 1080p instead of 720p, please contact Intel® to evaluate the AltaSens kit.
