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Surveillance-Slide3

Intel's® vision for a surveillance camera is shown on this slide. With the FPGA at the heart of the system, creating a single-chip surveillance camera is achievable. In a surveillance camera, the FPGA can handle: the sensor interface (glueless for parallel connectivity or high-speed serial); the entire image sensor pipeline, or ISP; the unique image processing for WDR CMOS sensors (e.g. the Aptina MT9M033 WDR CMOS sensor); optimized motor control for pan and tilt; on-chip video compression, scaling, analytics, Ethernet controllers, etc.; and the ability to connect to off-chip encoders or PHY devices for the broadcast, analog, or IP camera markets. Imagine one PCB that could be used to connect to SDI, analog or IP connections simply by “stuffing” options and changing the FPGA design. Note that external RAM is only needed if H.264 encoding or complex video analytics are done on-chip, the Apical (acquired by Arm®) imaging pipeline requires no external memory.

PTM Published on: 2011-08-03