A typical example of NVIC tail chaining can be related to automotive based applications. Automotive systems are highly interrupt driven, with routine actions like applying brakes and taking sharp turns being instances of interrupts. Fast and predictable response to such interrupts for the implementation of technology like anti-lock braking systems (ABS) and automatic stability control is critical for safe operation. These systems are especially complicated since many different such subsystems could deploy at any time. Tail-chaining technology in the NVIC supports interrupts that occur back-to-back, but there could be cases where an interrupt of higher priority could also occur during the stacking (Push) or state restore (Pop) stages of the interrupt being serviced. In traditional interrupt based systems, these stages need to complete before the pending interrupt can take over. As shown in the image, it would take around 30 clock cycles to jump from ISR1 to ISR2. The Cortex-M3 NVIC, on the other hand, provides deterministic response to these possibilities with support for late arrival and pre-emption. In case of the late arrival of a higher priority interrupt during the execution of the stack Push for a previous interrupt, the NVIC immediately fetches a new vector address to service the pending interrupt, as shown in this Figure. The interrupt latency in this case is just restricted to 6 clocks.