The main PLL (PLL0) accepts an input clock frequency in the range of 32 kHz to 25 MHz. The clock source is selected in the CLKSRCSEL register and it can use any one source: the main oscillator, the internal RC oscillator, or the RTC oscillator. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. PLL0 can produce a clock up to the maximum allowed for the CPU, which is 100 MHz. The USB PLL (PLL1) accepts an input clock frequency in the range of 10 MHz to 25 MHz only. PLL1 receives its clock input from the main oscillator only and can be used to provide a fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the possibility of generating the USB clock from PLL0. PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz. If PLL1 is enabled and connected via the PLL1CON register, it is automatically selected to drive the USB subsystem.