In summary, there are some common areas to be considered regarding the clock system when designing with MSP430. First is the high-level clock architecture. There are three fundamental branches to the MSP430 clock tree: ACLK is typically seen as the low frequency clock during low power modes that is by design ultra-low power and as an example would be used to clock a timer peripheral during LPM3 to achieve accurate and periodic wakeup from a watch crystal for the CPU; MCLK is the clock that sources the CPU and is typically the internal high frequency DCO; and the SMCLK branch which is designed to be flexible as it often sources higher frequency peripherals during active mode of the CPU, either from the internal DCO or external source. Another important consideration comes with the use of the 32 kHz crystal or watch crystal. The MSP430 LFXT1 oscillator is created for this purpose and is designed to be very low power. This is not always typical in many MCUs on the market and for some applications may require careful attention to get proper and reliable operation. Use of crystals that have compatible parameters are important but most often layout, assembly and application environment are core factors leading to incorrect watch crystal operation. There are also industry standard tests that are recommended on new designs, such as oscillation allowance testing, to determine safety factor of oscillator system. Following recommendation and performing validation testing are the best preemptive measures that can be taken. Lastly, it is important to understand the features and performance of a given MSP430 device and how that needs to enable the requirements of the application for the desired operation; be it frequency needs, power requirements or feature set. Hand in hand with this understanding is keeping in mind some fundamentals to the behavior of the clock system in a given MSP430 device. Most notable perhaps, is the instant on watch dog upon power up. Failure to realize this behavior can result in long debug efforts that are targeted at incorrect root causes. Also important to highlight are the clock failsafes built into many of the MSP430 oscillators. Incorrect handling of these failsafes can result in incorrect frequencies on chip and erroneous timing operation in the application. Understanding how these work and implementing recommended software to handle as well as leverage these robustness and safety features can provide for solid and reliable application performance.