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The typical CPU duty cycle in any application consists of 3 states: where the CPU is asleep temporarily, CPU wakes to process some instructions, and CPU returns to sleep. The basic building blocks for the MSP430 clock system are an auxiliary clock and a master clock. The auxiliary clock, ACLK, is ultra-low power, low frequency, and is used to source a timer during a sleep state of the CPU. The master clock, or MCLK, is specifically used to source the CPU with a system clock. Power is still important when on, although much higher than for ACLK, but it also must operate at a high clock rate up to the maximum CPU clock at least and it must be capable of ultra-fast wakeup. Wakeup is important because it minimizes the time that the system waits to transition from the low power mode to the active mode to execute instructions quickly and efficiently. The MSP430 clock system’s ability to meet these requirements is what provides the ULP performance, enabling ultra-low power standby power consumption with the CPU off, an ultra-fast wakeup to engage the CPU quickly at a high frequency so that it can then quickly go back to the ULP standby state once the tasks are completed awaiting the next interrupt request.
