Clock management or clock gating allows for the designer to modify peripherals in order to minimize power consumption while determining what features are necessary. This chart shows that by using the system clock gating registers, Run IDD can be reduced up to 33%. Clock gating is the mechanism used to disable the clock tree to any unused peripheral. The bus or peripheral clock runs to all modules, regardless if they are enabled or not. It also saves power by not clocking unused gates. A very significant feature with QE’s ultra low power technology.