Texas Instruments 的 AWR1243 规格书

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AWR1243 Single-Chip 77- and 79-GHz FMCW Transceiver

1 Features

• FMCW transceiver

– Integrated PLL, transmitter, receiver, Baseband,

and ADC

– 76- to 81-GHz coverage with 4 GHz available

bandwidth

– Four receive channels

– Three transmit channels (two can be used

simultaneously)

– Ultra-accurate chirp engine based on fractional-

N PLL

– TX power: 12 dBm

– RX noise figure:

• 14 dB (76 to 77 GHz)

• 15 dB (77 to 81 GHz)

– Phase noise at 1 MHz:

• –95 dBc/Hz (76 to 77 GHz)

• –93 dBc/Hz (77 to 81 GHz)

• Built-in calibration and self-test

– Built-in firmware (ROM)

– Self-calibrating system across process and

temperature

• Host interface

– Control interface with external processor over

SPI

– Data interface with external processor over

MIPI D-PHY and CSI2 V1.1

– Interrupts for fault reporting

•Functional Safety-Compliant

– Developed for functional safety applications

– Documentation available to aid ISO 26262

functional safety system design up to ASIL-D

– Hardware integrity up to ASIL-B

– Safety-related certification

• ISO 26262 certified upto ASIL B by TUV

SUD

• AEC-Q100 qualified

• Device advanced features

– Embedded self-monitoring with no host

processor involvement

– Complex baseband architecture

– Embedded interference detection capability

• Power management

– Built-in LDO network for enhanced PSRR

– I/Os support dual voltage 3.3 V/1.8 V

• Clock source

– Supports externally driven clock (square/sine)

at 40 MHz

– Supports 40 MHz crystal connection with load

capacitors

• Easy hardware design

– 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm

flip chip BGA package for easy assembly and

low-cost PCB design

– Small solution size

• Operating Conditions

– Junction temp range: –40°C to 125°C

AWR1243

SWRS188D – MAY 2017 – REVISED DECEMBER 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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2 Applications

•Automotive Sensor for measuring range, velocity

and angle

•Automated highway driving

•Automatic emergency braking

•Adaptive cruise control

Antenna

Structure SPI/I2C

Power Management Crystal

Interface to

External

Peripherals

CSI2 (4 Lane Data + 1 Clock lane)

Reset

Error

MCU Clock

mmWave Sensor

RX1

RX2

RX3

RX4

TX1

TX2

TX3

External

MCU

Figure 2-1. Autonomous Radar Sensor For Automotive Applications

3 Description

The AWR1243 device is an integrated single-chip FMCW transceiver capable of operation in the 76- to 81-GHz

band. The device enables unprecedented levels of integration in an extremely small form factor. AWR1243 is an

ideal solution for low power, self-monitored, ultra-accurate radar systems in the automotive space.

The AWR1243 device is a self-contained FMCW transceiver single-chip solution that simplifies the

implementation of Automotive Radar sensors in the band of 76 to 81 GHz. It is built on TI’s low-power 45-nm

RFCMOS process, which enables a monolithic implementation of a 3TX, 4RX system with built-in PLL and ADC

converters. Simple programming model changes can enable a wide variety of sensor implementation (Short,

Mid, Long) with the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally,

the device is provided as a complete platform solution including TI reference designs, software drivers, sample

configurations, API guides, and user documentation.

Device Information

PART NUMBER(2) PACKAGE(1) BODY SIZE TRAY / TAPE AND REEL

AWR1243FBIGABLQ1 FCBGA (161) 10.4 mm × 10.4 mm Tray

AWR1243FBIGABLRQ1 Tape and Reel

(1) For more information, see Section 13, Mechanical, Packaging, and Orderable Information.

(2) For more information, see Section 12.1, Device Nomenclature.

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4 Functional Block Diagram

Figure 4-1 shows the functional block diagram of the device.

ADC Buffer

16KB PING/PONG

IF ADC

Digital Front-end

(Decimation filter

chain)

LNA

IF ADC

LNA

IF ADC

LNA

IF ADC

LNA

PA û-

Synth

(20 GHz) Ramp Generator

Osc.

RF Control / BIST

GPADCVMON Temp(B)

SPI/I2C

CSI2

RF/Analog Subsystem

Host control

interface

ADC output

interface

Digital

Synth Cycle

Counter

Phase

Shifter

Control (A)

A. Phase Shift Control:

• 0° / 180° BPM for AWR1243

B. Internal temperature sensor accuracy is ± 7 °C.

Figure 4-1. Functional Block Diagram

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SWRS188D – MAY 2017 – REVISED DECEMBER 2021

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 2

3 Description.......................................................................2

4 Functional Block Diagram.............................................. 3

5 Revision History.............................................................. 5

6 Device Comparison......................................................... 6

6.1 Related Products........................................................ 7

7 Terminal Configuration and Functions..........................8

7.1 Pin Diagram................................................................ 8

7.2 Signal Descriptions................................................... 12

8 Specifications................................................................ 16

8.1 Absolute Maximum Ratings...................................... 16

8.2 ESD Ratings............................................................. 16

8.3 Power-On Hours (POH)............................................ 17

8.4 Recommended Operating Conditions.......................17

8.5 Power Supply Specifications.....................................18

8.6 Power Consumption Summary................................. 19

8.7 RF Specification........................................................20

8.8 Thermal Resistance Characteristics for FCBGA

Package [ABL0161].....................................................21

8.9 Timing and Switching Characteristics....................... 21

9 Detailed Description......................................................33

9.1 Overview................................................................... 33

9.2 Functional Block Diagram......................................... 33

9.3 Subsystems.............................................................. 34

9.4 Other Subsystems.................................................... 37

10 Monitoring and Diagnostics....................................... 39

10.1 Monitoring and Diagnostic Mechanisms................. 39

11 Applications, Implementation, and Layout............... 42

11.1 Application Information............................................42

11.2 Short-, Medium-, and Long-Range Radar ..............42

11.3 Reference Schematic..............................................43

12 Device and Documentation Support..........................44

12.1 Device Nomenclature..............................................44

12.2 Tools and Software................................................. 45

12.3 Documentation Support.......................................... 45

12.4 Support Resources................................................. 45

12.5 Trademarks.............................................................46

12.6 Electrostatic Discharge Caution..............................46

12.7 Glossary..................................................................46

13 Mechanical, Packaging, and Orderable

Information.................................................................... 47

13.1 Packaging Information............................................ 47

13.2 Tray Information for ................................................47

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5 Revision History

Changes from May 1, 2020 to December 8, 2021 (from Revision C (May 2020) to Revision D

(December 2021)) Page

•Global: Updated to reflect Functional Safety-Compliance and relevant certification collateral...........................1

•Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and

Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminology..................................1

•(Features) : Mentioned the specific operating temperature range for the mmWave Sensor.............................. 1

•(Applications) :Revised the figure and updated application links........................................................................2

• (Device Information): Removed a pre-production orderable part number (XA1243FPBGABL) from the table

and its assosiated features. ............................................................................................................................... 2

• Updated/Changed Functional Block Diagram to remove XA1243FPBGABL OPN specific features................. 3

•(Device Comparison) : Removed a row on Functionaly-Safety compliance and instead added a table-note for

this and LVDS Interface; modified the existing table-note on simultaneous TX operation; Additional

information on Device security added.................................................................................................................6

•(Device Comparison) : Updated/Changed RF Specification Receiver from "Max real sampling rate (Msps)" to

"Max real/complex 2x sampling rate (Msps)"; and "Max complex sampling rate (Msps)" to "Max complex 1x

sampling rate (Msps)".........................................................................................................................................6

•(Signal Descriptions): Removed XA1243FPBGABL OPN specific pin functions; updated descriptions for

CLKP and CLKM pins for Reference Oscillator................................................................................................ 12

•(Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and

a table-note for the signal level applied on TX..................................................................................................16

•(Power Supply Specifications): Updated/Changed footnote in Table 8-1 ........................................................ 18

• (Maximum Current Rating at Power Terminals): Updated footnotes section to add estimation assumption for

VIOIN rail.......................................................................................................................................................... 19

•(Average Power Consumption at Power Terminals): Removed 3TX, 4RX power numbers since only 2TX are

operational simultaneously in the device.......................................................................................................... 19

•(RF Specification): Updated/Changed RF Specification Receiver from "A2D sampling rate (complex)" to "ADC

sampling rate (complex 1x)"; and "A2D sampling rate (real)" to "ADC sampling rate (real/complex 2x)"........ 20

•(RF Specification): Updated/Changed the table to remove XA1243FPBGABL specific features.....................20

•(Synchronized Frame Triggering): Updated the maximum pulse width to 4ns................................................. 22

•(Clock Specifications): Updated/Changed Table 8-6 to reflect correct device operating temperature range... 24

•(Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppm..24

•(Switching Characteristics for Output Timing versus Load Capacitance): Updated/Modified the table to

remove Slew Rate = 1 condition; removed a footnote......................................................................................30

•Figure 9-1: Updated the figure to remove XA1243FPBGABL OPN specific features. .....................................33

•(Monitoring and Diagnostic Mechanisms): Added a new section..................................................................... 39

•(Reference Schematics) : Added weblinks to AWR1243 EVM documentation collateral ................................ 43

•(Device Nomenclature):Updated/changed Device Nomenclature ................................................................... 44

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AWR1243

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TEXAS INSTRUMENTS

6 Device Comparison

FUNCTION AWR1243(1) AWR1443 AWR1642 AWR1843

Number of receivers 4 4 4 4

Number of transmitters 3 3 2 3

On-chip memory — 576KB 1.5MB 2MB

Max I/F (Intermediate Frequency) (MHz) 15 5 5 10

Max real/complex 2x sampling rate (Msps) 37.5 12.5 12.5 25

Max complex 1x sampling rate (Msps) 18.75 6.25 6.25 12.5

Device Security(2) — — Yes Yes

Processor

MCU (R4F) — Yes Yes Yes

DSP (C674x) — — Yes Yes

Peripherals

Serial Peripheral Interface (SPI) ports 1 1 2 2

Quad Serial Peripheral Interface (QSPI) — Yes Yes Yes

Inter-Integrated Circuit (I2C) interface — 1 1 1

Controller Area Network (DCAN) interface — Yes Yes Yes

CAN-FD — — Yes Yes

Trace — — Yes Yes

PWM — — Yes Yes

Hardware In Loop (HIL/DMM) — — Yes Yes

GPADC — Yes Yes Yes

LVDS/Debug(3) Yes Yes Yes Yes

CSI2 Yes — — —

Hardware accelerator — Yes — Yes

1-V bypass mode Yes Yes Yes Yes

Cascade (20-GHz sync) — — — —

JTAG — Yes Yes Yes

Number of Tx that can be simultaneously used 2 2 2 3(4)

Per chirp configurable Tx phase shifter — — — Yes

Product

status(5)

PRODUCT PREVIEW (PP),

ADVANCE INFORMATION (AI),

or PRODUCTION DATA (PD)

PD PD PD PD

(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation

for more details.

(2) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part

variants as indicated by the Device Type identifier in Section 3, Device Information table.

(3) The LVDS interface is not a production interface and is only used for debug.

(4) 3 Tx Simultaneous operation is supported only in AWR1843 with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin. Rest of the other devices only support simultaneous operation of 2 Transmitters.

(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with

less power using the smallest footprint mmWave sensor portfolio for automotive

applications.

Automotive mmWave

Sensors

TI’s automotive mmWave sensor portfolio offers high-performance radar front end to

ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable

sensor portfolio enables design and development of ADAS system solution for every

performance, application and sensor configuration ranging from comfort functions to

safety functions in all vehicles.

Companion Products

for AWR1243

Review products that are frequently purchased or used in conjunction with this product.

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AWR1243

SWRS188D – MAY 2017 – REVISED DECEMBER 2021

I TEXAS INSTRUMENTS I X I X I X I X I X X X X / X ‘ \_ / _ ’ ’ mm mm’ ‘ w w ‘ H ‘ ‘ ‘ w ‘1 ‘ , , r ‘ ‘ H \ / / x / x / \ / \ / \ / w / /\ , y \r \r X X \ A /\ '\ /‘ A w / - ,\ / m to m

7 Terminal Configuration and Functions

7.1 Pin Diagram

Figure 7-1 shows the pin locations for the 161-pin FCBGA package. Figure 7-2, Figure 7-3, Figure 7-4, and

Figure 7-5 show the same pins, but split into four quadrants.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Not to scale

VSSA VOUT_PA VSSA VSSA VSSA VSSA VOUT

_14APLL

VOUT

_14SYNTH

OSC

_CLKOUT VSSA

FM_CW

_SYNCIN1 VOUT_PA VSSA TX1 VSSA TX2 VSSA TX3 VSSA VBGAP VIN

_18CLK

VIN

_18VCO VSSA VSSA FM_CW

_CLKOUT

VSSA VIN

_13RF2 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA

FM_CW

_SYNCOUT

VIN

_13RF2

VIOIN

_18DIFF

FM_CW

_SYNCIN2

VSSA VSSA VSSA VSS VSS VSS VSS VSS VSSA CLKP VSSA

RX4 VSSA VIN_18BB VSS VSS VDDIN CLKM

VSSA VSSA VSSA VIN

_13RF1 VSS VSS VSS VSS Reserved CSI2

_TXM[0]

CSI2

_TXP[0]

RX3 VSSA VIN

_13RF1 VSS VSS VSS TDI CSI2

_TXM[1]

CSI2

_TXP[1]

VSSA VSSA VSSA VIN

_13RF1 VSS VSS VSS VSS TDO CSI2_CLKM CSI2_CLKP

RX2 VSSA VIN_18BB VSS VSS VSS VSS VSS VIOIN_18 CSI2

_TXM[2]

CSI2

_TXP[2]

VSSA VSSA VSSA VSS VSS VSS VSS TMS CSI2

_TXM[3]

CSI2

_TXP[3]

RX1 TCK HS_M

_Debug1

HS_P

_Debug1

VSSA VSSA VSSA GPIO[0] RS232_RX RS232_TX GPIO[1] NERROR_OUTMCU_CLK_OUT Sync_in VDDIN WARM

_RESET GPIO[2] HS_M

_Debug2

HS_P

_Debug2

Reserved MISO_1 SPI_HOST_INTR_1NERROR_IN QSPI_CS QSPI[1] QSPI[3] Sync_out NRESET PMIC_CLK_OUT VNWA VDDIN

VSSA Reserved Reserved Reserved VDDIN SPI_CS_1 MOSI_1 SPI_CLK_1 QSPI_CLK QSPI[0] QSPI[2] VIOIN VIN_SRAM VSS

ANAMUX VSENSE

VSSA

Analog Test 1 Analog Test 2 Analog Test 3

Analog Test 4

Figure 7-1. Pin Diagram

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1 2 3 4 5 6 7 8

Not to scale

VSSA VOUT_PA VSSA VSSA VSSA

FM_CW

_SYNCIN1 VOUT_PA VSSA TX1 VSSA TX2 VSSA TX3

VSSA VIN

_13RF2 VSSA VSSA VSSA VSSA VSSA VSSA

FM_CW

_SYNCOUT

VIN

_13RF2

VSSA VSSA VSSA VSS VSS VSS

RX4 VSSA VIN_18BB

VSSA VSSA VSSA VIN

_13RF1 VSS VSS VSS

Figure 7-2. Top Left Quadrant

9 10 11 12 13 14 15

Not to scale

VSSA VOUT

_14APLL

VOUT

_14SYNTH

OSC

_CLKOUT VSSA

VSSA VBGAP VIN

_18CLK

VIN

_18VCO VSSA VSSA FM_CW

_CLKOUT

VSSA VSSA

VIOIN

_18DIFF

FM_CW

_SYNCIN2

VSS VSS VSSA CLKP VSSA

VSS VSS VDDIN CLKM

VSS Reserved CSI2

_TXM[0]

CSI2

_TXP[0]

ANAMUX VSENSE

Figure 7-3. Top Right Quadrant

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12345678

Not to scale

RX3 VSSA VIN

_13RF1 VSS

VSSA VSSA VSSA VIN

_13RF1 VSS VSS VSS

RX2 VSSA VIN_18BB VSS VSS

VSSA VSSA VSSA VSS VSS VSS

RX1

VSSA VSSA VSSA GPIO[0] RS232_RX RS232_TX GPIO[1] NERROR_OUT

Reserved MISO_1 SPI_HOST_INTR_1NERROR_IN QSPI_CS

VSSA Reserved Reserved Reserved VDDIN SPI_CS_1 MOSI_1

VSSA

Analog Test 1 Analog Test 2 Analog Test 3

Analog Test 4

Figure 7-4. Bottom Left Quadrant

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9 10 11 12 13 14 15

Not to scale

VSS VSS TDI CSI2

_TXM[1]

CSI2

_TXP[1]

VSS TDO CSI2_CLKM CSI2_CLKP

VSS VSS VSS VIOIN_18 CSI2

_TXM[2]

CSI2

_TXP[2]

VSS TMS CSI2

_TXM[3]

CSI2

_TXP[3]

TCK HS_M

_Debug1

HS_P

_Debug1

MCU_CLK_OUT Sync_in VDDIN WARM

_RESET GPIO[2] HS_M

_Debug2

HS_P

_Debug2

QSPI[1] QSPI[3] Sync_out NRESET PMIC_CLK_OUT VNWA VDDIN

SPI_CLK_1 QSPI_CLK QSPI[0] QSPI[2] VIOIN VIN_SRAM VSS

Figure 7-5. Bottom Right Quadrant

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TEXAS INSTRUMENTS

7.2 Signal Descriptions

Section 7.2.1 lists the pins by function and describes that function.

Note

All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;

hence, care needs to be taken that they are not driven externally without the VIO supply being present

to the device.

7.2.1 Signal Descriptions

FUNCTION SIGNAL NAME PIN

NUMBER

TYPE

DEFAULT PULL

STATUS(1) DESCRIPTION

Transmitters

TX1 B4 O — Single-ended transmitter1 o/p

TX2 B6 O — Single-ended transmitter2 o/p

TX3 B8 O — Single-ended transmitter3 o/p

Receivers

RX1 M2 I — Single-ended receiver1 i/p

RX2 K2 I — Single-ended receiver2 i/p

RX3 H2 I — Single-ended receiver3 i/p

RX4 F2 I — Single-ended receiver4 i/p

CSI2 TX

CSI2_TXP[0] G15 O — Differential data Out – Lane 0 (for CSI and LVDS

debug interface)

CSI2_TXM[0] G14 O —

CSI2_CLKP J15 O — Differential clock Out (for CSI and LVDS debug

interface)

CSI2_CLKM J14 O —

CSI2_TXP[1] H15 O — Differential data Out – Lane 1 (for CSI and LVDS

debug interface)

CSI2_TXM[1] H14 O —

CSI2_TXP[2] K15 O — Differential data Out – Lane 2 (for CSI and LVDS

debug interface)

CSI2_TXM[2] K14 O —

CSI2_TXP[3] L15 O — Differential data Out – Lane 3 (for CSI and LVDS

debug interface)

CSI2_TXM[3] L14 O —

HS_DEBUG1_P M15 O — Differential debug port 1 (for LVDS debug interface)

HS_DEBUG1_M M14 O —

HS_DEBUG2_P N15 O — Differential debug port 2 (for LVDS debug interface)

HS_DEBUG2_M N14 O —

Reserved

Space

FM_CW_CLKOUT B15 O — Reserved Signal. Not applicable in AWR1243.

FM_CW_SYNCOUT D1

FM_CW_SYNCIN1 B1 I — Reserved Signal. Not applicable in AWR1243.

FM_CW_SYNCIN2 D15

Reference clock OSC_CLKOUT A14 O —

Reference clock output from clocking subsystem

after cleanup PLL. Can be used by peripheral chip

in multichip cascading

System

synchronization

SYNC_OUT P11 O Pull Down

Low-frequency frame synchronization signal output.

Can be used by peripheral chip in multichip

cascading

SYNC_IN N10 I Pull Down

Low-frequency frame synchronization signal input.

This signal could also be used as a hardware trigger

for frame start

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FUNCTION SIGNAL NAME PIN

NUMBER

TYPE

DEFAULT PULL

STATUS(1) DESCRIPTION

SPI control

interface from

external MCU

(default

peripheral

mode)

SPI_CS_1 R7 I Pull Up SPI chip select

SPI_CLK_1 R9 I Pull Down SPI clock

MOSI_1 R8 I Pull Up SPI data input

MISO_1 P5 O Pull Up SPI data output

SPI_HOST_INTR_1 P6 O Pull Down SPI interrupt to host

RESERVED R3, R4, R5,

P4 —

Reset

NRESET P12 I — Power on reset for chip. Active low

WARM_RESET(2) N12 IO Open Drain

Open-drain fail-safe warm reset signal. Can be

driven from PMIC for diagnostic or can be used as

status signal that the device is going through reset.

SOP2 P13 I The SOP pins are driven externally (weak drive)

and the AWR device senses the state of these pins

during bootup to decide the bootup mode. After boot

the same pins have other functionality.

[SOP2 SOP1 SOP0] = [0 0 1] → Functional SPI

mode

[SOP2 SOP1 SOP0] = [1 0 1] → Flashing mode

[SOP2 SOP1 SOP0] = [0 1 1] → debug mode

Sense on Power SOP1 P11 I —

SOP0 J13 I

Safety

NERROR_OUT N8 O Open Drain

Open-drain fail-safe output signal. Connected to

PMIC/Processor/MCU to indicate that some severe

criticality fault has happened. Recovery would be

through reset.

NERROR_IN P7 I Open Drain

Fail-safe input to the device. Error output from

any other device can be concentrated in the error

signaling monitor module inside the device and

appropriate action can be taken by firmware

JTAG

TMS L13 I Pull Up

JTAG port for TI internal development

TCK M13 I Pull Down

TDI H13 I Pull Up

TDO J13 O —

Reference

oscillator

CLKP E14 I —

In XTAL mode: Input for the reference crystal

In External clock mode: Single ended input

reference clock port

CLKM F14 O —

In XTAL mode: Feedback drive for the reference

crystal

In External clock mode: Connect this port to ground

Band-gap

voltage VBGAP B10 O —

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FUNCTION SIGNAL NAME PIN

NUMBER

TYPE

DEFAULT PULL

STATUS(1) DESCRIPTION

Power supply

VDDIN F13,N11,P15

,R6 POW — 1.2-V digital power supply

VIN_SRAM R14 POW — 1.2-V power rail for internal SRAM

VNWA P14 POW — 1.2-V power rail for SRAM array back bias

VIOIN R13 POW — I/O supply (3.3-V or 1.8-V): All CMOS I/Os would

operate on this supply.

VIOIN_18 K13 POW — 1.8-V supply for CMOS IO

VIN_18CLK B11 POW — 1.8-V supply for clock module

VIOIN_18DIFF D13 POW — 1.8-V supply for CSI2 port

Reserved G13 POW — No connect

VIN_13RF1 G5,J5,H5 POW — 1.3-V Analog and RF supply,VIN_13RF1 and

VIN_13RF2 could be shorted on the board

VIN_13RF2 C2,D2 POW —

VIN_18BB K5,F5 POW — 1.8-V Analog baseband power supply

VIN_18VCO B12 POW — 1.8-V RF VCO supply

VSS

E5,E6,E8,E1

0,E11,F9,F1

1,G6,G7,G8,

G10,H7,H9,

H11,J6,J7,J8

,J10,K7,K8,K

9,K10,K11,L

5,L6,L8,L10,

R15

GND — Digital ground

VSSA

A1,A3,A5,A7

,A9,A15,B3,

B5,B7,B9,B1

3,B14,C1,C3

,C4,C5,C6,C

7,C8,C9,C15

,E1,E2,E3,E

13,E15,F3,G

1,G2,G3,H3,

J1,J2,J3,K3,

L1,L2,L3,

M3,N1,N2,N

3,R1

GND — Analog ground

Internal LDO

output/inputs

VOUT_14APLL A10 O —

VOUT_14SYNTH A13 O —

VOUT_PA A2,B2 IO —

When internal PA LDO is used this pin provides the

output voltage of the LDO. When the internal PA

LDO is bypassed and disabled 1V supply should

be fed on this pin. This is mandatory in 3TX

simultaneous use case.

External clock

out

PMIC_CLK_OUT P13 O — Dithered clock input to PMIC

MCU_CLK_OUT N9 O — Programmable clock given out to external MCU or

the processor

General-

purpose I/Os

GPIO[0] N4 IO Pull Down General-purpose IO

GPIO[1] N7 IO Pull Down General-purpose IO

GPIO[2] N13 IO Pull Down General-purpose IO

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FUNCTION SIGNAL NAME PIN

NUMBER

TYPE

DEFAULT PULL

STATUS(1) DESCRIPTION

QSPI for Serial

Flash

QSPI_CS P8 O Pull Up Chip-select output from the device. Device is a

controller connected to serial flash peripheral.

QSPI_CLK R10 O Pull Down Clock output from the device. Device is a controller

connected to serial flash peripheral.

QSPI[0] R11 IO Pull Down Data IN/OUT

QSPI[1] P9 IO Pull Down Data IN/OUT

QSPI[2] R12 IO Pull Up Data IN/OUT

QSPI[3] P10 IO Pull Up Data IN/OUT

Flash

programming

and RS232

UART

RS232_TX N6 O Pull Down

UART pins for programming external flash

RS232_RX N5 I Pull Up

Test and Debug

output for

preproduction

phase. Can be

pinned out on

production

hardware for

field debug

Analog Test1 P1 IO — Internal test signal

Analog Test2 P2 IO — Internal test signal

Analog Test3 P3 IO — Internal test signal

Analog Test4 R2 IO — Internal test signal

ANAMUX C13 IO — Internal test signal

VSENSE C14 IO — Internal test signal

(1) Status of PULL structures associated with the IO after device POWER UP.

(2) For the AWR1243 WARM_RESET can be used as an output only pin for status indication.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

PARAMETERS(1) (2) MIN MAX UNIT

VDDIN 1.2 V digital power supply –0.5 1.4 V

VIN_SRAM 1.2 V power rail for internal SRAM –0.5 1.4 V

VNWA 1.2 V power rail for SRAM array back bias –0.5 1.4 V

VIOIN I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply. –0.5 3.8 V

VIOIN_18 1.8 V supply for CMOS IO –0.5 2 V

VIN_18CLK 1.8 V supply for clock module –0.5 2 V

VIOIN_18DIFF 1.8 V supply for CSI2 port –0.5 2 V

VIN_13RF1 1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could

be shorted on the board. –0.5 1.45 V

VIN_13RF2

VIN_13RF1 1-V Internal LDO bypass mode. Device supports mode

where external Power Management block can supply 1 V on

VIN_13RF1 and VIN_13RF2 rails. In this configuration, the

internal LDO of the device would be kept bypassed.

–0.5 1.4 V

VIN_13RF2

VIN_18BB 1.8-V Analog baseband power supply –0.5 2 V

VIN_18VCO supply 1.8-V RF VCO supply –0.5 2 V

RX1-4 Externally applied power on RF inputs 10 dBm

TX1-3 Externally applied power on RF outputs(3) 10 dBm

Input and output

voltage range

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State) –0.3V VIOIN + 0.3

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

VIOIN + 20% up to

20% of signal period

CLKP, CLKM Input ports for reference crystal –0.5 2 V

Clamp current

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

–20 20 mA

TJOperating junction temperature range –40 125 °C

TSTG Storage temperature range after soldered onto PC board –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS, unless otherwise noted.

(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on

the TX output.

8.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1) ±2000

Charged-device model (CDM), per AEC

Q100-011

All other pins ±500

Corner pins ±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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8.3 Power-On Hours (POH)

JUNCTION

TEMPERATURE (Tj)

(1) (2)

OPERATING

CONDITION NOMINAL CVDD VOLTAGE (V) POWER-ON HOURS [POH] (HOURS)

–40°C

100% duty cycle 1.2

600 (6%)

75°C 2000 (20%)

95°C 6500 (65%)

125°C 900 (9%)

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would

not be applicable, if the Tx gain table is overwritten using an API.

8.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VDDIN 1.2 V digital power supply 1.14 1.2 1.32 V

VIN_SRAM 1.2 V power rail for internal SRAM 1.14 1.2 1.32 V

VNWA 1.2 V power rail for SRAM array back bias 1.14 1.2 1.32 V

VIOIN I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

3.135 3.3 3.465 V

1.71 1.8 1.89

VIOIN_18 1.8 V supply for CMOS IO 1.71 1.8 1.9 V

VIN_18CLK 1.8 V supply for clock module 1.71 1.8 1.9 V

VIOIN_18DIFF 1.8 V supply for CSI2 port 1.71 1.8 1.9 V

VIN_13RF1 1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2

could be shorted on the board 1.23 1.3 1.36 V

VIN_13RF2

VIN_13RF1

(1-V Internal LDO

bypass mode) 0.95 1 1.05 V

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN18BB 1.8-V Analog baseband power supply 1.71 1.8 1.9 V

VIN_18VCO 1.8V RF VCO supply 1.71 1.8 1.9 V

VIH

Voltage Input High (1.8 V mode) 1.17 V

Voltage Input High (3.3 V mode) 2.25

VIL

Voltage Input Low (1.8 V mode) 0.3*VIOIN V

Voltage Input Low (3.3 V mode) 0.62

VOH High-level output threshold (IOH = 6 mA) VIOIN – 450 mV

VOL Low-level output threshold (IOL = 6 mA) 450 mV

NRESET

SOP[2:0]

VIL (1.8V Mode) 0.2

VIH (1.8V Mode) 0.96

VIL (3.3V Mode) 0.3

VIH (3.3V Mode) 1.57

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8.5 Power Supply Specifications

Table 8-1 describes the four rails from an external power supply block of the AWR1243 device.

Table 8-1. Power Supply Rails Characteristics

SUPPLY DEVICE BLOCKS POWERED FROM THE SUPPLY RELEVANT IOS IN THE DEVICE

1.8 V Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, CSI2

Input: VIN_18VCO, VIN18CLK, VIN_18BB,

VIOIN_18DIFF, VIOIN_18IO

LDO Output: VOUT_14SYNTH, VOUT_14APLL

1.3 V (or 1 V in internal

LDO bypass mode)(1)

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

Input: VIN_13RF2, VIN_13RF1

LDO Output: VOUT_PA

3.3 V (or 1.8 V for 1.8 V

I/O mode) Digital I/Os Input VIOIN

1.2 V Core Digital and SRAMs Input: VDDIN, VIN_SRAM

(1) The device only supports simultanoeus operation of 2 transmitters. In the 1-V LDO bypass mode, 1V supply needs to be fed on the

VOUT PA pin.

The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 8-2 are defined to meet

a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB

relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted

are rms levels for a sinusoidal input applied at the specified frequency.

Table 8-2. Ripple Specifications

FREQUENCY (kHz)

RF RAIL VCO/IF RAIL

1.0 V (INTERNAL LDO BYPASS)

(µVRMS)1.3 V (µVRMS) 1.8 V (µVRMS)

137.5 7 648 83

275 5 76 21

550 3 22 11

1100 2 4 6

2200 11 82 13

4400 13 93 19

6600 22 117 29

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8.6 Power Consumption Summary

Table 8-3 and Table 8-4 summarize the power consumption at the power terminals.

Table 8-3. Maximum Current Ratings at Power Terminals

PARAMETER SUPPLY NAME DESCRIPTION MIN TYP MAX UNIT

Current consumption(1)

VDDIN, VIN_SRAM, VNWA Total current drawn by all

nodes driven by 1.2V rail 500

VIN_13RF1, VIN_13RF2

Total current drawn by all

nodes driven by 1.3V (or

1V in LDO Bypass mode)

rail

2000

VIOIN_18, VIN_18CLK,

VIOIN_18DIFF, VIN_18BB,

VIN_18VCO

Total current drawn by all

nodes driven by 1.8V rail 850

VIOIN

Total current drawn by

all nodes driven by 3.3V

rail(2)

(1) The specified current values are at typical supply voltage level.

(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.

Table 8-4. Average Power Consumption at Power Terminals

PARAMETER CONDITION DESCRIPTION MIN TYP MAX UNIT

Average power

consumption

1.0-V internal

LDO bypass

mode

1TX, 4RX Sampling: 16.66 MSps complex

Transceiver, 40-ms frame time, 512

chirps, 512 samples/chirp, 8.5-μs

interchirp time (50% duty cycle)

Data Port: MIPI-CSI-2

1.62

2TX, 4RX 1.79

1.3-V internal

LDO enabled

mode

1TX, 4RX 1.80

2TX, 4RX 2.01

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8.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

Receiver

Noise figure 76 to 77 GHz (VCO1) 14 dB

77 to 81 GHz (VCO2) 15

1-dB compression point (Out Of Band)(1) –8 dBm

Maximum gain 48 dB

Gain range 24 dB

Gain step size 2 dB

Image Rejection Ratio (IMRR) 30 dB

IF bandwidth(2) 15 MHz

ADC sampling rate (real/complex 2x) 37.5 Msps

ADC sampling rate (complex 1x) 18.75 Msps

ADC resolution 12 Bits

Return loss (S11) <–10 dB

Gain mismatch variation (over temperature) ±0.5 dB

Phase mismatch variation (over temperature) ±3 °

In-band IIP2

RX gain = 30dB

IF = 1.5, 2 MHz at

–12 dBFS

16 dBm

Out-of-band IIP2

RX gain = 24dB

IF = 10 kHz at -10dBm,

1.9 MHz at -30 dBm

24 dBm

Idle Channel Spurs –90 dBFS

Transmitter Output power 12 dBm

Amplitude noise –145 dBc/Hz

Clock

subsystem

Frequency range 76 81 GHz

Ramp rate 100 MHz/µs

Phase noise at 1-MHz offset 76 to 77 GHz (VCO1) –95 dBc/Hz

77 to 81 GHz (VCO2) –93

(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off

frequency.

(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set

of available HPF corners is summarized as follows:

Available HPF Corner Frequencies (kHz)

HPF1 HPF2

175, 235, 350, 700 350, 700, 1400, 2800

The filtering performed by the digital baseband chain is targeted to provide:

• Less than ±0.5 dB pass-band ripple/droop, and

• Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain

programmed.

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I TEXAS INSTRUMENTS 13 43 //

RX Gain (dB)

NF (dB)

In-band P1DB (dBm)

8 -48

10 -42

12 -36

14 -30

16 -24

18 -18

30 32 34 36 38 40 42 44 46 48

NF (dB)

In-band P1DB (dBm)

Figure 8-1. Noise Figure, In-band P1dB vs Receiver Gain

8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

THERMAL METRICS(1) °C/W(2) (3)

RΘJC Junction-to-case 5

RΘJB Junction-to-board 5.9

RΘJA Junction-to-free air 21.6

RΘJMA Junction-to-moving air 15.3 (4)

PsiJT Junction-to-package top 0.69

PsiJB Junction-to-board 5.8

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on

a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(4) Air flow = 1 m/s

8.9 Timing and Switching Characteristics

8.9.1 Power Supply Sequencing and Reset Timing

The AWR1243 device expects all external voltage rails and SOP lines to be stable before reset is deasserted.

Figure 8-2 describes the device wake-up sequence.

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VDDIN,

VIN_SRAM

VNWA

WARMRESET

OUTPUT

VIOIN_18

VIN18_CLK

VIOIN_18DIFF

VIN18_BB

VIN_13RF1

VIN_13RF2

VIOIN

nRESET

SOP[2.1.0]

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

MCUCLK

OUTPUT (1)

QSPI_CS

OUTPUT

DC power

Stable before

nRESET

release

SOP

Setup

Time

SOP

Hold time to

nRESET

Power

MSS

BOOT

START

QSPI

READ

nRESET

ASSERT

tPGDEL

Power

notOK

Warm reset

delay for crystal

or ext osc

7ms (XTAL Mode)

500 µs (REFCLK Mode)

Figure 8-2. Device Wake-up Sequence

8.9.2 Synchronized Frame Triggering

The AWR1243 device supports a hardware based mechanism to trigger radar frames. An external host can

pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of

the external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional

programmable delay that the user can set to control the frame start time.

The periodicity of the external SYNC_IN pulse should be always greater than the programmed frame periodic in

the frame configurations in all instances.

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MM M

SYNC_IN

(Hardware

Trigger)

Radar

Frames

Tlag

Frame-1 Frame-2

Tactive_frame

Tpulse

Figure 8-3. Sync In Hardware Trigger

Table 8-5. Frame Trigger Timing

PARAMETER DESCRIPTION MIN MAX UNIT

Tactive_frame Active frame duration User defined ns

Tpulse 25 4000

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8.9.3 Input Clocks and Oscillators

8.9.3.1 Clock Specifications

An external crystal is connected to the device pins. Figure 8-4 shows the crystal implementation.

40 MHz

CLKP

CLKM

Cf1

Cf2

Figure 8-4. Crystal Implementation

Note

The load capacitors, Cf1 and Cf2 in Figure 8-4, should be chosen such that Equation 1 is satisfied.

CL in the equation is the load specified by the crystal manufacturer. All discrete components used

to implement the oscillator circuit should be placed as close as possible to the associated oscillator

CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

f 2

L f1 P

f1 f 2

C C C

C C

= ´ +

(1)

Table 8-6 lists the electrical characteristics of the clock crystal.

Table 8-6. Crystal Electrical Characteristics (Oscillator Mode)

NAME DESCRIPTION MIN TYP MAX UNIT

fPParallel resonance crystal frequency 40 MHz

CLCrystal load capacitance 5 8 12 pF

ESR Crystal ESR 50 Ω

Temperature range Expected temperature range of operation –40 125 °C

Frequency

tolerance Crystal frequency tolerance(1) (2) –200 200 ppm

Drive level 50 200 µW

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-7

lists the electrical characteristics of the external clock signal.

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Table 8-7. External Clock Mode Specifications

PARAMETER SPECIFICATION UNIT

MIN TYP MAX

Input Clock:

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise referred to 40 MHz

Frequency 40 MHz

AC-Amplitude 700 1200 mV (pp)

DC-trise/fall 10 ns

Phase Noise at 1 kHz –132 dBc/Hz

Phase Noise at 10 kHz –143 dBc/Hz

Phase Noise at 100 kHz –152 dBc/Hz

Phase Noise at 1 MHz –153 dBc/Hz

Duty Cycle 35 65 %

Freq Tolerance –100 100 ppm

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8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

8.9.4.1 Peripheral Description

The SPI uses a MibSPI Protocol by TI.

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream to be shifted

into and out of the device at a programmed bit-transfer rate. The MibSPI/SPI is normally used for communication

between the microcontroller and external peripherals or another microcontroller.

Section 8.9.4.1.2 and Section 8.9.4.1.3 assume the operating conditions stated in Section 8.9.4.1.1. Section

8.9.4.1.2, Section 8.9.4.1.3, and Figure 8-5 describe the timing and switching characteristics of the MibSPI.

8.9.4.1.1 SPI Timing Conditions

MIN TYP MAX UNIT

Input Conditions

tRInput rise time 1 3 ns

tFInput fall time 1 3 ns

Output Conditions

CLOAD Output load capacitance 2 15 pF

8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output)

NO. PARAMETER MIN TYP MAX UNIT

1 tc(SPC)S Cycle time, SPICLK 25 ns

2 tw(SPCH)S Pulse duration, SPICLK high 10 ns

3 tw(SPCL)S Pulse duration, SPICLK low 10 ns

4 td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low 10 ns

5 th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low 2 ns

8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input,

and SPISOMI = output)

NO. MIN TYP MAX UNIT

6 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high 3 ns

7 th(SPCH-SIMO)S Hold time, SPISIMO data valid after SPICLK high 1 ns

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l TEXAS INSTRUMENTS 1 1 1 1 SPICLK 1 1 1 ‘ 1 ,K 1 1 S; ,4 1 1 1 1 1 1 1.724.: 1 1 1 1 ‘ 1473—u ‘ 1 1 ‘ 1 ‘ 1 ‘ 1 1 ‘ 1 1 }<—5—>1 1 1 “—‘—"1 4’1 smsom swsow Da(a1sVa11ﬂ 1 1 1 1 1 14—6—N‘ 1 1 1 1 1 14774» 1 1 1 1 smswo SF1SIMO Data Mus1 Be vane

Figure 8-5. SPI Peripheral Mode External Timing

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8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)

1. Host should ensure that there is a delay of at least two SPI clocks between CS going low and start of SPI

clock.

2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.

Figure 8-6 shows the SPI communication timing of the typical interface protocol.

Figure 8-6. SPI Communication

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I TEXAS INSTRUMENTS \ oommammc«anumunnumummmmom ‘ L i 1 1 \i— ‘ a ‘f JmNUUUWWlhmmmnnmnnnmummwm

8.9.5 LVDS Interface Configuration

The AWR1243 supports seven differential LVDS IOs/Lanes to support debug where raw ADC data could

be extracted. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane

(LVDS_CLKP/M) one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data

rates:

• 900 Mbps (450 MHz DDR Clock)

• 600 Mbps (300 MHz DDR Clock)

• 450 Mbps (225 MHz DDR Clock)

• 400 Mbps (200 MHz DDR Clock)

• 300 Mbps (150 MHz DDR Clock)

• 225 Mbps (112.5 MHz DDR Clock)

• 150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

LVDS_FRCLKP/M

LVDS_TXP/M

LVDS_CLKP/M

Data bitwidth

Figure 8-7. LVDS Interface Lane Configuration And Relative Timings

8.9.5.1 LVDS Interface Timings

Table 8-8. LVDS Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Duty Cycle Requirements max 1 pF lumped capacitive load on

LVDS lanes

48% 52%

Output Differential Voltage peak-to-peak single-ended with 100 Ω

resistive load between differential pairs 250 450 mV

Output Offset Voltage 1125 1275 mV

Trise and Tfall 20%-80%, 900 Mbps 330 ps

Jitter (pk-pk) 900 Mbps 80 ps

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Trise

LVDS_CLK

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

Clock Jitter = 6sigma

Figure 8-8. Timing Parameters

8.9.6 General-Purpose Input/Output

Section 8.9.6.1 lists the switching characteristics of output timing relative to load capacitance.

8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)

PARAMETER(1) TEST CONDITIONS VIOIN = 1.8V VIOIN = 3.3V UNIT

trMax rise time

CL = 20 pF 2.8 3.0

nsCL = 50 pF 6.4 6.9

CL = 75 pF 9.4 10.2

tfMax fall time

CL = 20 pF 2.8 2.8

nsCL = 50 pF 6.4 6.6

CL = 75 pF 9.4 9.8

(1) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

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8.9.7 Camera Serial Interface (CSI)

The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This

interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity of

each wire of a lane is also configurable. Section 8.9.7.1, Figure 8-9, Figure 8-10, and Figure 8-11 describe the

clock and data timing of the CSI.The clock is always ON once the CSI IP is enabled. Hence it remains in HS

mode.

8.9.7.1 CSI Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

HPTX

HSTXDBR Data bit rate (1/2/4 data lane PHY) 150 600 Mbps

fCLK DDR clock frequency (1/2/4 data lane PHY) 75 300 MHz

ΔVCMTX(LF) Common-level variation –50 50 mV

tR and tF20% to 80% rise time and fall time 0.3 UI

LPTX DRIVER

tEOT Time from start of THS-TRAIL period to start of LP-11 state 105 +

12*UI

DATA-CLOCK Timing Specification

UINOM Nominal Unit Interval 1.67 13.33 ns

UIINST,MIN Minimum instantaneous Unit Interval 1.131 ns

TSKEW[TX] Data to clock skew measured at transmitter –0.15 0.15 UIINST,

MIN

CSI2 TIMING SPECIFICATION

TCLK-PRE Time that the HS clock shall be driven by the transmitter before

any associated data lane beginning the transition from LP to HS

mode.

8 ns

TCLK-PREPARE Time that the transmitter drives the clock lane LP-00 line

state immediately before the HS-0 line state starting the HS

transmission.

38 95 ns

TCLK-PREPARE + TCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state

before starting the clock.

300 ns

TEOT Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL,

to the start of the LP-11 state following a HS burst.

105 ns

+ 12*UI

THS-PREPARE Time that the transmitter drives the data lane LP-00 line

state immediately before the HS-0 line state starting the HS

transmission

40 + 4*UI 85 +

6*UI

THS-PREPARE + THS-ZERO THS-PREPARE + time that the transmitter drives the HS-0 state prior

to transmitting the Sync sequence.

145 ns +

10*UI

THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns

THS-TRAIL Time that the transmitter drives the flipped differential state after

last payload data bit of a HS transmission burst

max(8*UI, 60

ns + 4*UI)

TLPX TXXXransmitted length of any low-power state period 50 ns

CSI2_CLK(P/M)

CSI2_TX(P/M)

1 UI

0.5UI + Tskew

Figure 8-9. Clock and Data Timing in HS Transmission

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I TEXAS INSTRUMENTS WWWWWWOWQW: /—V ' F” {23009 WiV k A? a TRANS‘TION SEQUENCE TRANSWON nnnnnnnnn // \ k a mpcmwdbd/IJD/ EJ/ﬁggbogOd/OOOCN I II I/ H I/ [I H I I II N H H /I H \ /

TLPX

THS-SETTLE THS-TRAIL THS-EXIT

TEOT

THS-SKIP

THS-ZERO THS-SYNC

VIH(min)

VIL(max)

Clock

Lane

Data Lane

Dp/Dn

Disconnect

Terminator

LP-11 LP-01 LP-00

LP-11

Capture

1st Data Bit

THS-PREPARE

TD-TERM-EN

TREOT

LOW-POWER TO

HIGH-SPEED

TRANSITION

HS-ZERO

START OF

TRANSMISSION

SEQUENCE

HIGH-SPEED DATA

TRANSMISSION HS-TRAIL

HIGH-SPEED TO

LOW-POWER

TRANSITION

VOH

VOL

Figure 8-10. High-Speed Data Transmission Burst

Clock Lane

Dp/Dn

VIH(min)

VIL(max)

THS-SKIP

Data Lane

Dp/Dn

TCLK-SETTLE

TLPX TCLK-ZERO TCLK-PRE

THS-SETTLE

TLPX

VIH(min)

VIL(max)

Disconnect

Terminator

Disconnect

Terminator

TCLK-PREPARE

THS-PREPARE

A. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.

Figure 8-11. Switching the Clock Lane Between Clock Transmission and Low-Power Mode

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*9 TEXAS INSTRUMENTS 2+

9 Detailed Description

9.1 Overview

The AWR1243 device is a single-chip highly integrated 77-GHz transceiver and front end that includes three

transmit and four receive chains. The device can be used in long-range automotive radar applications such

as automatic emergency braking and automatic adaptive cruise control. The AWR1243 has extremely small

form factor and provides ultra-high resolution with very low power consumption. This device, when used with

the TDA3X or TD2X, offers higher levels of performance and flexibility through a programmable digital signal

processor (DSP); thus addressing the standard short-, mid-, and long-range automotive radar applications.

9.2 Functional Block Diagram

ADC Buffer

16KB PING/PONG

IF ADC

Digital Front-end

(Decimation filter

chain)

LNA

IF ADC

LNA

IF ADC

LNA

IF ADC

LNA

PA û-

Synth

(20 GHz) Ramp Generator

Osc.

RF Control / BIST

GPADCVMON Temp(B)

SPI/I2C

CSI2

RF/Analog Subsystem

Host control

interface

ADC output

interface

Digital

Synth Cycle

Counter

Phase

Shifter

Control (A)

A. Phase Shift Control:

• 0° / 180° BPM for AWR1243

B. Internal temperature sensor accuracy is ± 7 °C.

Figure 9-1. Functional Block Diagram

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9.3 Subsystems

9.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit

channels can be operated simultaneously for transmit beamforming purpose as required; whereas the four

receive channels can all be operated simultaneously.

Please note that AWR1243 device supports simultaneous operation of 2 transmitters only.

AWR1243

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MENTS

9.3.1.1 Clock Subsystem

The AWR1243 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has

a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF

synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum.

The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective

sensor operation.

The output of the RF synthesizer is available at the device pin boundary for multichip cascaded configuration.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

Figure 9-2 describes the clock subsystem.

Clean-Up

PLL

MULT

RFSYNTH

Timing

Engine

RX LO

XO /

Slicer

SoC Clock

40 MHz

CLK Detect

Lock Detect

SYNC_IN

OSC_CLKOUT

Lock Detect

TX LO

FM_CW_SYNCIN2*

FM_CW_SYNCOUT

FM_CW_CLKOUT

FM_CW_SYNCIN1*

SYNC_OUT

* These pins are 20GHz LO input pins. Connect LO to one pin while grounding the

other pin.

Figure 9-2. Clock Subsystem

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9.3.1.2 Transmit Subsystem

The AWR1243 transmit subsystem consists of three parallel transmit chains, each with independent phase and

amplitude control. A maximum of two transmit chains can be operational at the same time, however all three

chains can be operated together in a time-multiplexed fashion. The device supports binary phase modulation for

MIMO radar and interference mitigation.

Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also

support programmable backoff for system optimization.

Figure 9-3 describes the transmit subsystem.

û-

0/180°

(from Timing Engine)

6 bits

Loopback Path Fine Phase Shifter Control

PCB

Package

Chip

12dBm

@ 50 Ÿ LO

Self Test

Figure 9-3. Transmit Subsystem (Per Channel)

9.3.1.3 Receive Subsystem

The AWR1243 receive subsystem consists of four parallel channels. A single receive channel consists of an

LNA, mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the

same time an individual power-down option is also available for system optimization.

Unlike conventional real-only receivers, the AWR1243 device supports a complex baseband architecture, which

uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver

channel. The AWR1243 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff

frequencies above 175 kHz and can support bandwidths up to 15 MHz.

Figure 9-4 describes the receive subsystem.

Self Test

Chip

Package

PCB

50 W

GSG

Loopback

Path

DAC

DSM

RSSI

Saturation

Detect

DAC

Decimation

Image Rejection

ADC Buffer

I/Q Correction

Figure 9-4. Receive Subsystem (Per Channel)

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9.3.2 Host Interface

The AWR1243 device communicates with the host radar processor over the following main interfaces:

• Reference Clock – Reference clock available for host processor after device wakeup

• Control – 4-port standard SPI (peripheral) for host control along with HOST INTR pin for async events.. All

radio control commands (and response) flow through this interface.

• Data – High-speed serial port following the MIPI CSI2 format. Four data and one clock lane (all differential).

Data from different receive channels can be multiplexed on a single data lane to optimize board routing. This

is a unidirectional interface used for data transfer only.

• Reset – Active-low reset for device wakeup from host

• Out-of-band interrupt

• Error – Used for notifying the host in case the radio controller detects a fault

9.4 Other Subsystems

9.4.1 ADC Data Format Over CSI2 Interface

The AWR1243 device uses MIPI D-PHY / CSI2-based format to transfer the raw ADC samples to the external

MCU. This is shown in Figure 9-5.

• Supports four data lanes

• CSI-2 data rate scalable from 150 Mbps to 600 Mbps per lane

• Virtual channel based

• CRC generation

1 2 3 N

Frame Period

Acquisition Period

Frame

Ramp/Chirp

Data Ready

ST SP ET

Short

Packet

LPS

ST SP ET

Short

Packet

LPS

Chirp 1 data

Data rate/Lane should be such that "Chirp + Interchirp" period

should be able to accommodate the data transfer

ST SP ET

Short

Packet

Normal Mode

ST PH DATA

Long

Packet

PF ET LPS LPS

.5 s-.8 sμ μ

Frame Start – CSi2 VSYNC Start Short PacketLine Start – CSI2 HSYNC Start Short PacketLine End – CSI2 HSYNC End Short

PacketFrame End – CSi2 VSYNC End Short Packet

Figure 9-5. CSI-2 Transmission Format

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The data payload is constructed with the following three types of information:

• Chirp profile information

• The actual chirp number

• ADC data corresponding to chirps of all four channels

– Interleaved fashion

• Chirp quality data (configurable)

The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The data

packet packing format is shown in Figure 9-6

First

11 51011 0

CH Chirp

Profile

Channel

Number Chirp Num

11 51011 0

CH Chirp

Profile

Channel

Number Chirp Num

11 51011 0

CH Chirp

Profile

Channel

Number Chirp Num

11 51011 0

CH Chirp

Profile

Channel

Number Chirp Num

11 011 0

Channel 0 Sample 0 i Channel 0 Sample 0 q

11 011 0

Channel 1 Sample 0 i Channel 1 Sample 0 q

11 011 0

Channel 2 Sample 0 i Channel 2 Sample 0 q

11 011 0

Channel 3 Sample 0 i Channel 3 Sample 0 q

11 011 0

Channel 0 Sample 1 i Channel 0 Sample 1 q

11 011 0

Channel 1 Sample 1 i Channel 1 Sample 1 q

11 011 0

Channel 2 Sample 1 i Channel 2 Sample 1 q

11 011 0

Channel 3 Sample 1 i Channel 3 Sample 1 q

11 011 0

CQ Data [11:0] CQ Data [23:12]

11 011 0

CQ Data [35:24] CQ Data [47:36]

11 011 0

CQ Data [59:48] NU CQ Data [63:60]

Last

Continues till the

last sample. Max 1023

Figure 9-6. Data Packet Packing Format for 12-Bit Complex Configuration

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10 Monitoring and Diagnostics

10.1 Monitoring and Diagnostic Mechanisms

Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR1243.

MSS R4F is the processor used for running TI's Functional Firmware stored in the ROM that helps in the

execution of the API calls issued by the host processor (It is not a customer programmable core).

Table 10-1. Monitoring and Diagnostic Mechanisms for AWR1243

S No Feature Description

Boot time LBIST For MSS

R4F Core and associated

VIM

AWR1243 architecture supports hardware logic BIST (LBIST) engine self-test Controller

(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the MSS

R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level.

LBIST for the CPU and VIM are triggered by the bootloader.

2Boot time PBIST for MSS

R4F TCM Memories

MSS R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and

TCMB1. AWR1243 architecture supports a hardware programmable memory BIST (PBIST)

engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the

implemented MSS R4F TCMs at a transistor level.

PBIST for TCM memories is triggered by Bootloader at the boot time . CPU stays there in

while loop and does not proceed further if a fault is identified.

3End to End ECC for MSS

R4F TCM Memories

TCMs diagnostic is supported by Single error correction double error detection (SECDED)

ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the

64-bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This

scheme provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU

is configured to have predetermined response (Ignore or Abort generation) to single and

double bit error conditions.

4MSS R4F TCM bit

multiplexing

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as

an ECC fault.Further, bit multiplexing scheme implemented such that the bits accessed to

generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the

probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest

as multiple single bit faults. As the SECDED TCM ECC can correct a single bit fault in a

logical word, this scheme improves the usefulness of the TCM ECC diagnostic.

5 Clock Monitor

AWR1243 architecture supports Three Digital Clock Comparators (DCCs) and an internal

RCOSC. Dual functionality is provided by these modules – Clock detection and Clock

Monitoring.

DCCint is used to check the availability/range of Reference clock at boot otherwise the

device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source.

This provides debug capability). DCCint is only used by boot loader during boot time. It is

disabled once the APLL is enabled and locked.

DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided

version with the Reference input clock of the device. Initially (before configuring APLL),

DCC1 is used by bootloader to identify the precise frequency of reference input clock

against the internal RCOSC clock source. Failure detection for DCC1 would cause the

device to go into limp mode.

Clock Compare module (CCC) module is used to compare the APLL divided down

frequency with reference clock (XTAL). Failure detection is indicated by the nERROR OUT

signal.

6 RTI/WD for MSS R4F Internal watchdog is enabled by the bootloader in a windowed watchdog (DWWD) mode..

Watchdog expiry issues an internal warm reset and nERROR OUT signal to the host.

7 MPU for MSS R4F

Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial

separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions.

It is expected that the operating system controls the MPU and changes the MPU settings

based on the needs of each task. A violation of a configured memory protection policy

results in a CPU abort.

8PBIST for Peripheral interface

SRAMs - SPI, I2C

AWR1243 architecture supports a hardware programmable memory BIST (PBIST) engine

for Peripheral SRAMs as well.

PBIST for peripheral SRAM memories is triggered by the bootloader. The PBIST tests are

destructive to memory contents, and as such are typically run only at boot time. .

Any fault detected by the PBIST results in an error indicated in PBIST and boot status

response message.

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Table 10-1. Monitoring and Diagnostic Mechanisms for AWR1243 (continued)

S No Feature Description

9ECC for Peripheral interface

SRAMs – SPI, I2C

Peripheral interface SRAMs diagnostic is supported by Single error correction double error

detection (SECDED) ECC diagnostic. When a single or double bit error is detected the error

is indicated by nERROR (double bit error) or via SPI message (single bit error).

10 Cyclic Redundancy Check –

Main SS

Cyclic Redundancy Check (CRC) module is available for the Main SS. The firmware uses

this feature for data transfer checks in mailbox and SPI communication.

11 MPU for DMAs AWR1243 architecture supports MPUs on Main SS DMAs. The firmware uses this for stack

protection.

Boot time LBIST For BIST

R4F Core and associated

VIM

AWR1243 architecture supports hardware logic BIST (LBIST) even for BIST R4F core and

associated VIM module. This logic provides very high diagnostic coverage (>90%) on the

BIST R4F CPU core and VIM.

This is triggered by MSS R4F boot loader at boot time and it does not proceed further if the

fault is detected.

13 Boot time PBIST for BIST

R4F TCM Memories

AWR1243 architecture supports a hardware programmable memory BIST (PBIST) engine

for BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST

R4F TCMs.

PBIST is triggered at the power up of the BIST R4F.

14 End to End ECC for BIST

R4F TCM Memories

BIST R4F TCMs diagnostic is supported by Single error correction double error detection

(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while

double bit error is communicated to MSS R4F as an interrupt which sends a async event to

the host.

15 BIST R4F TCM bit

multiplexing

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults

resulting in logical multi-bit faults.

16 Temperature Sensors

AWR1243 architecture supports various temperature sensors all across the device (next to

power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame

period.(1)

17 Tx Power Monitors AWR1243 architecture supports power detectors at the Tx output.(2)

18 Error Signaling

Error Output

When a diagnostic detects a fault, the error must be indicated. The AWR1243 architecture

provides aggregation of fault indication from internal monitoring/diagnostic mechanisms

using nERROR signaling or async event over SPI interface.

19 Synthesizer (Chirp) frequency

monitor

Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and

comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if

any, are detected and reported.

20 Ball break detection for TX

ports (TX Ball break monitor)

AWR1243 architecture supports a ball break detection mechanism based on Impedance

measurement at the TX output(s) to detect and report any large deviations that can indicate

a ball break.

Monitoring is done by TIs code running on BIST R4F and failure is reported to the host.

It is completely up to customer SW to decide on the appropriate action based on the

message from BIST R4F.

21 RX loopback test Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,

inter-RX balance, etc.

22 IF loopback test Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect

failure.

23 RX saturation detect Provision to detect ADC saturation due to excessive incoming signal level and/or

interference.

(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the

temperature sensed via API by customer application.

a. Report the temperature sensed after every N frames

b. Report the condition once the temperature crosses programmed threshold.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.

(2) Monitoring is done by the TI's code running on BIST R4F.

There are two modes in which it could be configured to report the detected output power via API by customer application.

a. Report the power detected after every N frames

b. Report the condition once the output power degrades by more than configured threshold from the configured.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.

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I TEXAS INSTRUMENTS

Note

Refer to the Device Safety Manual or other relevant collaterals for more details on applicability of all

diagnostics mechanisms. For certification details, refer to the device product folder.

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11 Applications, Implementation, and Layout

Note

Information in the following Applications section is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

11.1 Application Information

A typical application addresses the standard short-, mid-, long-range, and high-performance imaging radar

applications with this radar front end and external programmable MCU. Figure 11-1 shows a short-, medium-, or

long-range radar application.

11.2 Short-, Medium-, and Long-Range Radar

Antenna

Structure SPI

Power Management Crystal

Automotive

Interface PHY

CSI2 (4 Lane Data + 1 Clock lane)

Reset

Error

MCU Clock

AWR1243

RX1

RX2

RX3

RX4

TX1

TX2

TX3

External

MCU

(For Example

TDA3x)

Figure 11-1. Short-, Medium-, and Long-Range Radar

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11.3 Reference Schematic

The reference schematic and power supply information can be found in the AWR1243 EVM Documentation.

Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.

•Altium AWR1243 EVM Design Files

•AWR1243 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions follow.

12.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, AWR1243). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package

type (for example, ABL0161 ALB0161), the temperature range (for example, blank is the default commercial

temperature range). Figure 12-1 provides a legend for reading the complete device name for any AWR1243

device.

For orderable part numbers of AWR1243 devices in the ABL0161 package types, see the Package Option

Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the AWR1243 Device Errata .

AWR1243

SWRS188D – MAY 2017 – REVISED DECEMBER 2021 www.ti.com

AWR 1 2 43 B I GABL

Prefix XA = Pre-Production

AWR = Production

Generation

Variant

Num RX/TX Channels

Features

Silicon PG Revision

Safety

 ±GHz

2 = FE

4 = FE + FFT + MCU

6 = FE + MCU + DSP

8 = FE + FFT + MCU + DSP

RX = 1,2,3,4

TX = 1,2,3

Blank = Baseline

Blank = Rev 1.0

E = Rev 2.0

B = Functional Safety Complaint, ASIL-B

Tray or Tape & Reel

Package

Security

Temperature (Tj)

R = Big Reel

Blank = Tray

ABL = BGA

G = General

S = Secure

D = Development Secure

C = 0°C to 70°C

K = ±°C to 85°C

A = ±°C to 105°C

I = ±°C to 125°C

Qualification

Q1 = AEC-Q100

Blank = no special Qual

F = Rev 3.0

Figure 12-1. Device Nomenclature

12.2 Tools and Software

Development Tools

AWR1243 cascade application note Describes TI's cascaded mmWave radar system.

Models

AWR1243 BSDL model Boundary scan database of testable input and output pins for IEEE 1149.1 of the

specific device.

AWR1x43 IBIS model IO buffer information model for the IO buffers of the device. For simulation on a

circuit board, see IBIS Open Forum.

AWR1243 checklist for

schematic review, layout

review, bringup/wakeup

A set of steps in spreadsheet form to select system functions and pinmux options.

Specific EVM schematic and layout notes to apply to customer engineering. A

bringup checklist is suggested for customers.

12.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral follows.

Errata

AWR1243 device errata Describes known advisories, limitations, and cautions on silicon and provides

workarounds.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

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AWR1243

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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

AWR1243

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I TEXAS INSTRUMENTS K0 Lg+++++ ++++++ ++++++ +++++ +++++ K ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ am” my mm pm ‘ mm mm W 5

13 Mechanical, Packaging, and Orderable Information

13.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

13.2 Tray Information for

www.ti.com

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I TEXAS INSTRUMENTS Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

AWR1243FBIGABLQ1 ACTIVE FCCSP ABL 161 176 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 AWR1243

964FC

AWR1243FBIGABLRQ1 ACTIVE FCCSP ABL 161 1000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 AWR1243

ABL G1

964FC

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 11-Nov-2021

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS L - Outer tray length without tabs rt+++++ ++++++ ++++++ ++++++ ++++++ + + + +++++ +++++ +++++ +++++ ++++++ ++++++ +tTgr+ + + + ++++++ Outer tray width 1 P1 - Tray unit pocket pitch CW - Measurement tor tray edge (Y direction) to comer pocket center — CL - Measurement for tray edge (X direction) to corner pocket center {KU- Outer tray height

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package

Name Package

Type Pins SPQ Unit array

matrix Max

temperature

(°C)

L (mm) W

(mm) K0

(µm) P1

(mm) CL

(mm) CW

(mm)

AWR1243FBIGABLQ1 ABL FCCSP 161 176 8 x 22 150 315 135.9 7620 13.4 16.8 17.2

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

‘ 1 :4 -aoooooo$oooooo®7 0000000 0000000 0000000 0000000 00 000 000 00 o 000 00 o o o 000 000 000 o 000 K ifw7 e7 e7e77e7eee7im ooo 000$ o 000 00 o ‘0 o 00 000 00 oo oo 00 Q o %\, ¢ 0000000 o 000 i777aoooooo ooooooo $¢ @ “ 7Tp§o o 0‘00 000 $5@ C] “ ‘ a 4% 'nmm

www.ti.com

PACKAGE OUTLINE

1.17 MAX

TYP

0.37

0.27

9.1

TYP

9.1 TYP

0.65 TYP

161X 0.45

0.35

A10.5

10.3 B

10.5

10.3

(0.65) TYP

FCBGA - 1.17 mm max heightABL0161A

PLASTIC BALL GRID ARRAY

4222493/B 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

BALL A1 CORNER

SEATING PLANE

BALL TYP 0.1 C

0.15 C A B

0.08 C

PKG

BALL A1 CORNER

12345678910 11

12 13 14 15

SCALE 1.400

CO 000 00 OO 00 0 000 O CO 000 000 0 000g) 79%7677&+@779770—O%}7 Ki 0 GOO GOO GOO 000 0008; 000 003000 0 O OO 00 000 C? CO ‘ OOOOOOOEDOOOOOOO ooooooo®ooooooo ooooooocpooooooo é TEXAS (<3 1="">

www.ti.com

EXAMPLE BOARD LAYOUT

161X ( 0.32)

(0.65) TYP

( 0.32)

METAL

0.05 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( 0.32)

SOLDER MASK

OPENING

0.05 MIN

FCBGA - 1.17 mm max heightABL0161A

PLASTIC BALL GRID ARRAY

4222493/B 10/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

PKG

LAND PATTERN EXAMPLE

SCALE:10X

12 3 45678910 11

12 13 14 15

NON-SOLDER MASK

DEFINED

(PREFERRED) SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

DEFINED

§ PH \ 6/1 $0 0 0‘00 000 @ooooocmpooooooo ooooooogx; 000 00 ‘ o o 000 00 9b 00 000 00 o ‘0 o 00 000 000$ o 000 K ieﬁewevg+awevaeei¢ 000 Good) o 000 00 O O®ooo 000 000 00 q) o 000 00 ‘ ooo oooooooéooooooo ooooooodyooooooo oo oo oooooc‘Pooooo K c:

www.ti.com

EXAMPLE STENCIL DESIGN

(0.65) TYP

161X ( 0.32)

(0.65) TYP

FCBGA - 1.17 mm max heightABL0161A

PLASTIC BALL GRID ARRAY

4222493/B 10/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

PKG

12 3 45678910 11

12 13 14 15

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments 的 AWR1243 规格书

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