Texas Instruments 的 LM290(2,4)LV 规格书

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LM290xLV Industry Standard, Low Voltage Operational Amplifiers
1 Features
• Industry standard amplifier for cost-sensitive
systems
• Low input offset voltage: ±1 mV
• Common-mode voltage range includes ground
• Unity-gain bandwidth: 1 MHz
• Low broadband noise: 40 nV/√Hz
• Low quiescent current: 90 µA/Ch
• Unity-gain stable
• Operational at supply voltages from 2.7 V to 5.5 V
• Offered in dual- and quad-channel variants
• Robust ESD specification: 2-kV HBM
• Extended temperature range: –40°C to 125°C
2 Applications
• Cordless appliances
• Uninterruptible power supply
• Battery pack, charger, and test equipment
• Power supply modules
• Environmental sensors signal conditioning
• Field transmitter: temperature sensors
• Oscilloscopes, digital multimeters, and signal
analyzers
• Rack mount server
• HVAC: heating, ventilating, and air conditioning
• DC motor control
• Low-side current sensing
3 Description
The LM290xLV family includes the dual LM2904LV
and quad LM2902LV operational amplifiers, or op
amps. The devices operate from a low voltage of
2.7 V to 5.5 V.
These op amps supply an alternative to the
LM2904 and LM2902 in low-voltage applications
that are sensitive to cost. Some applications are
large appliances, smoke detectors, and personal
electronics. The LM290xLV devices supply better
performance than the LM290x devices at low voltage,
and have lower power consumption. The op amps are
stable at unity gain, and do not have reverse phase
in overdrive conditions. The design for ESD gives the
LM290xLV family an HBM specification for a minimum
of 2 kV.
The LM290xLV family is available in packages that
have industry standards. The packages include SOIC,
VSSOP, and TSSOP packages.
Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
LM2902LV
SOIC (14) 8.65 mm × 3.91 mm
TSSOP (14) 4.40 mm × 5.00 mm
SOT-23 (14) 4.20 mm × 2.00 mm
LM2904LV
SOIC (8) 3.91 mm × 4.90 mm
TSSOP (8) 3.00 mm × 4.40 mm
SOT-23 (8) 1.60 mm × 2.90 mm
VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
RGRF
R1
C1
VIN
VOUT
= 1 +
V
V
OUT
IN
R
R
F
G
1
1 + sR C
1 1
( (
((
1
2pR C
1 1
f =
-3 dB
Single-Pole, Low-Pass Filter
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: LM2904LV.................................5
6.5 Thermal Information: LM2902LV.................................6
6.6 Electrical Characteristics.............................................6
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................17
9.1 Input and ESD Protection......................................... 17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................19
11.1 Documentation Support.......................................... 19
11.2 Receiving Notification of Documentation Updates..19
11.3 Support Resources................................................. 19
11.4 Trademarks............................................................. 19
11.5 Electrostatic Discharge Caution..............................19
11.6 Glossary.................................................................. 19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2019) to Revision C (February 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added SOT-23 (DYY) package to Device Information table...............................................................................1
• Added DYY (SOT-23) package to Pin Configuration and Functions section......................................................3
• Added DYY (SOT-23) package to Thermal Information: LM2902LV section......................................................6
Changes from Revision A (May 2019) to Revision B (October 2019) Page
• Deleted all SOT-23 (DDF) preview notations......................................................................................................1
Changes from Revision * (September 2018) to Revision A (May 2019) Page
• Added SOT-23 (DDF) package to Device Information table...............................................................................1
• Added DDF (SOT-23) package to Pin Configuration and Functions section......................................................3
• Added DDF (SOT-23) Thermal Information: LM2904LV section........................................................................ 5
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5 Pin Configuration and Functions
1OUT1 8 V+
2IN1±7 OUT2
3IN1+ 6 IN2±
4V±5 IN2+
Not to scale
Figure 5-1. LM2904LV D, DGK, PW, and DDF Package
8-Pin SOIC, VSSOP, TSSOP, and SOT-23
(Top View)
Table 5-1. Pin Functions: LM2904LV
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V– 4 I or — Negative (low) supply or ground (for single-supply operation)
V+ 8 I Positive (high) supply
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1OUT1 14 OUT4
2IN1±13 IN4±
3IN1+ 12 IN4+
4V+ 11 V±
5IN2+ 10 IN3+
6IN2±9 IN3±
7OUT2 8 OUT3
Not to scale
Figure 5-2. LM2902LV D, PW, DYY and Package
14-Pin SOIC, TSSOP, and SOT-23
(Top View)
Table 5-2. Pin Functions: LM2902LV
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
IN3– 9 I Inverting input, channel 3
IN3+ 10 I Noninverting input, channel 3
IN4– 13 I Inverting input, channel 4
IN4+ 12 I Noninverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 I or — Negative (low) supply or ground (for single-supply operation)
V+ 4 I Positive (high) supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, ([V+] – [V–]) 0 6 V
Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V
Differential (V+) – (V–) + 0.2 V
Current(2) –10 10 mA
Output short-circuit(3) Continuous
Operating, TA–55 125 °C
Operating junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
VSSupply voltage [(V+) – (V–)] 2.7 5.5 V
VIN Input-pin voltage range (V–) – 0.1 (V+) – 1 V
TASpecified temperature –40 125 °C
6.4 Thermal Information: LM2904LV
THERMAL METRIC(1)
LM2904LV
UNITD (SOIC) DGK (VSSOP) PW (TSSOP) DDF (SOT-23)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 207.9 201.2 200.7 183.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 92.8 85.7 95.4 112.5 °C/W
RθJB Junction-to-board thermal resistance 129.7 122.9 128.6 98.2 °C/W
ψJT Junction-to-top characterization parameter 26 21.2 27.2 18.8 °C/W
ψJB Junction-to-board characterization parameter 127.9 121.4 127.2 97.6 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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6.5 Thermal Information: LM2902LV
THERMAL METRIC(1)
LM2902LV
UNITD (SOIC) PW (TSSOP) DYY (SOT-23)
14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 102.1 148.3 154.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.8 68.1 86.3 °C/W
RθJB Junction-to-board thermal resistance 58.5 92.7 67.3 °C/W
ψJT Junction-to-top characterization parameter 20.5 16.9 9.8 °C/W
ψJB Junction-to-board characterization parameter 58.1 91.8 67.1 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.6 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 5.5 V (±1.35 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =
VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V ±1 ±3 mV
VS = 5 V, TA = –40°C to 125°C ±5
dVOS/dT VOS vs temperature TA = –40°C to 125°C ±4 µV/°C
PSRR Power-supply rejection ratio VS = 2.7 V to 5.5 V, VCM = (V–) 80 100 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal (V–) – 0.1 (V+) – 1 V
CMRR Common-mode rejection ratio
VS = 2.7 V, (V–) – 0.1 V < VCM < (V+) – 1 V
TA = –40°C to 125°C 84
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1 V
TA = –40°C to 125°C 63 92
INPUT BIAS CURRENT
IBInput bias current VS = 5 V ±15 pA
IOS Input offset current ±5 pA
NOISE
EnInput voltage noise (peak-to-peak) ƒ = 0.1 Hz to 10 Hz, VS = 5 V 5.1 µVPP
enInput voltage noise density ƒ = 1 kHz, VS = 5 V 40 nV/√ Hz
INPUT CAPACITANCE
CID Differential 2 pF
CIC Common-mode 5.5 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 2.7 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ 110 dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ 125
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 5 V 1 MHz
φmPhase margin VS = 5.5 V, G = 1 75 °
SR Slew rate VS = 5 V 1.5 V/µs
tSSettling time To 0.1%, VS = 5 V, 2-V step, G = 1, CL = 100 pF 4 µs
To 0.01%, VS = 5 V, 2-V step, G = 1, CL = 100 pF 5
tOR Overload recovery time VS = 5 V, VIN × gain > VS1 µs
THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = 1, ƒ = 1 kHz,
80-kHz measurement BW 0.005%
OUTPUT
VOH Voltage output swing from positive supply RL ≥ 2 kΩ, TA = –40°C to 125°C 1 V
VOL Voltage output swing from negative supply RL ≤ 10 kΩ, TA = –40°C to 125°C 40 75 mV
ISC Short-circuit current VS = 5.5 V ±40 mA
ZOOpen-loop output impedance VS = 5 V, ƒ = 1 MHz 1200 Ω
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6.6 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 5.5 V (±1.35 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =
VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VSSpecified voltage range 2.7 (±1.35) 5.5 (±2.75) V
IQQuiescent current per amplifier IO = 0 mA, VS = 5.5 V 90 150 µA
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 160
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Common-Mode Voltage (V)
IB and IOS (pA)
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3
-10
-8
-6
-4
-2
0
2
4
6
8
10
D007
IB-
IB+
IOS
Figure 6-1. IB and IOS vs Common-Mode Voltage
Temperature (qC)
Gain (dB)
-40 -20 0 20 40 60 80 100 120 140
0
20
40
60
80
100
120
140
160
D008
VS = 5.5 V
VS = 2.5 V
Figure 6-2. Open-Loop Gain vs Temperature
Frequency (Hz)
Gain (dB)
Phase (q)
-20 0
0 20
20 40
40 60
60 80
80 100
100 120
1k 10k 100k 1M
D009
Gain
Phase
CL = 10 pF
Figure 6-3. Open-Loop Gain and Phase vs Frequency
Output Voltage (V)
Open-Loop Voltage Gain (dB)
-3 -2 -1 0 1 2 3
0
20
40
60
80
100
120
140
160
D010D010D010D010
Figure 6-4. Open-Loop Gain vs Output Voltage
CL = 10 pF
Figure 6-5. Closed-Loop Gain vs Frequency
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Output Current (mA)
Output Voltage (V)
0 5 10 15 20 25 30 35 40 45 50
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
D012D012
-40 qC
25 qC
85 qC
125 qC
Figure 6-6. Output Voltage vs Output Current (Claw)
Frequency (Hz)
Power Supply Rejection Ratio (dB)
0
20
40
60
80
100
120
100 1k 10k 100k 1M
D013
PSRR+
PSRR
Figure 6-7. PSRR vs Frequency
Temperature (qC)
Power Supply Rejection Ratio (dB)
-40 -20 0 20 40 60 80 100 120 140
0
20
40
60
80
100
120
D014
VS = 2.7 V to 5.5 V
Figure 6-8. DC PSRR vs Temperature
Frequency (Hz)
Common-Mode Rejection Ratio (dB)
0
20
40
60
80
100
120
100 1k 10k 100k 1M
D015
Figure 6-9. CMRR vs Frequency
Temperature (qC)
Common-Mode Rejection Ratio (dB)
-40 -20 0 20 40 60 80 100 120 140
0
20
40
60
80
100
120
D016
VS = 2.7 V
VS = 5.5 V
VCM = (V–) – 0.1 V to (V+) – 1.5 V
Figure 6-10. DC CMRR vs Temperature
Time (1 s/div)
Amplitude (1 PV/div)
D017
Figure 6-11. 0.1-Hz to 10-Hz Integrated Voltage Noise
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Frequency (Hz)
Input Voltage Noise Spectral Density (nV/—Hz)
0
20
40
60
80
100
120
140
10 100 1k 10k 100k
D018
Figure 6-12. Input Voltage Noise Spectral Density
Frequency (Hz)
THD + N (dB)
-100
-90
-80
-70
-60
-50
100 1k 10k
D019
RL = 2K
RL = 10K
VS = 5.5 V VCM = 2.5 V G = 1
BW = 80 kHz VOUT = 0.5 VRMS
Figure 6-13. THD + N vs Frequency
Amplitude (VRMS)
THD + N (dB)
0.001 0.01 0.1 1 2
-100
-80
-60
-40
-20
0
D020
G = +1, RL = 2 k:
G = +1, RL = 10 k:
G = 1, RL = 2 k:
G = 1, RL = 10 k:
VS = 5.5 V VCM = 2.5 V f = 1 kHz
G = 1 BW = 80 kHz
Figure 6-14. THD + N vs Amplitude
Voltage Supply (V)
Quiescent Current (PA)
2.5 3 3.5 4 4.5 5 5.5
60
70
80
90
100
D021
Figure 6-15. Quiescent Current vs Supply Voltage
Temperature (qC)
Quiescent Current (PA)
-40 -20 0 20 40 60 80 100 120 140
60
70
80
90
100
D022
Figure 6-16. Quiescent Current vs Temperature
Frequency (Hz)
Open-Loop Output Impedance (:)
0
200
400
600
800
1000
1200
1400
1600
1800
2000
1k 10k 100k 1M 10M
D023
Figure 6-17. Open-Loop Output Impedance vs Frequency
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6.7 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Capacitance Load (pF)
Overshoot (%)
0 200 400 600 800 1000
0
5
10
15
20
25
30
35
40
45
50
D024
Overshoot (+)
Overshoot (–)
G = 1 VIN = 100 mVpp
Figure 6-18. Small Signal Overshoot vs Capacitive Load
Capacitance Load (pF)
Overshoot (%)
0 200 400 600 800 1000
0
5
10
15
20
25
30
35
40
45
50
D025
Overshoot (+)
Overshoot (–)
G = –1 VIN = 100 mVpp
Figure 6-19. Small Signal Overshoot vs Capacitive Load
Capacitance Load (pF)
Phase Margin (q)
0 200 400 600 800 1000
0
10
20
30
40
50
60
70
80
90
D026
Figure 6-20. Phase Margin vs Capacitive Load
Time (100 Ps/div)
Amplitude (1 V/div)
D027D027
VOUT
VIN
G = 1 VIN = 6.5 VPP
Figure 6-21. No Phase Reversal
Time (20 Ps/div)
Amplitude (1 V/div)
D028
VOUT
VIN
G = –10 VIN = 600 mVPP
Figure 6-22. Overload Recovery
Time (10 Ps/div)
Voltage (20 mV/div)
D029
VOUT
VIN
G = 1 VIN = 100 mVPP CL = 10 pF
Figure 6-23. Small-Signal Step Response
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6.7 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Time (10 Ps/div)
Voltage (1 V/div)
D030
VOUT
VIN
G = 1 CL = 10 pF VIN = 4 VPP
Figure 6-24. Large-Signal Step Response
Time (1 s/div)μ
Output Voltage (1 mV/div)
D031
G = 1 CL = 100 pF 2-V step
Figure 6-25. Large-Signal Settling Time (Negative)
Time (1 Ps/div)
Output Voltage (1 mV/div)
D032
G = 1 CL = 100 pF 2-V step
Figure 6-26. Large-Signal Settling Time (Positive)
Temperature (qC)
Short Circuit Current (mA)
-40 -20 0 20 40 60 80 100 120
-80
-60
-40
-20
0
20
40
60
80
D033
Sinking
Sourcing
Figure 6-27. Short-Circuit Current vs Temperature
Frequency (Hz)
EMIRR (dB)
0
20
40
60
80
100
120
140
10M 100M 1G 10G
D035
Figure 6-28. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
Frequency (Hz)
Channel Separation (dB)
-140
-120
-100
-80
-60
-40
-20
0
1k 10k 100k 1M 10M
D036
Figure 6-29. Channel Separation
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7 Detailed Description
7.1 Overview
The LM290xLV family of low-power op amps is intended for cost-optimized systems. These devices operate
from 2.7 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications.
The input common-mode voltage range includes the negative rail and allows the LM290xLV family to be used in
many single-supply applications.
7.2 Functional Block Diagram
Reference
Current
V+
VIN-
VIN+
V
(Ground)
-
VBIAS2
VBIAS1 Class AB
Control
Circuitry
VO
7.3 Feature Description
7.3.1 Operating Voltage
The LM290xLV family of op amps is specified for operation from 2.7 V to 5.5 V. In addition, many specifications
apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown
in the section.
7.3.2 Common-Mode Input Range Includes Ground
The input common-mode voltage range of the LM290xLV family extends to the negative supply rail and within
1 V below the positive rail for the full supply voltage range of 2.7 V to 5.5 V. This performance is achieved with a
P‑channel differential pair, as shown in the Functional Block Diagram. Additionally, a complementary N‑channel
differential pair has been included in parallel to eliminate issues with phase reversal that are common with
previous generations of op amps. However, the N-channel pair is not optimized for operation, and significant
performance degradation occurs while this pair is operational. TI recommends limiting any voltage applied at the
inputs to at least 1 V below the positive supply rail (V+) to ensure that the op amp conforms to the specifications
detailed in the section.
7.3.3 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the specified output voltage swing, because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return to the linear
state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate.
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Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the LM290xLV family is typically 1 µs.
7.3.4 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can also involve the supply voltage pins. Each of
these different pin functions has electrical stress limits determined by the voltage breakdown characteristics of
the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal
electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events
both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-1 shows the ESD circuits contained in the LM290xLV. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal power
supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
+
±
V+
V±
+IN
±IN OUT
Power Supply
ESD Cell
Figure 7-1. Equivalent Internal ESD Circuitry
7.3.5 EMI Susceptibility and Input Filtering
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The Figure 6-28 plot illustrates
the performance of the LM290xLV family's EMI filters across a wide range of frequencies. For more detailed
information, see EMI Rejection Ratio of Operational Amplifiers available for download from www.ti.com.
7.4 Device Functional Modes
The LM290xLV family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 2.7 V (±1.35 V) and 5.5 V (±2.75 V).
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I TEXAS INSTRUMENTS V0 : IL >
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM290xLV devices are a family of low-power, cost-optimized operational amplifiers. The devices operate
from 2.7 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications.
The input common-mode voltage range includes the negative rail, and allows the LM290xLV to be used in any
single-supply applications.
8.2 Typical Application
Figure 8-1 shows the LM290xLV device configured in a low-side current sensing application.
ILOAD ZLOAD
VBUS
VSHUNT RSHUNT
0.1 Ÿ RF
255 NŸ
RG
7.5 NŸ
VOUT
5 V
+
í
+
í
Figure 8-1. LM290xLV Device in a Low-Side, Current-Sensing Application
8.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 3.5 V
• Maximum shunt voltage: 100 mV
8.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1:
OUT LOAD SHUNT
V I R Gain u u
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest allowable shunt
resistor is shown using Equation 2:
_
_
SHUNT MAX
SHUNT
LOAD MAX
V100mV
R 100m
I 1A
:
(2)
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Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the LM290xLV device to produce an output voltage of approximately 0 V to 3.5 V. The gain needed
by the LM290xLV to produce the necessary output voltage is calculated using Equation 3:
 
 
_ _
_ _
OUT MAX OUT MIN
IN MAX IN MIN
V V
Gain
V V
(3)
Using Equation 3, the required gain is calculated to be 35 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the LM290xLV device to 35 V/V.
 
 
F
G
R
Gain 1
R
(4)
8.2.3 Application Curve
Selecting RF as 255 kΩ and RG as 7.5 kΩ provides a combination that equals 35 V/V. Figure 8-2 shows the
measured transfer function of the circuit shown in Figure 8-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
ILOAD (A)
Output (V)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.5
1
1.5
2
2.5
3
3.5
Outp
Figure 8-2. Low-Side, Current-Sense Transfer Function
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9 Power Supply Recommendations
The LM290xLV family is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Section 6.6 presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 10.1.
9.1 Input and ESD Protection
The LM290xLV family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA, as stated in the section. Figure 9-1 shows how a series input resistor can be added to the driven input to
limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be
kept to a minimum in noise-sensitive applications.
5 kW
10-mA maximum
V+
VIN
VOUT
IOVERLOAD
Device
Figure 9-1. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds. Use thermal signatures or EMI measurement techniques
to determine where the majority of the ground current is flowing and be sure to route this path away from
sensitive analog circuitry. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace at a 90° angle is much better as opposed
to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Figure 10-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN 2
VOUT 2
RG
RF
+
VIN 1
VOUT 1
RG
RF
Figure 10-1. Schematic Representation for
OUT1
IN1±
IN1+
V±
OUT2
IN2±
IN2+
V+
VS±
GND
Ground (GND) plane on another layer
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Place components
close to device and to
each other to reduce
parasitic errors.
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VIN 1
GND
RF
RG
VIN 2
GND
RF
RG
VS+
GND
OUT 1
OUT 2
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
Figure 10-2. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Jun-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2902LVIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM2902LV Samples
LM2902LVIDYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902I Samples
LM2902LVIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM2902LV Samples
LM2904LVIDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L904 Samples
LM2904LVIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG | SN Level-2-260C-1 YEAR -40 to 125 1SQX Samples
LM2904LVIDR ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 2904LV Samples
LM2904LVIPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 2904 Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jun-2022
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM2902LV, LM2904LV :
•Automotive : LM2902LV-Q1, LM2904LV-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM2902LVIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LM2902LVIDYYR SOT-23-
THIN DYY 14 3000 330.0 12.4 4.8 3.6 1.6 8.0 12.0 Q3
LM2902LVIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2904LVIDDFR SOT-23-
THIN DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM2904LVIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM2904LVIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM2904LVIDR SOIC D 8 2500 330.0 15.4 6.4 5.2 2.1 8.0 12.0 Q1
LM2904LVIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
LM2904LVIPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM2902LVIDR SOIC D 14 2500 356.0 356.0 35.0
LM2902LVIDYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8
LM2902LVIPWR TSSOP PW 14 2000 366.0 364.0 50.0
LM2904LVIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
LM2904LVIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
LM2904LVIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
LM2904LVIDR SOIC D 8 2500 336.6 336.6 41.3
LM2904LVIPWR TSSOP PW 8 2000 366.0 364.0 50.0
LM2904LVIPWR TSSOP PW 8 2000 356.0 356.0 35.0
Pack Materials-Page 2
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddifi§n%="" 5.40="" 5,40="" @eeeeeej="" rfihfl§eflhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
PW0008A '
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
PW0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
PW0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
DDF0008A / —— \ JI- \ /~x
www.ti.com
PACKAGE OUTLINE
C
TYP
2.95
2.65
1.1 MAX
6X 0.65
8X 0.4
0.2
2X
1.95
TYP
0.20
0.08
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.3
A
NOTE 3
2.95
2.85
B1.65
1.55
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 4.000
DDF0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(2.6)
8X (1.05)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
1
45
8
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DDF0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
6X (0.65)
8X (0.45)
8X (1.05)
(R ) TYP0.05
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
PACKAGE OUTLINE
4224643/B 07/2021
www.ti.com
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
A
0.1 C
B
PIN 1 INDEX
AREA
4.3
4.1
NOTE 3
2.1
1.9
3.36
3.16
2X
3
14X 0.31
0.11
0.1 C A B 1.1 MAX
C
SEATING PLANE
0.2
0.08 TYP
SEE DETAIL A
0.1
0.0
0.25
GAUGE PLANE
0°- 8°
0.63
0.33
DETAIL A
TYP
1
7
8
14
12X 0.5
mEiEE Q ‘“““““J\““““““ flm@g_@_—J % 1 MS @
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE BOARD LAYOUT
4224643/B 07/2021
www.ti.com
SOT-23-THIN - 1.1 mm max height
DYY0014A
PLASTIC SMALL OUTLINE
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
14X (0.3)
14X (1.05)
(3)
12X (0.5)
(R0.05) TYP
1
78
14
METAL
SOLDER MASK
OPENING SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EEiEEE FL “‘ EEES—E_—L
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
EXAMPLE STENCIL DESIGN
4224643/B 07/2021
www.ti.com
SOT-23-THIN - 1.1 mm max height
DYY0014A
PLASTIC SMALL OUTLINE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
SYMM
SYMM
14X (0.3)
14X (1.05)
(3)
12X (0.5)
(R0.05) TYP
1
78
14
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