Texas Instruments 的 PCA9548A 规格书

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PCA9548A Low Voltage 8-Channel I2C Switch with Reset

1 Features

• 1-of-8 Bidirectional Translating Switches

• I2C Bus and SMBus Compatible

• Active-Low Reset Input

• Three Hardware Address Pins for Use of up to

Eight PCA9548A Devices on the I2C Bus

• Channel Selection Via I2C Bus

• Power-Up with All Switch Channels Deselected

• Low RON Switches

• Allows Voltage-Level Translation Between

1.8-V, 2.5-V, 3.3-V, and 5-V Buses

• No Glitch on Power Up

• Supports Hot Insertion

• Low Standby Current

• Operating Power-Supply Voltage Range of

2.3 V to 5.5 V

• 5-V Tolerant Inputs

• 0-kHz to 400-kHz Clock Frequency

• Latch-Up Performance Exceeds 100 mA Per JESD

78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

2 Applications

•Servers

•Routers (Telecom Switching Equipment)

•Factory Automation

•Products With I2C Slave Address Conflicts (For

Example, Multiple, Identical Temp Sensors)

3 Description

The PCA9548A device has eight bidirectional

translating switches that can be controlled through

the I2C bus. The SCL/SDA upstream pair fans out to

eight downstream pairs, or channels. Any individual

SCx/SDx channel or combination of channels can

be selected, determined by the contents of the

programmable control register. These downstream

channels can be used to resolve I2C slave address

conflicts. For example, if eight identical digital

temperature sensors are needed in the application,

one sensor can be connected at each channel: 0-7.

The system master can reset the PCA9548A in the

event of a time-out or other improper operation by

asserting a low in the RESET input. Similarly, the

power-on reset deselects all channels and initializes

the I2C/SMBus state machine. Asserting RESET

causes the same reset and initialization to occur

without powering down the part. This allows recovery

should once of the downstream I2C buses get stuck in

a low state.

The pass gates of the switches are constructed so

that the VCC pin can be used to limit the maximum

high voltage, which is passed by the PCA9548A.

This allows the use of different bus voltages on

each pair, so that 1.8-V, 2.5-V or 3.3-V parts can

communicate with 5-V parts, without any additional

protection. External pull-up resistors pull the bus up to

the desired voltage level for each channel. All I/O pins

are 5-V tolerant.

Device Information

DEVICE NAME PACKAGE(1) BODY SIZE (NOM)

PCA9548A

SSOP (24) 8.20 mm × 5.30 mm

TVSOP (24) 5.00 mm × 4.40 mm

SOIC (24) 15.40 mm × 7.50 mm

TSSOP (24) 7.80 mm × 4.40 mm

VQFN (24) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

PCA9548A

Slaves A0, A1...AN

Slaves B0, B1...BN

Slaves H0, H1...HN

I2C or SMBus

Master

(processor)

SDA

SCL

SD0

SC0

Channel 0

Channel 1

Channel 7

RESET SD1

SC1

SD7

SC7

VCC

GND

Slaves C0, C1...CN

Channel 2

SD2

SC2

Simplified Schematic

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

I TEXAS INSTRUMENTS

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 I2C Interface Timing Requirements.............................7

6.7 Reset Timing Requirements........................................8

6.8 Switching Characteristics............................................8

6.9 Typical Characteristics................................................9

7 Parameter Measurement Information.......................... 10

8 Detailed Description......................................................12

8.1 Overview................................................................... 12

8.2 Functional Block Diagram......................................... 13

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................14

8.5 Programming............................................................ 14

8.6 Register Maps...........................................................15

9 Application Information Disclaimer............................. 19

9.1 Application Information............................................. 19

9.2 Typical Application.................................................... 19

10 Power Supply Recommendations..............................23

10.1 Power-On Reset Requirements.............................. 23

11 Layout........................................................................... 25

11.1 Layout Guidelines................................................... 25

11.2 Layout Example...................................................... 26

12 Device and Documentation Support..........................27

12.1 Related Documentation.......................................... 27

12.2 Receiving Notification of Documentation Updates..27

12.3 Support Resources................................................. 27

12.4 Trademarks.............................................................27

12.5 Electrostatic Discharge Caution..............................27

12.6 Glossary..................................................................27

13 Mechanical, Packaging, and Orderable

Information.................................................................... 27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (April 2019) to Revision G (March 2021) Page

• Changed the PW and RGE package values in the Thermal Information. ..........................................................5

• Changed the VPORR row in the Electrical Characteristics .................................................................................. 6

• Added VPORF row to the Electrical Characteristics ............................................................................................ 6

• Changed the ICC Low inputs and High inputs values in the Electrical Characteristics .......................................6

• Changed the Power Supply Recommendations .............................................................................................. 23

Changes from Revision E (February 2015) to Revision F (April 2019) Page

• Updated the Section 3 section ...........................................................................................................................1

• Changed the Pin Configuration images.............................................................................................................. 3

• Updated Pin Name for Pin 8 From: SC2 To: SD2 in the Pin Functions table..................................................... 3

• Added the Typical Characteristics section.......................................................................................................... 9

Changes from Revision D (June 2014) to Revision E (February 2015) Page

• Changed front page image................................................................................................................................. 1

• Added Thermal Information. .............................................................................................................................. 5

• Changed Note (2) in the Electrical Characteristics ............................................................................................. 6

• Added Layout Example.....................................................................................................................................26

Changes from Revision C (June 2007) to Revision D (June 2014) Page

• Added RESET Errata section........................................................................................................................... 14

• Updated Typical Application schematic. .......................................................................................................... 19

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5 Pin Configuration and Functions

1A0 24 VCC

2A1 23 SDA

3RE SET 22 SCL

4SD0 21 A2

5SC0 20 SC7

6SD1 19 SD7

7SC1 18 SC6

8SD2 17 SD6

9SC2 16 SC5

10SD3 15 SD5

11SC3 14 SC4

12GND 13 SD4

No t to scale

Figure 5-1. DB, DGV, DW or PW Package, 24-Pin SSOP, TVSOP, SOIC or TSSOP , Top View

Table 5-1. Pin Functions

I/O DESCRIPTION

NAME

NO.

DB, DW, DGV ,

A0 1 I Address input 0. Connect directly to VCC or ground

A1 2 I Address input 1. Connect directly to VCC or ground

RESET 3 I Active-low reset input. Connect to VCC through a pull-up resistor, if not used

SD0 4 I/O Serial data 0. Connect to VCC through a pull-up resistor

SC0 5 I/O Serial clock 0. Connect to VCC through a pull-up resistor

SD1 6 I/O Serial data 1. Connect to VCC through a pull-up resistor

SC1 7 I/O Serial clock 1. Connect to VCC through a pull-up resistor

SD2 8 I/O Serial data 2. Connect to VCC through a pull-up resistor

SC2 9 I/O Serial clock 2. Connect to VCC through a pull-up resistor

SD3 10 I/O Serial data 3. Connect to VCC through a pull-up resistor

SC3 11 I/O Serial clock 3. Connect to VCC through a pull-up resistor

GND 12 — Ground

SD4 13 I/O Serial data 4. Connect to VCC through a pull-up resistor

SC4 14 I/O Serial clock 4. Connect to VCC through a pull-up resistor

SD5 15 I/O Serial data 5. Connect to VCC through a pull-up resistor

SC5 16 I/O Serial clock 5. Connect to VCC through a pull-up resistor

SD6 17 I/O Serial data 6. Connect to VCC through a pull-up resistor

SC6 18 I/O Serial clock 6. Connect to VCC through a pull-up resistor

SD7 19 I/O Serial data 7. Connect to VCC through a pull-up resistor

SC7 20 I/O Serial clock 7. Connect to VCC through a pull-up resistor

A2 21 I Address input 2. Connect directly to VCC or ground

SCL 22 I/O Serial clock bus. Connect to VCC through a pull-up resistor

SDA 23 I/O Serial data bus. Connect to VCC through a pull-up resistor

VCC 24 — Supply voltage

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24 RE SET7SD3

1SD0 18 A2

23 A18SC3

2SC0 17 SC7

22 A09GND

3SD1 16 SD7

21 VCC

10SD4

4SC1 15 SC6

20 SDA11SC4

5SD2 14 SD6

19 SCL12SD5

6SC2 13 SC5

No t to scale

Th ermal

Pad

Figure 5-2. RGE Package, 24-Pin VQFN , Top View

Table 5-2. Pin Functions, RGE

PIN I/O DESCRIPTION

NAME NO.

SD0 1 I/O Serial data 0. Connect to VCC through a pull-up resistor

SC0 2 I/O Serial clock 0. Connect to VCC through a pull-up resistor

SD1 3 I/O Serial data 1. Connect to VCC through a pull-up resistor

SC1 4 I/O Serial clock 1. Connect to VCC through a pull-up resistor

SD2 5 I/O Serial data 2. Connect to VCC through a pull-up resistor

SC2 6 I/O Serial clock 2. Connect to VCC through a pull-up resistor

SD3 7 I/O Serial data 3. Connect to VCC through a pull-up resistor

SC3 8 I/O Serial clock 3. Connect to VCC through a pull-up resistor

GND 9 — Ground

SD4 10 I/O Serial data 4. Connect to VCC through a pull-up resistor

SC4 11 I/O Serial clock 4. Connect to VCC through a pull-up resistor

SD5 12 I/O Serial data 5. Connect to VCC through a pull-up resistor

SC5 13 I/O Serial clock 5. Connect to VCC through a pull-up resistor

SD6 14 I/O Serial data 6. Connect to VCC through a pull-up resistor

SC6 15 I/O Serial clock 6. Connect to VCC through a pull-up resistor

SD7 16 I/O Serial data 7. Connect to VCC through a pull-up resistor

SC7 17 I/O Serial clock 7. Connect to VCC through a pull-up resistor

A2 18 I Address input 2. Connect directly to VCC or ground

SCL 19 I/O Serial clock bus. Connect to VCC through a pull-up resistor

SDA 20 I/O Serial data bus. Connect to VCC through a pull-up resistor

VCC 21 — Supply voltage

A0 22 I Address input 0. Connect directly to VCC or ground

A1 23 I Address input 1. Connect directly to VCC or ground

RESET 24 I Active-low reset input. Connect to VCC through a pull-up resistor, if not used

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TEXAS INSTRUMENTS

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

VCC Supply voltage –0.5 7 V

VIInput voltage(2) –0.5 7 V

IIInput current –20 20 mA

IOOutput current –25 25 mA

ICC Supply current –100 100 mA

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT

V(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101 or

ANSI/ESDA/JEDEC JS-002(2)

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

See (1)

MIN MAX UNIT

VCC Supply voltage 2.3 5.5 V

VIH High-level input voltage SCL, SDA 0.7 × VCC 6V

A2–A0, RESET 0.7 × VCC VCC + 0.5

VIL Low-level input voltage SCL, SDA –0.5 0.3 × VCC V

A2–A0, RESET –0.5 0.3 × VCC

TAOperating free-air temperature –40 85 °C

(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or

Floating CMOS Inputs application report.

6.4 Thermal Information

THERMAL METRIC(1)

PCA9548A

UNIT

DB (SSOP) DGV (TVSOP) DW (SOIC) PW (TSSOP) RGE (VQFN)

24 PINS

RθJA Junction-to-ambient thermal resistance 89.1 99.6 73.2 108.8 57.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 51.1 31.1 41.3 54.1 62.5 °C/W

RθJB Junction-to-board thermal resistance 46.6 53.1 42.9 62.7 34.4 °C/W

ψJT Junction-to-top characterization parameter 18.5 0.9 15.3 10.9 3.8 °C/W

ψJB Junction-to-board characterization parameter 46.3 52.6 42.6 62.3 34.4 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 15.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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TEXAS INSTRUMENTS

6.5 Electrical Characteristics

VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT

VPORR Power-on reset voltage, VCC rising No load, VI = VCC or GND 1.2 1.5 V

VPORF Power-on reset voltage, VCC falling(2) No load, VI = VCC or GND 0.8 1 V

Vo(sw) Switch output voltage Vi(sw) = VCC, ISWout = –100 μA

5 V 3.6

4.5 V to 5.5 V 2.6 4.5

3.3 V 1.9

3 V to 3.6 V 1.6 2.8

2.5 V 1.5

2.3 V to 2.7 V 1.1 2

IOL SDA VOL = 0.4 V 2.3 V to 5.5 V 3 6 mA

VOL = 0.6 V 6 9

SCL, SDA

VI = VCC or GND 2.3 V to 5.5 V

–1 1

μA

SC7–SC0, SD7–SD0 –1 1

A2–A0 –1 1

RESET –1 1

ICC

Operating mode

fSCL = 400 kHz VI = VCC or GND, IO = 0

5.5 V 50 80

μA

3.6 V 20 35

2.7 V 11 20

fSCL = 100 kHz VI = VCC or GND, IO = 0

5.5 V 9 30

3.6 V 6 15

2.7 V 4 8

Standby mode

Low inputs VI = GND, IO = 0

5.5 V 0.2 2

3.6 V 0.1 2

2.7 V 0.1 1

High inputs VI = VCC, IO = 0

5.5 V 0.2 2

3.6 V 0.1 2

2.7 V 0.1 1

ΔICC

Supply-current

change SCL, SDA

SCL or SDA input at 0.6 V,

Other inputs at VCC or GND 2.3 V to 5.5 V

3 20

μA

SCL or SDA input at VCC – 0.6 V,

Other inputs at VCC or GND 3 20

A2–A0 VI = VCC or GND 2.3 V to 5.5 V

4 5

pFRESET 4 5

SCL VI = VCC or GND, Switch OFF 20 28

Cio(off) (3) SDA VI = VCC or GND, Switch OFF 2.3 V to 5.5 V 20 28 pF

SC7–SC0, SD7–SD0 5.5 7.5

RON Switch-on resistance VO = 0.4 V, IO = 15 mA 4.5 V to 5.5 V 4 10 20

Ω3 V to 3.6 V 5 12 30

VO = 0.4 V, IO = 10 mA 2.3 V to 2.7 V 7 15 45

(1) All typical values are at nominal supply voltage (2.5-, 3.3-, or 5-V VCC), TA = 25°C.

(2) The power-on reset circuit resets the I2C bus logic with VCC < VPORF.

(3) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.

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TEXAS INSTRUMENTS

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)

MIN MAX UNIT

STANDARD MODE

fscl I2C clock frequency 0 100 kHz

tsch I2C clock high time 4 μs

tscl I2C clock low time 4.7 μs

tsp I2C spike time 50 ns

tsds I2C serial-data setup time 250 ns

tsdh I2C serial-data hold time 0(1) μs

ticr I2C input rise time 1000 ns

ticf I2C input fall time 300 ns

tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 300 ns

tbuf I2C bus free time between stop and start 4.7 μs

tsts I2C start or repeated start condition setup 4.7 μs

tsth I2C start or repeated start condition hold 4 μs

tsps I2C stop condition setup 4 μs

tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 μs

tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 μs

tvd(ack) Valid-data time of ACK condition ACK signal from SCL low

to SDA output low 1 μs

CbI2C bus capacitive load 400 pF

FAST MODE

fscl I2C clock frequency 0 400 kHz

tsch I2C clock high time 0.6 μs

tscl I2C clock low time 1.3 μs

tsp I2C spike time 50 ns

tsds I2C serial-data setup time 100 ns

tsdh I2C serial-data hold time 0(1) μs

ticr I2C input rise time 20 + 0.1Cb

(2) 300 ns

ticf I2C input fall time 20 + 0.1Cb

(2) 300 ns

tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 20 + 0.1Cb

(2) 300 ns

tbuf I2C bus free time between stop and start 1.3 μs

tsts I2C start or repeated start condition setup 0.6 μs

tsth I2C start or repeated start condition hold 0.6 μs

tsps I2C stop condition setup 0.6 μs

tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 μs

tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 μs

tvd(ack) Valid-data time of ACK condition ACK signal from SCL low

to SDA output low 1 μs

CbI2C bus capacitive load 400 pF

(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge

the undefined region of the falling edge of SCL.

(2) Cb = total bus capacitance of one bus line in pF.

(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-2).

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6.7 Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

tW(L) Pulse duration, RESET low 6 ns

tREC(STA) Recovery time from RESET to start 0 ns

6.8 Switching Characteristics

over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-1)

PARAMETER FROM

(INPUT)

(OUTPUT) MIN MAX UNIT

tpd (1) Propagation delay time RON = 20 Ω, CL = 15 pF SDA or SCL SDn or SCn 0.3 ns

RON = 20 Ω, CL = 50 pF SDA or SCL SDn or SCn 1

trst (2) RESET time (SDA clear) RESET SDA 500 ns

(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load

capacitance, when driven by an ideal voltage source (zero output impedance).

(2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,

signaling a stop condition. It must be a minimum of tWL.

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TEXAS INSTRUMENTS

6.9 Typical Characteristics

Cb (pF)

Rp(max) (kOhm)

0 50 100 150 200 250 300 350 400 450

D008

Standard-mode

Fast-mode

Standard-mode (fSCL = 100

kHz, tr = 1 µs)

Fast-mode (fSCL= 400 kHz, tr =

300 ns)

Figure 6-1. Maximum Pull-Up Resistance (Rp(max)) vs Bus

Capacitance (Cb)

VDPUX (V)

Rp(min) (kOhm)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

D009

VDPUX > 2V

VDPUX <= 2

VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V

VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V

Figure 6-2. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up

Reference Voltage (VDPUX)

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ﬂ TEXAS INSTRUMENTS

7 Parameter Measurement Information

SCL

SDA

SDA LOADCONFIGURATION

2,3

VCC

R =1k

C =50pF

(seeNote A)

DUT

SDA

ThreeBytesforComplete

DeviceProgramming

Stop

Condition

(P)

Start

Condition

(S)

Address

Bit7

(MSB)

Address

Bit6

Address

Bit1

Bit0

(LSB)

WACK

(A)

Data

Bit7

(MSB)

Data

Bit0

(LSB)

Stop

Condition

(P)

0.7 V´CC

0.3 V´CC

VOLTAGEWAVEFORMS

Startor

RepeatStart

Condition

RepeatStart

Condition Stop

Condition

BYTE DESCRIPTION

I Caddress

P-portdata

0.7 V´CC

0.3 V´CC

tscl tsch

tbuf

ticf

ticr

tsth

ticr

tsds

tsp

tsdh

tvd(ack)

tvdH(Data)

tsts

tsps

tvdL(Data)

A. CL includes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.

C. Not all parameters and waveforms are applicable to all devices.

Figure 7-1. I2C Load Circuit and Voltage Waveforms

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{5‘ TEXAS INSTRUMENTS

SDA

SCL

Start

ACK or Read Cycle

tREC

RESET

0.3 VCC

tRESET

SDn, SCn

RL= 1 kW

VCC

CL= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

DUT SDA

VCC/2

tRESET

A. CL includes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.

C. I/Os are configured as inputs.

D. Not all parameters and waveforms are applicable to all devices.

Figure 7-2. Reset Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The PCA9548A is a 8-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed

to eight channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as

well as any combination of the eight channels.

The device offers an active-low RESET input which resets the state machine and allows the PCA9548A to

recover if one of the downstream I2C buses get stuck in a low state. The state machine of the device can also be

reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a

POR cause all channels to be deselected.

The connections of the I2C data path are controlled by the same I2C master device that is switched to

communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware

selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected

channels.

The PCA9548A may also be used for voltage translation, allowing the use of different bus voltages on each

SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using

external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.

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l TEXAS INSTRUMENTS L, L, L L, 74] J .— +40—h ¢—> ‘— .— AL A A a

8.2 Functional Block Diagram

PCA9548A

SC0

SC1

SC2

SC3

SC4

SC5

SC6

SC7

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

GND

VCC

RESET

SCL

SDA

SwitchControlLogic

ResetCircuit

InputFilter

I CBusControl

8.3 Feature Description

The PCA9548A is an 8-channel, bidirectional translating switch for I2C buses that supports Standard-Mode

(100 kHz) and Fast-Mode (400 kHz) operation. The PCA9548A features I2C control using a single 8-bit control

Depending on the application, voltage translation of the I2C bus can also be achieved using the PCA9548A to

allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on

the I2C bus enters a fault state, the PCA9548A can be reset to resume normal operation using the RESET pin

feature or by a power-on reset which results from cycling power to the device.

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8.4 Device Functional Modes

8.4.1 RESET Input

The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal

is asserted low for a minimum of tWL, the PCA9548A resets its registers and I2C state machine and deselects all

channels. The RESET input must be connected to VCC through a pull-up resistor.

8.4.1.1 RESET Errata

If RESET voltage set higher than VCC, current flows from RESET pin to VCC pin.

8.4.1.1.1 System Impact

VCC is pulled above its regular voltage level.

8.4.1.1.2 System Workaround

Design such that RESET voltage is same or lower than VCC.

8.4.2 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition

until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I2C

state machine initialize to their default states. After that, VCC must be lowered to below VPOR and then back up to

the operating voltage for a power-reset cycle.

8.5 Programming

8.5.1 I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 8-1). After the start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must

not be changed between the start and the stop conditions.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 8-2).

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 8-1).

Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure

8-3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the

master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times

must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a stop condition.

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SDA

SCL

Start Condition

Stop Condition

Figure 8-1. Definition of Start and Stop Conditions

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 8-2. Bit Transfer

Data Output

by Transmitter

SCL From

Master

Start

Condition

1 2 8 9

Data Output

by Receiver

Clock Pulse for

Acknowledgment

NACK

ACK

Figure 8-3. Acknowledgment on I2C Bus

8.6 Register Maps

8.6.1 Device Address

Figure 8-4 shows the address byte of the PCA9548A.

1 1 1 0 A1A2 A0

Slave Address

R/W

Fixed Hardware

Selectable

Figure 8-4. PCA9548A Address

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The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read

is selected, while a low (0) selects a write operation.

Table 8-1 shows the PCA9548A address reference.

Table 8-1. Address Reference

INPUTS I2C BUS SLAVE ADDRESS

A2 A1 A0

L L L 112 (decimal), 70 (hexadecimal)

L L H 113 (decimal), 71 (hexadecimal)

L H L 114 (decimal), 72 (hexadecimal)

L H H 115 (decimal), 73 (hexadecimal)

H L L 116 (decimal), 74 (hexadecimal)

H L H 117 (decimal), 75 (hexadecimal)

H H L 118 (decimal), 76 (hexadecimal)

H H H 119 (decimal), 77 (hexadecimal)

8.6.2 Control Register

Following the successful acknowledgment of the address byte, the bus master sends a command byte that

is stored in the control register in the PCA9548A (see Figure 8-5). This register can be written and read via

the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects

this channel. Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the

channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn

lines are in a high state when the channel is made active, so that no false conditions are generated at the time

of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are

received by the PCA9548A, it saves the last byte received.

ChannelSelectionBits(Read/Write)

Channel1

Channel0

Channel2

Channel3

Channel4

Channel5

Channel6

Channel7

B7 B6 B5 B4 B3 B2 B1 B0

Figure 8-5. Control Register

Table 8-2 shows the PCA9548A Command byte definition.

Table 8-2. Command Byte Definition

CONTROL REGISTER BITS COMMAND

B7 B6 B5 B4 B3 B2 B1 B0

X X X X X X X 0 Channel 0 disabled

1 Channel 0 enabled

X X X X X X 0XChannel 1 disabled

1 Channel 1 enabled

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Table 8-2. Command Byte Definition (continued)

CONTROL REGISTER BITS COMMAND

B7 B6 B5 B4 B3 B2 B1 B0

XXXXX0X X Channel 2 disabled

1 Channel 2 enabled

XXXX0XXXChannel 3 disabled

1 Channel 3 enabled

XXX0XXXXChannel 4 disabled

1 Channel 4 enabled

X X 0XXXXXChannel 5 disabled

1 Channel 5 enabled

X0XXXXXXChannel 6 disabled

1 Channel 6 enabled

0XXXXXXXChannel 7 disabled

1 Channel 7 enabled

0 0 0 0 0 0 0 0 No channel selected, power-up/reset

default state

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TEXAS INSTRUMENTS . . . . . . . S . . . . . . . f f f f f Start Condition RIW ACK From Slave ACK From Slave Stop Condition f f f f i start Condilion RIW ACK From Slave NACK From Master Slop Condilion

8.6.3 Bus Transactions

Data is exchanged between the master and PCA9548A through write and read commands.

8.6.3.1 Writes

Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to

a logic 0 (see Figure 8-4 for device address). The command byte is sent after the address and determines which

SCn/SDn channel receives the data that follows the command byte (see Figure 8-6). There is no limitation on the

number of data bytes sent in one write transmission.

A AS 1 1 1 0 A2 A1 A0 0

Start Condition

SDA

R/W ACK From Slave ACK From Slave

B0B1B2B3B4B5B6B7

Stop Condition

Slave Address Control Register

Figure 8-6. Write to Control Register

8.6.3.2 Reads

The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 8-4 for device

address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.

After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the SCn/SDn

channel defined by the command byte then is sent by the PCA9548A (see Figure 8-7). After a restart, the value

of the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed when the

restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse. There is

no limitation on the number of data bytes received in one read transmission, but when the final byte is received,

the bus master must not acknowledge the data.

AS 1 1 1 0 A2 A1 A0 1

SDA PB3 B2 B1 B0

Start Condition R/W ACK From Slave NACK From Master Stop Condition

Slave Address Control Register

B7 B6 B5 B4 NA

Figure 8-7. Read From Control Register

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9 Application Information Disclaimer

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

Applications of the PCA9548A contain an I2C (or SMBus) master device and up to eight I2C slave devices.

The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if eight identical

digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1,

2, and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled

and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the

next channel.

In an application where the I2C bus contains many additional slave devices that do not result in I2C slave

address conflicts, these slave devices can be connected to any desired channel to distribute the total bus

capacitance across multiple channels. If multiple switches are enabled simultaneously, additional design

requirements must be considered (See the Design Requirements and Detailed Design Procedure sections).

9.2 Typical Application

A typical application of the PCA9548A contains 1 or many separate data pull-up voltages, VCC , one for

the master device and one for each of the selectable slave channels, 0 through 7. In the event where the

master device and all slave devices operate at the same voltage, then the VCC pin can be connected to this

supply voltage. In an application where voltage translation is necessary, additional design requirements must be

considered (See the Design Requirements section).

Figure 9-1 shows an application in which the PCA9548A can be used.

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} \I>I, II, } 1\{, 1f 1} 1} I 5 D D S 5 A a 4 0‘ % A C P D 7 ZION % e

PCA9548A

SD1

SDA Channel 0

Channel 1

Channel 2

Channel 3

See Note A

I2C/SMBus

Master SCL

RESET

SC1

SD2

SC2

SD3

SC3

SD0

SC0

VCC = 2.7 V to 5.5 V

VCC = 3.3 V

VCC = 2.7 V to 5.5 V

See Note A

SDA

SCL

GND

SD5

Channel 4

Channel 5

Channel 6

Channel 7

See Note A

SC5

SD6

SC6

SD7

SC7

SD4

SC4

VCC = 2.7 V to 5.5 V

See Note A

RESET

A. Pin numbers shown are for the PW and RTW packages.

Figure 9-1. PCA9548A Typical Application Schematic

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9.2.1 Design Requirements

The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9548A. These pins

may be tied directly to GND or VCC in the application.

If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to

GND on the master side is the sum of the currents through all pull-up resistors, Rp.

The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the

maximum voltage that is passed from one I2C bus to another.

Figure 9-2 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated

using data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9548A to act

as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example,

if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or

below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 9-2, Vpass(max) is 2.7 V when

the PCA9548A supply voltage is 4 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up

resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 9-1).

9.2.2 Detailed Design Procedure

Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up

resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a

function of the reference voltage of the specific I2C channel (VDPUX), VOL,(max), and IOL as shown in Equation 1.

DPUX OL(max)

p(min)

V V



(1)

The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL

= 400 kHz) and bus capacitance, Cbis given by Equation 2.

p(max)

R0.8473 C

(2)

The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus

capacitance can be approximated by adding the capacitance of the PCA9548A, Cio(OFF), the capacitance of

wires, connections, traces, and the capacitance of each individual slave on a given channel. If multiple channels

are activated simultaneously, each of the slaves on all channels contribute to total bus capacitance.

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9.2.3 Application Curves

VCC (V)

Vpass (V)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

D007

25ºC (Room Temperature)

85ºC

-40ºC

Standard-mode (fSCL kHz, trSPACE (fSCL kHz, tr)

Figure 9-2. Pass-Gate Voltage (Vpass) vs Supply

Voltage (VCC) at Three Temperature Points

Cb (pF)

Rp(max) (kOhm)

0 50 100 150 200 250 300 350 400 450

D008

Standard-mode

Fast-mode

Standard-mode (fSCL = 100

kHz, tr = 1 µs)

Fast-mode (fSCL = 400 kHz, tr

= 300 ns)

Figure 9-3. Maximum Pull-Up Resistance (Rp(max))

vs Bus Capacitance (Cb)

VDPUX (V)

Rp(min) (kOhm)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

D009

VDPUX > 2V

VDPUX <= 2

VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V

VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V

Figure 9-4. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VDPUX)

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10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, PCA9548A can be reset to its default conditions by using the power-on

reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.

VCC

Ramp-Up Re-Ramp-Up

Time to Re-Ramp

Time

Ramp-Down

VCC_RT VCC_RT

VCC_FT

VCC_TRR_GND

Figure 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC

VCC

Ramp-Up

Time to Re-Ramp

Time

Ramp-Down

VIN drops below POR levels

VCC_RT

VCC_FT

VCC_TRR_VPOR50

Figure 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC

Table 10-1 specifies the performance of the power-on reset feature for PCA9548A for both types of power-on

reset.

Table 10-1. Recommended Supply Sequencing And Ramp Rates (1)

PARAMETER MIN TYP MAX UNIT

VCC_FT Fall rate See Figure 10-1 1 100 ms

VCC_RT Rise rate See Figure 10-1 0.01 100 ms

VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 10-1 0.001 ms

VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 10-2 0.001 ms

VCC_GH

Level that VCCP can glitch down to, but not cause a functional

disruption when VCCX_GW = 1 μs See Figure 10-3 1.2 V

VCC_GW

Glitch width that will not cause a functional disruption when

VCCX_GH = 0.5 × VCCx

See Figure 10-3 μs

VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V

VPORR Voltage trip point of POR on rising VCC 1.033 1.428 V

(1) TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and

the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide

more information on how to measure these specifications.

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VCC

Time

VCC_GH

VCC_GW

Figure 10-3. Glitch Width And Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and

all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR

differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this

specification.

VCC

VPOR

VPORF

Time

POR

Time

Figure 10-4. VPOR

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11 Layout

11.1 Layout Guidelines

For PCB layout of the PCA9548A, common PCB layout practices must be followed but additional concerns

related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C

signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are

connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours

and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,

using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller

capacitor to filter out high-frequency ripple.

In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same

potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In

an application where voltage translation is required, VDPUM and VDPU0 – VDPU7 may all be on the same layer of

the board with split planes to isolate different voltage potentials.

To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short

as possible and the widths of the traces must also be minimized (For example, 5-10 mils depending on copper

weight).

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11.2 Layout Example

SD7

SC7

SD6

SC6

SC4

SD4

SD0

RESET

SC0

SD1

SC1

GND

VCC

SDA

SCL

SD3

SC3

SD2

SC2

VDPU0

Via to Power Plane

Partial Power Plane

VDPUM

Via to GND Plane

Copper Pour

VCC

GND

By-pass/de-coupling

capacitors

PCA9548A

GND

To I2C Master

To Slave Channel 0

LEGEND

SC5

SD5

(inner layer)

(outer layer)

VDPU2

To Slave Channel 2

VDPU1

To Slave Channel 1

VDPU6

To Slave Channel 6

VDPU5

To Slave Channel 5

VDPU3

To Slave Channel 3

VDPU4

To Slave Channel 4

VDPU7

To Slave Channel 7

12 13

PW package

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Related Documentation

For related documentation see the following:

•I2C Bus Pull-Up Resistor Calculation

•Maximum Clock Frequency of I2C Bus Using Repeaters

•Introduction to Logic

•Understanding the I2C Bus

•Choosing the Correct I2C Device for New Designs

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly

digest of product information that has changed (if any). For change details, check the revision history of any

revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

PCA9548ADB ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples

PCA9548ADBG4 ACTIVE SSOP DB 24 60 TBD Call TI Call TI -40 to 85 Samples

PCA9548ADBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples

PCA9548ADGV NRND TVSOP DGV 24 TBD Call TI Call TI -40 to 85

PCA9548ADGVR ACTIVE TVSOP DGV 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples

PCA9548ADW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9548A Samples

PCA9548ADWG4 ACTIVE SOIC DW 24 25 TBD Call TI Call TI -40 to 85 Samples

PCA9548ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9548A Samples

PCA9548APWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples

PCA9548APWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PD548A Samples

PCA9548ARGER NRND VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PD548A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

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(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

I TEXAS INSTRUMENTS 5:. V.’

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

PCA9548ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1

PCA9548ADGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PCA9548ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

PCA9548APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

PCA9548ARGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PCA9548ADBR SSOP DB 24 2000 356.0 356.0 35.0

PCA9548ADGVR TVSOP DGV 24 2000 356.0 356.0 35.0

PCA9548ADWR SOIC DW 24 2000 350.0 350.0 43.0

PCA9548APWR TSSOP PW 24 2000 356.0 356.0 35.0

PCA9548ARGER VQFN RGE 24 3000 356.0 356.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

PCA9548ADB DB SSOP 24 60 530 10.5 4000 4.1

PCA9548ADW DW SOIC 24 25 506.98 12.7 4826 6.6

Pack Materials-Page 3

I TEXAS INSTRUMENTS

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

RGE 24 VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4204104/H

nnm :) ‘ W # gnmnmnAT Q NOTES: INSTRUMBU'S

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PACKAGE OUTLINE

www.ti.com

4224376 / C 07/2021

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RGE0024C

0.08 C

0.1 C A B

0.05 C

SYMM

4.1

3.9

4.1

3.9

PIN 1 INDEX AREA

1 MAX

0.05

0.00

SEATING PLANE

2X 2.5

2.1±0.1

2.5

20X 0.5

712

24X 0.30

0.18

24X 0.50

0.30

(0.2) TYP

PIN 1 ID

(OPTIONAL)

{mm ~~~~~~~~~ J

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

EXAMPLE BOARD LAYOUT

4224376 / C 06/2021

www.ti.com

VQFN - 1 mm max height

RGE0024C

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

(0.8)

2X(0.8)

(3.8)

( 2.1)

712

24X (0.6)

24X (0.24)

20X (0.5)

(R0.05)

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

(Ø0.2) VIA

TYP

(3.8)

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

EXAMPLE STENCIL DESIGN

4224376 / C 06/2021

www.ti.com

VQFN - 1 mm max height

RGE0024C

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED COVERAGE BY AREA

SCALE: 20X

(3.8)

(0.57)

TYP

(0.57)

TYP

4X ( 0.94)

712

1924

24X (0.24)

24X (0.6)

20X (0.5)

(R0.05) TYP

METAL

TYP

(3.8)

I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL ﬁg

www.ti.com

PACKAGE OUTLINE

22X 0.65

7.15

24X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

NOTE 4

4.5

4.3

NOTE 3

7.9

7.7

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

12 13

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.000

gmmmﬂgmmﬁj ‘w“““‘+“‘w““‘ Emma—5% R

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

12 13

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

ﬁﬂmmmmmﬁmmmﬁ$% Emma—5%g

www.ti.com

EXAMPLE STENCIL DESIGN

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

12 13

MECHANICAL DATA DW «#:5075220 JLASW‘ SMALL 0U J\L HHHHHHHHHHHH’ﬁ N A AH Hnec' d'vnensm m ‘mmes (mammaers) D'ws'nmng md tu‘ermc'mq per ASME w 5M 1994, B TH: drawmq ‘5 Sn :0 change wan: nohce. a Body dimensmns ca nut inc‘ude mom ﬂcsh ur mum" rut m exceed 0035 (055) D FONS WMHH JEDEC MSiOH vermin" ADV NOTES: {if TEXAS INSTRUMENTS wwvmi .com

oo A‘ioyi 55 ﬁHHHHHHHHHHHHﬁ {'3 TEXAS INSTRUMENTS

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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