Texas Instruments 的 CD54,74HC(T)243 规格书

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CDx4HC243, CDx4HCT243 High-Speed CMOS Logic Quad-Bus Transceiver with

Three-State Outputs

1 Features

• Typical propagation delay (A to B, B to A) of 7ns at

VCC = 5 V, CL = 15pF, TA = 25oC

• Three-state outputs

• Buffered inputs

• Fanout (over temperature range)

– Standard outputs : 10 LSTTL loads

– Bus driver outputs : 15 LSTTL loads

• Wide operating temperature range : -55oC to

125oC

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

logic ICs

• HC types

– 2 V to 6 V Operation

– High noise immunity: NIL = 30%, NIH = 30% of

VCC at VCC = 5V

• HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatibility, VIL= 0.8

V (Max), VIH = 2 V (Min)

– CMOS input compatibility, Il ≤ 1µA at VOL, VOH

2 Description

The CDx4HC243 and CDx4HCT243 are quad bus

transceivers with 3-state outputs. The OEA and OEB

inputs control both the high-impedance state as well

as the direction of communication through the device.

Device Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM)

CD54HC243F CDIP (14) 19.55 mm × 6.71 mm

CD74HC243E PDIP (14) 19.31 mm × 6.35 mm

CD74HC243M SOIC (14) 8.65 mm × 3.90 mm

CD74HCT243E PDIP (14) 19.31 mm × 6.35 mm

CD74HCT243M SOIC (14) 8.65 mm × 3.90 mm

(1) For all packages see the orderable addendum at the end of

the datasheet.

Ax Bx

OEB

OEA

1 of 4 Channels

Functional Block Diagram

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

I TEXAS INSTRUMENTS

Table of Contents

1 Features............................................................................1

2 Description.......................................................................1

3 Revision History.............................................................. 2

4 Pin Configuration and Functions...................................3

5 Specifications.................................................................. 4

5.1 Absolute Maximum Ratings........................................ 4

5.2 Recommended Operating Conditions.........................4

5.3 Thermal Information....................................................4

5.4 Electrical Characteristics.............................................5

5.5 Switching Characteristics............................................6

6 Parameter Measurement Information............................ 7

7 Detailed Description........................................................8

7.1 Overview..................................................................... 8

7.2 Functional Block Diagram........................................... 8

7.3 Device Functional Modes............................................8

8 Power Supply Recommendations..................................9

9 Layout...............................................................................9

9.1 Layout Guidelines....................................................... 9

10 Device and Documentation Support..........................10

10.1 Documentation Support.......................................... 10

10.2 Receiving Notification of Documentation Updates..10

10.3 Support Resources................................................. 10

10.4 Trademarks.............................................................10

10.5 Electrostatic Discharge Caution..............................10

10.6 Glossary..................................................................10

11 Mechanical, Packaging, and Orderable

Information.................................................................... 10

3 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (October 2003) to Revision E (March 2022) Page

• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect

modern data sheet standards............................................................................................................................. 1

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022 www.ti.com

Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243

l TEXAS INSTRUMENTS

4 Pin Configuration and Functions

J, N, or D Package

14-Pin CDIP, PDIP, or SOIC

Top View

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CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022

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5 Specifications

5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage -0.5 7 V

IIK Input diode current For VI < -0.5V or VO > VCC + 0.5V ±20 mA

IOK Output diode current For VC < -0.5V or VO > VCC + 0.5V ±20 mA

IODrian Current, per output For -0.5V < VO < VCC + 0.5V ±35 mA

Output source or sink current per

output pin For VO > -0.5V or VO < VCC + 0.5V ±25 mA

Continuous current through VCC or GND ±70 mA

Tstg Storage temperature range -65 150 °C

TJJunction temperature 150 °C

Lead temperature (Soldering 10s)(SOIC - Lead Tips Only) 300 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

MIN MAX UNIT

VCC Supply voltage range HC Types 2 6 V

HCT Types 4.5 5.5

VIInput voltage 0 VCC V

VOOutput voltage 0 VCC V

ttInput rise and fall time

VCC = 2V 1000

nsVCC = 4.5V 500

VCC = 6V 400

TATemperature Range -55 125 °C

5.3 Thermal Information

THERMAL METRIC

N (PDIP) D (SOIC)

UNIT14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance(1) 80 86 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

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Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243

TEXAS INSTRUMENTS

5.4 Electrical Characteristics

PARAMETER TEST

CONDITIONS(1) VCC (V) 25°C -40°C to 85°C -55°C to 125°C UNIT

MIN TYP MAX MIN MAX MIN MAX

HC TYPES

VIH High-level input voltage

2 1.5 1.5 1.5

V4.5 3.15 3.15 3.15

6 4.2 4.2 4.2

VIL Low-level input voltage

2 0.5 0.5 0.5

V4.5 1.35 1.35 1.35

6 1.8 1.8 1.8

VOH

High-level output voltage

CMOS loads

IOH = – 20μA 2 1.9 1.9 1.9

IOH = – 20μA 4.5 4.4 4.4 4.4

IOH = – 20μA 6 5.9 5.9 5.9

High-level output voltage

TTL loads

IOH = – 6mA 4.5 3.98 3.84 3.7

IOH = – 7.8mA 6 5.48 5.34 5.2

VOL

Low-level output voltage

CMOS loads

IOL = 20μA 2 0.1 0.1 0.1

IOL = 20μA 4.5 0.1 0.1 0.1

IOL = 20μA 6 0.1 0.1 0.1

Low-level output voltage

TTL

IOL = 6mA 4.5 0.26 0.33 0.4

IOL = 7.8mA 6 0.26 0.33 0.4

IIInput leakage current VCC or GND 6 ±0.1 ±1 ±1 µA

ICC Supply Current VCC or GND 6 8 80 160 µA

IOZ

Three-state leakage

current VIL or VIH 6 ±0.5 ±0.5 ±10 µA

HCT TYPES

VIH High-level input voltage 4.5 to 5.5 2 2 2 V

VIL Low-level input voltage 4.5 to 5.5 0.8 0.8 0.8 V

VOH

High-level output voltage

CMOS loads IOH = – 20μA 4.5 4.4 4.4 4.4

High-level output voltage

TTL loads IOH = – 6mA 4.5 3.98 3.84 3.7

VOL

Low-level output voltage

CMOS loads IOL = 20μA 4.5 0.1 0.1 0.1

Low-level output voltage

TTL loads IOL = 6mA 4.5 0.26 0.33 0.4

IIInput leakage current VCC to GND 5.5 ±0.1 ±1 ±1 µA

ICC Supply current VCC or GND 5.5 8 80 160 µA

∆ICC (2)

(3)

Additional supply current

per input pin

One of An or Bn 4.5 to 5.5 100 396 495 539

µA

One of OEA or

OEB 4.5 to 5.5 100 216 270 294

IOZ

Three-state leakage

current VIL or VIH 5.5 ±0.5 ±5 ±10 µA

(1) VI = VIH or VIL, unless otherwise noted.

(2) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.

(3) Inputs held at VCC – 2.1.

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CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022

Product Folder Links: CD54HC243 CD74HC243 CD54HCT243 CD74HCT243

TEXAS INSTRUMENTS

5.5 Switching Characteristics

Input tt = 6ns. Unless otherwise specified, CL = 50pF

PARAMETER VCC (V) 25°C -40°C to

85°C

-55°C to

125°C UNIT

TYP MAX MAX MAX

HC TYPES

tpd Propagation delay data to outputs

2 90 115 135

ns4.5 7(1) 18 23 27

6 15 20 23

tPZL, tPZH Output high-Z, to high level to low level

2 150 190 225

ns4.5 12(1) 30 38 45

6 26 33 38

tPHZ, tPLZ

Output high level, output low level to

high-Z

2 150 190 225

ns4.5 12(1) 30 38 45

6 26 33 38

ttOutput transition times

2 60 75 90

ns4.5 12 15 18

6 10 13 15

CiInput capacitance 10 10 10 pF

COThree-state output capacitance 20 20 20 pF

Cpd (2) (3) Power dissipation capacitance 5 80 pF

HCT TYPES

tpd Propagation delay data to outputs 4.5 9(1) 22 28 33 ns

tPZH, tPLZ Output high-Z to high level to low level 4.5 14(1) 34 43 51 ns

tPHZ, tPLZ

Output high level, output low level to

high-Z 4.5 14(1) 35 44 53 ns

ttOutput transition times 4.5 12 15 18 ns

CiInput capacitance 10 10 10 pF

COThree-state output capacitance 20 20 20 pF

Cpd (2) (3) Power dissipation capacitance 5 91 pF

(1) Typical value tested at 5V, CL = 15pF.

(2) CPD is used to determine the dynamic power consumption, per channel.

(3) PD = VCC 2fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

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TEXAS INSTRUMENTS t, = 6n: + Vcc INPUY GND ‘THL’ INVERTING OUTPUT * ‘PHL + * ‘PLH + ouTPuT Vcc DISAELE GND‘ OUTPUT HIGH 507. To OFF OUTPUIS a OllTPUTS .7 OUYFUTS ENABLED DISABLED ENABLED UIHER 0- INPUTS 0- Ic WI'IH TIED HIGH 0- THREE- 0R Low 0- STATE ouTPuT °_ OUTPUT D‘SABLE t, = Ens + av INPUT 6ND kML INVERTING OUTPUT x, a e Ens * Ens ouTPuT 3V DmaLE 0.3 6ND + om - OUTPUT Low To oﬂ= OU'IPU'I HIGH To oﬂ= 1.3V ourFuTs a OUTPUTS k OUTPUTS ENABLED DISABLED EMAILED Vcc FDR M; AND lrxL GND FOR beAnD I,"

6 Parameter Measurement Information

tPD is the maximum between tPLH and tPHL

tt is the maximum between tTLH and tTHL

Figure 6-1. HC and HCT transition times and

propagation delay times, combination logic

Figure 6-2. HCT transition times and tpopationg

delay times, combination logic

Figure 6-3. HC three-state propagation delay

waveform

Figure 6-4. HCT three-state propagation delay

waveform

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test

circuit is Output RL = 1kΩ to VCC, CL = 50pF.

Figure 6-5. HC and HCT three-state propagation delay test circuit

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CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

SCHS168E – NOVEMBER 1998 – REVISED MARCH 2022

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I TEXAS INSTRUMENTS _&

7 Detailed Description

7.1 Overview

The CDx4HC243 and CDx4HCT243 silicon-gate CMOS three-state bidirectional noninverting buffers are

intended for two-way asynchronous communication between data buses. They have high-drive-current outputs

that enable high-speed operation when driving large bus capacitances. These circuits possess the low power

dissipation of CMOS circuits and have speeds comparable to low-power Schottky TTL circuits. They can drive

15 LSTTL loads.

The states of the output-enable (OEB, OEA) inputs determine both the direction of flow (A to B, B to A), and the

three-state mode.

7.2 Functional Block Diagram

Ax Bx

OEB

OEA

1 of 4 Channels

Figure 7-1. Functional Diagram

7.3 Device Functional Modes

Table 7-1. Truth Table(1)(2)

Control Inputs HC, HCT243 Series

Data port status

OEB OEA An Bn

H H O I

L H Z Z

H L Z Z

L L I O

(1) H = High voltage level. L = Low voltage level. I = Input. O =

Output (Same level as input). Z = High Impedance

(2) To prevent excess currents in the High Z modes all I/O terminals

hsould be terminated with 10kΩ to 1MΩ resistors.

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8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power

disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps

to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The

bypass capacitor should be installed as close to the power terminal as possible for best results.

9 Layout

9.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many

cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a

triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left

unconnected because the undefined voltages at the outside connections result in undefined operational states.

All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the

input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular

unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever

makes more sense for the logic function or is more convenient.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

10.1 Documentation Support

10.1.1 Related Documentation

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

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PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

8409001CA ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 8409001CA

CD54HC243F3A Samples

CD54HC243F ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 CD54HC243F Samples

CD54HC243F3A ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 8409001CA

CD54HC243F3A Samples

CD74HC243E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E Samples

CD74HC243EE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E Samples

CD74HC243M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M Samples

CD74HC243M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M Samples

CD74HC243MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M Samples

CD74HCT243E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT243E Samples

CD74HCT243EE4 ACTIVE PDIP N 14 25 TBD Call TI Call TI -55 to 125 Samples

CD74HCT243M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT243M Samples

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

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(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC243, CD74HC243 :

•Catalog : CD74HC243

•Military : CD54HC243

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Military - QML certified for Military and Defense Applications

Addendum-Page 2

I TEXAS INSTRUMENTS ‘3‘ V.'

PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC243M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HC243MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC243M96 SOIC D 14 2500 356.0 356.0 35.0

CD74HC243MT SOIC D 14 250 210.0 185.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

CD74HC243E N PDIP 14 25 506 13.97 11230 4.32

CD74HC243EE4 N PDIP 14 25 506 13.97 11230 4.32

CD74HC243M D SOIC 14 50 506.6 8 3940 4.32

CD74HCT243E N PDIP 14 25 506 13.97 11230 4.32

CD74HCT243M D SOIC 14 50 506.6 8 3940 4.32

Pack Materials-Page 3

MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘ﬁ: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): noﬁce /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmﬂder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkﬂh INSI'RUMENTS www.1i.com

GENERIC PACKAGE VIEW J 14 CDIP - 5.08 mm max heigm CERAMIC DUAL IN LINE PACKAGE [I l l 'I I.“ Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the produd dala sheel for package details. 4040053756 I TEXAS INSTRI IMFNTS

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PACKAGE OUTLINE

14X .008-.014

[0.2-0.36]

TYP

-15

AT GAGE PLANE

-.314.308 -7.977.83[ ]

14X -.026.014 -0.660.36[ ]

14X -.065.045 -1.651.15[ ]

.2 MAX TYP

[5.08] .13 MIN TYP

[3.3]

TYP-.060.015 -1.520.38[ ]

4X .005 MIN

[0.13]

12X .100

[2.54]

.015 GAGE PLANE

[0.38]

-.785.754 -19.9419.15[ ]

B -.283.245 -7.196.22[ ]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for

reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermitically sealed with a ceramic lid using glass frit.

4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.

5. Falls within MIL-STD-1835 and GDIP1-T14.

PIN 1 ID

(OPTIONAL)

SCALE 0.900

SEATING PLANE

.010 [0.25] C A B

www.ti.com

EXAMPLE BOARD LAYOUT

ALL AROUND

[0.05] MAX.002

.002 MAX

[0.05]

ALL AROUND

SOLDER MASK

OPENING

METAL

(.063)

[1.6]

(R.002 ) TYP

[0.05]

14X ( .039)

[1]

( .063)

[1.6]

12X (.100 )

[2.54]

(.300 ) TYP

[7.62]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE: 5X

SEE DETAIL A SEE DETAIL B

SYMM

DETAIL A

SCALE: 15X

SOLDER MASK

OPENING

METAL

DETAIL B

13X, SCALE: 15X

MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam AB, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddiﬁ§n%="" 5.40="" 5,40="" @eeeeeej="" rﬁhﬂ§eﬂhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com

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Texas Instruments 的 CD54,74HC(T)243 规格书

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