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Output Current (A)

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0 4 8 12 16 20

40 0

50 2

60 4

70 6

80 8

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100 12

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VDD = 5 V

VIN = 12 V

VOUT = 1.8 V

LOUT = 0.29 PH

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CSD97394Q4M

SLPS542 –JANUARY 2015

CSD97394Q4M Synchronous Buck NexFET™ Power Stage

1 Features 2 Applications

1• 90% System Efficiency at 15 A • Ultrabook/Notebook DC/DC Converters

• Max Rated Continuous Current 20 A, Peak 45 A • Multiphase Vcore and DDR Solutions

• High Frequency Operation (up to 2 MHz) • Point-of-Load Synchronous Buck in Networking,

Telecom, and Computing Systems

• High Density – SON 3.5 × 4.5 mm Footprint

• Ultra-Low Inductance Package 3 Description

• System Optimized PCB Footprint The CSD97394Q4M NexFET™ Power Stage is a

• Ultra-Low Quiescent (ULQ) Current Mode highly-optimized design for use in a high-power, high-

• 3.3 V and 5 V PWM Signal Compatible density synchronous buck converter. This product

integrates the driver IC and NexFET technology to

• Diode Emulation Mode with FCCM complete the power stage switching function. The

• Input Voltages up to 24 V driver IC has a built-in selectable diode emulation

• Tri-State PWM Input function that enables DCM operation to improve light

load efficiency. In addition, the driver IC supports

• Integrated Bootsrap Diode ULQ mode that enables connected standby for

• Shoot Through Protection Windows®8. With the PWM input in tri-state,

• RoHS Compliant – Lead Free Terminal Plating quiescent current is reduced to 130 µA, with

immediate response. When SKIP# is held at tri-state,

• Halogen Free the current is reduced to 8 µA (typically 20 µs is

required to resume switching). This combination

produces a high current, high efficiency, and high

speed switching device in a small 3.5 × 4.5 mm

outline package. In addition, the PCB footprint is

optimized to help reduce design time and simplify the

completion of the overall system design.

Device Information(1)

ORDER NUMBER PACKAGE MEDIA AND QTY

CSD97394Q4M 13-inch reel 2500

SON 3.5 × 4.5 mm

Plastic Package

CSD97394Q4MT 7-inch reel 250

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

spacer

Application Diagram Typical Power Stage Efficiency and Power Loss

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

l TEXAS INSTRUMENTS

CSD97394Q4M

SLPS542 –JANUARY 2015

www.ti.com

Table of Contents

1 Features.................................................................. 18 Application and Implementation .......................... 9

8.1 Application Information.............................................. 9

2 Applications ........................................................... 18.2 Typical Application ................................................... 9

3 Description ............................................................. 18.1 System Example ..................................................... 12

4 Revision History..................................................... 29 Layout ................................................................... 14

5 Pin Configuration and Functions......................... 39.1 Layout Guidelines ................................................... 14

6 Specifications......................................................... 49.2 Layout Example ...................................................... 14

6.1 Absolute Maximum Ratings ...................................... 49.3 Thermal Considerations.......................................... 14

6.2 ESD Ratings.............................................................. 410 Device and Documentation Support ................. 15

6.3 Recommended Operating Conditions....................... 410.1 Trademarks........................................................... 15

6.4 Thermal Information.................................................. 410.2 Electrostatic Discharge Caution............................ 15

6.5 Electrical Characteristics........................................... 510.3 Glossary................................................................ 15

7 Detailed Description.............................................. 611 Mechanical, Packaging, and Orderable

7.1 Overview ................................................................... 6Information ........................................................... 16

7.2 Functional Block Diagram......................................... 611.1 Mechanical Drawing.............................................. 16

7.3 Feature Description................................................... 611.2 Recommended PCB Land Pattern........................ 17

7.4 Device Functional Modes.......................................... 811.3 Recommended Stencil Opening ........................... 17

4 Revision History

DATE REVISION NOTES

January 2015 * Initial release.

*9 TEXAS INSTRUMENTS

PWM

PGND

VIN

SKIP#

VSW

VDD

PGND

BOOT

BOOT_R

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5 Pin Configuration and Functions

SON 3.5 × 4.5 mm

(Top View)

Pin Functions

PIN DESCRIPTION

NO. NAME

This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the

1 SKIP# Sync FET. When SKIP# is High, the CSD95391Q4M operates in Forced Continuous Conduction Mode. A tri-state

voltage on SKIP# puts the driver into a very low power state.

2 VDD Supply voltage to gate drivers and internal circuitry.

3 PGND Power ground, needs to be connected to Pin 9 and PCB

4 VSW Voltage switching node – pin connection to the output inductor.

5 VIN Input voltage pin. Connect input capacitors close to this pin.

6 BOOT_R Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic cap from BOOT to BOOT_R pins. The

bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. Boot_R is

7 BOOT internally connected to VSW.

Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET

8 PWM gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates

low if greater than the tri-state shutdown hold-off time (t3HT)

9 PGND Power ground

l TEXAS INSTRUMENTS

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6 Specifications

6.1 Absolute Maximum Ratings(1)

TA= 25°C (unless otherwise noted)

MIN MAX UNIT

VIN to PGND –0.3 30 V

VSW to PGND , VIN to VSW –0.3 30 V

VSW to PGND, VIN to VSW (<10 ns) –7 33 V

VDD to PGND –0.3 6 V

PWM, SKIP# to PGND –0.3 6 V

BOOT to PGND –0.3 35 V

BOOT to PGND (<10 ns) –2 38 V

BOOT to BOOT_R –0.3 6 V

BOOT to BOOT_R (duty cycle <0.2%) 8 V

PDPower dissipation 8 W

TJOperating temperature range –40 150 °C

Tstg Storage temperature range –55 150 °C

(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT

Human Body Model (HBM)(1) ±2000

V(ESD) Electrostatic discharge V

Charged Device Model (CDM)(2) ±500

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA= 25° (unless otherwise noted)

MIN MAX UNIT

VDD Gate drive voltage 4.5 5.5 V

VIN Input supply voltage(1) 24 V

IOUT Continuous output current VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, 20 A

ƒSW = 500 kHz, LOUT = 0.29 µH(2)

IOUT-PK Peak output current(3) 45 A

ƒSW Switching frequency CBST = 0.1 µF (min) 2000 kHz

On time duty cycle 85%

Minimum PWM on time 40 ns

Operating temperature –40 125 °C

(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For

reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.

(3) System conditions as defined in Note 2. Peak Output Current is applied for tp= 10 ms, duty cycle ≤1%

6.4 Thermal Information

TA= 25°C (unless otherwise noted)

THERMAL METRIC MIN TYP MAX UNIT

RθJC Junction-to-case (top of package) thermal resistance(1) 22.8 °C/W

RθJB Junction-to-board thermal resistance(2) 2.5

(1) RθJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch

(1.52 mm) thick FR4 board.

(2) RθJB value based on hottest board temperature within 1mm of the package.

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6.5 Electrical Characteristics

TA= 25°C, VDD = POR to 5.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PLOSS

VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,

Power 2.2 W

loss(1) ƒSW = 500 kHz, LOUT = 0.29 µH , TJ= 25°C

VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,

Power 2.4 W

loss(2) ƒSW = 500 kHz, LOUT = 0.29 µH , TJ= 25°C

VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,

Power 3.0 W

loss(2) ƒSW = 500 kHz, LOUT = 0.29 µH , TJ= 125°C

VIN

IQVIN quiescent current PWM = Floating, VDD = 5 V, VIN= 24 V 1 µA

VDD

PWM = Float, SKIP# = VDD or 0 V 130 µA

IDD Standby supply current SKIP# = Float 8 µA

IDD Operating supply current PWM = 50% Duty cycle, ƒSW = 500 kHz 5.3 mA

POWER-ON RESET AND UNDERVOLTAGE LOCKOUT

VDD Rising Power-on reset 4.15 V

VDD Falling UVLO 3.7 V

Hysteresis 0.2 mV

PWM AND SKIP# I/O SPECIFICATIONS

Pull up to VDD 1700

RIInput Impedance kΩ

Pull down (to GND) 800

VIH Logic level high 2.65

VIL Logic level low 0.6 V

VIH Hysteresis 0.2

VTS Tri-state voltage 1.3 2

Tri-state activation time

tTHOLD(off1) 60

(falling) PWM ns

Tri-state activation time (rising)

tTHOLD(off2) 60

PWM

Tri-state activation time

tTSKF 1

(falling) SKIP# µs

Tri-state activation time (rising)

tTSKR 1

SKIP#

t3RD(PWM) Tri-state exit time PWM (2) 100 ns

t3RD(SKIP#) Tri-state exit time SKIP#(2) 50 µs

BOOTSTRAP SWITCH

VFBST Forward voltage IF= 10 mA 120 240 mV

IRLEAK Reverse leakage(2) VBST – VDD = 25 V 2 µA

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.

(2) Specified by design

l TEXAS INSTRUMENTS

SKIP#

PWM

PGND

BOOT

DRVH

VSW

VDD

Level Shift

DRVL

+1 V

1 V

VDD

3-State

Logic

VDD

VUVLO

3-State

Logic

VDD

800k

1.7Meg

800k

1.7Meg

Control

FET

Sync

FET

6 BOOT_R

DRVL

5 VIN

3PGND

CSD97394Q4M

SLPS542 –JANUARY 2015

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7 Detailed Description

7.1 Overview

The CSD97394Q4M NexFET™ Power Stage is a highly optimized design for use in a high-power, high-density

synchronous buck converter.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Powering CSD97394Q4M And Gate Drivers

An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive

power for the MOSFETS. A 1 µF 10 V X5R or higher ceramic capacitor is recommended to bypass VDD pin to

PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply

to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and

BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of the Control FET and

reduce voltage spikes on the VSW node. A typical 1 Ωto 4.7 Ωvalue is a compromise between switching loss

and VSW spike amplitude.

7.3.2 Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control

FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H).,

Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower

UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the

Control FET and Sync FET gates actively low. Figure 1 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP# = Tri-state).

{L} TEXAS INSTRUMENTS

tpdLH

Time

High-Z Window

High-Z

PWM

VSW

High-Z Window VIH

VIL

tpdHL

tHOLD_OFF1 t3RD1 tHOLD_OFF2 t3RD2

VOUT

UDG-12218

VUVLO_H

VUVLO_L

VVDD

Driver On

CSD97394Q4M

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SLPS542 –JANUARY 2015

Feature Description (continued)

Figure 1. UVLO Operation

7.3.3 PWM Pin

The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when

PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin

incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes.

Operation into and out of tri-state mode follows the timing diagram outlined in Figure 2.

When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The

window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The

device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V

(typical) and 5 V (typical) PWM drive signals.

When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#

pin. Normal operation requires this time period in order for the auto-zero comparator to resume.

Figure 2. PWM Tri-State Timing Diagram

7.3.4 SKIP# Pin

The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is

low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current

is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM

mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the

driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent

current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.

Table 1 shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate.

l TEXAS INSTRUMENTS

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SLPS542 –JANUARY 2015

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Feature Description (continued)

Table 1. Logic Functions of the Driver IC

UVLO PWM SKIP# Sync FET Gate Control FET Gate MODE

Active — — Low Low Disabled

Inactive Low Low High(1) Low DCM(1)

Inactive Low High High Low FCCM

Inactive High H or L Low High

Inactive Tri-state H or L Low Low LQ

Inactive — Tri-state Low Low ULQ

(1) Until zero crossing protection occurs.

7.3.4.1 Zero Crossing (ZX) Operation

The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy

load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,

which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects

the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the

rectifying MOSFET.

7.3.5 Integrated Boost-Switch

To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the

conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL

signal.

7.4 Device Functional Modes

Table 1 shows the different functional modes of CSD97394. The diode emulation mode is enabled with SKIP#

pulled low, which improves light load efficiency. With PWM in tri-state, Power Stage enters LQ mode and the

quiescent current is reduced to 130 µA. When SKIP# is held in tri-state, ULQ mode is enabled and the current is

decreased to 8 µA.

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CSD97394Q4M

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SLPS542 –JANUARY 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The Power Stage CSD97394Q4M is a highly optimized design for synchronous buck applications using NexFET

devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest

power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more

systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the

parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such

as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance

in the actual application.

8.2 Typical Application

Figure 3. Application Schematic

l TEXAS INSTRUMENTS

Board Temperature (qC)

Output Current (A)

0 20 40 60 80 100 120 140

D006

Min

Typ

Switching Frequency (kHz)

Power Loss, Normalized

SOA Temperature Adj. (qC)

0 400 800 1200 1600 2000 2400

0.9 -2.4

0.95 -1.2

1 0.0

1.05 1.2

1.1 2.4

1.15 3.6

1.2 4.8

1.25 6.0

1.3 7.2

D007

Ambient Temperature (qC)

Output Current (A)

0 10 20 30 40 50 60 70 80 90

D004

400 LFM

200 LFM

100 LFM

Nat. conv.

Ambient Temperature (qC)

Output Current (A)

0 10 20 30 40 50 60 70 80 90

D005

400 LFM

200 LFM

100 LFM

Nat. conv.

Output Current (A)

Power Loss (W)

2 4 6 8 10 12 14 16 18 20

D002

Typ

Max

TC - Junction Temperature (qC)

Power Loss, Normalized

-50 -25 0 25 50 75 100 125 150

0.5

0.6

0.7

0.8

0.9

1.1

D003

CSD97394Q4M

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Typical Application (continued)

8.2.1 Application Curves

TJ= 125°C, unless stated otherwise

VIN = 12 V VDD = 5 V VOUT = 1.8 V VIN = 12 V VDD = 5 V VOUT = 1.8 V

ƒSW = 500 kHz LOUT = 0.29 µH ƒSW = 500 kHz LOUT = 0.29 µH

Figure 4. Power Loss vs Output Current Figure 5. Power Loss vs Temperature

VIN = 12 V VDD = 5 V VOUT = 1.8 V

VIN = 12 V VDD = 5 V VOUT = 1.8 V ƒSW = 500 kHz LOUT = 0.29 µH

ƒSW = 500 kHz LOUT = 0.29 µH

Figure 7. Safe Operating Area – PCB Vertical Mount (1)

Figure 6. Safe Operating Area – PCB Horizontal Mount (1)

VIN = 12 V VDD = 5 V VOUT = 1.8 V VIN = 12 V VDD = 5 V VOUT = 1.8 V

ƒSW = 500 kHz LOUT = 0.29 µH IOUT = 20 A LOUT = 0.29 µH

Figure 8. Typical Safe Operating Area (1) Figure 9. Normalized Power Loss vs Frequency

l TEXAS INSTRUMENTS s5

TC - Junction Temperature (qC)

Driver Current (mA)

-50 -25 0 25 50 75 100 125 150

7.3

7.6

7.9

8.2

8.5

D012

Output Inductance (nH)

Power Loss, Normalized

SOA Temperature Adj. (qC)

0 100 200 300 400 500 600 700 800 900 1000 1100

0.85 -3.6

0.9 -2.4

0.95 -1.2

1 0.0

1.05 1.2

1.1 2.4

1.15 3.6

1.2 4.8

1.25 6.0

1.3 7.2

D010

Switching Frequency (kHz)

Driver Current (mA)

0 400 800 1200 1600 2000 2400

D011

Input Voltage (V)

Power Loss, Normalized

SOA Temperature Adj. (qC)

2 4 6 8 10 12 14 16 18 20 22 24

0.9 -2.4

0.95 -1.2

1 0.0

1.05 1.2

1.1 2.4

1.15 3.6

1.2 4.8

1.25 6.0

1.3 7.2

D008

Output Voltage (V)

Power Loss, Normalized

SOA Temperature Adj. (qC)

0 0.6 1.2 1.8 2.4 3 3.6

0.7 -7.3

0.8 -4.9

0.9 -2.4

1 0.0

1.1 2.4

1.2 4.9

1.3 7.3

1.4 9.7

D009

CSD97394Q4M

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SLPS542 –JANUARY 2015

Typical Application (continued)

TJ= 125°C, unless stated otherwise

IOUT = 20 A VDD = 5 V VOUT = 1.8 V VIN = 12 V VDD = 5 V IOUT = 20 A

ƒSW = 500 kHz LOUT = 0.29 µH ƒSW = 500 kHz LOUT = 0.29 µH

Figure 10. Normalized Power Loss vs Input Voltage Figure 11. Normalized Power Loss vs Output Voltage

VIN = 12 V VDD = 5 V IOUT = 20 A VIN = 12 V VDD = 5 V IOUT = 20 A

ƒSW = 500 kHz VOUT = 1.8 V LOUT = 0.29 µH VOUT = 1.8 V

Figure 12. Normalized Power Loss vs Output Inductance Figure 13. Driver Current vs Frequency

VIN = 12 V VDD = 5 V VOUT = 1.8 V

IOUT = 20 A LOUT = 0.29 µH

Figure 14. Driver Current vs Temperature

1. The Typical CSD97394Q4M System Characteristic curves are based on measurements made on a PCB

design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz.

copper thickness. See the System Example section for detailed explanation.

l TEXAS INSTRUMENTS CSD97394Q4M m m

Vin

PWM

VDD VDD

SKIP#

PWM

GND

BST

DRVH

DRVL

HSgate

Vsw

LSgate

VIN

VSW

PGND

Gate Drive

Current (IDD)

Gate Drive

Voltage (VDD)

Input Voltage

(VIN)

Averaged Switched

Node Voltage

(VSW_AVG)

Output Current

(IOUT)

Averaging

Circuit

Control

FET

Sync

FET

Input Current (IIN)

CSD97394Q4M

Boot

Boot_R

CBoot Cin

SKIP#

CSD97394Q4M

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8.1 System Example

8.1.1 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss

generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has

provided measured power loss performance curves. Figure 4 plots the power loss of the CSD97394Q4M as a

function of load current. This curve is measured by configuring and running the CSD97394Q4M as it would be in

the final application (see Figure 15). The measured power loss is the CSD97394Q4M device power loss which

consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT)(1)

The power loss curve in Figure 4 is measured at the maximum recommended junction temperature of

TJ= 125°C under isothermal test conditions.

8.1.2 Safe Operating Curves (SOA)

The SOA curves in the CSD97394Q4M datasheet give engineers guidance on the temperature boundaries within

an operating system by incorporating the thermal resistance and system power loss. Figure 6 and Figure 8

outline the temperature and airflow conditions required for a given load current. The area under the curve

dictates the safe operating area. All the curves are based on measurements made on a PCB design with

dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.

8.1.3 Normalized Curves

The normalized curves in the CSD97394Q4M data sheet give engineers guidance on the Power Loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change is system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is

subtracted from the SOA curve.

Figure 15. Power Loss Test Circuit

l TEXAS INSTRUMENTS 24 0mm Currem 4A) u 20 40 so so mu mu mo Euzvd Temperamre cc)

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SLPS542 –JANUARY 2015

System Example (continued)

8.1.3.1 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).

Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the

following procedure will outline the steps engineers should take to predict product performance for any set of

system conditions.

8.1.3.1.1 Design Example

Operating Conditions: Output Current (lOUT) = 10 A, Input Voltage (VIN ) = 7 V, Output Voltage (VOUT) = 1.5 V,

Switching Frequency (ƒSW) = 800 kHz, Output Inductor (LOUT) = 0.2 µH

8.1.3.1.2 Calculating Power Loss

• Typical Power Loss at 10 A = 2.1 W (Figure 4)

• Normalized Power Loss for switching frequency ≈0.99 (Figure 9)

• Normalized Power Loss for input voltage ≈1.10 (Figure 10)

• Normalized Power Loss for output voltage ≈0.93 (Figure 11)

• Normalized Power Loss for output inductor ≈1.10 (Figure 12)

•Final calculated Power Loss = 2.1 W × 0.99 × 1.10 × 0.93 × 1.10 ≈2.3 W

8.1.3.1.3 Calculating SOA Adjustments

• SOA adjustment for switching frequency ≈–0.2°C (Figure 9)

• SOA adjustment for input voltage ≈2.5°C (Figure 10)

• SOA adjustment for output voltage ≈1.0°C (Figure 11)

• SOA adjustment for output inductor ≈2.3°C (Figure 12)

•Final calculated SOA adjustment = –0.2 + 2.5 + (–1.5) + 2.3 ≈3.1°C

Figure 16. Power Stage CSD97394Q4M SOA

In the design example above, the estimated power loss of the CSD97394Q4M would increase to 2.3 W. In

addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.1°C. Figure 16

graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 3.1°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

l TEXAS INSTRUMENTS

CSD97394Q4M

SLPS542 –JANUARY 2015

www.ti.com

9 Layout

9.1 Layout Guidelines

9.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below

is a brief description on how to address each parameter.

9.1.2 Electrical Performance

The CSD97394Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

• The placement of the input capacitors relative to VIN and PGND pins of CSD97394Q4M device should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 17).

The example in Figure 17 uses 1 x 1 nF 0402 25V and 3 x 10 µF 1206 25 V ceramic capacitors (TDK part

number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board

with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the

Power Stage C5, C8 and C6, C19 should follow in order.

• The bootstrap cap CBOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT

and BOOT_R pins.

• The switching node of the output inductor should be placed relatively close to the Power Stage

CSD97394Q4M VSW pins. Minimizing the VSW node length between these two components will reduce the

PCB conduction losses and actually reduce the switching noise level. (1)

9.2 Layout Example

Figure 17. Recommended PCB Layout (Top Down View)

9.3 Thermal Considerations

The CSD97394Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

• Use the smallest drill size allowed in your design. The example in Figure 17 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

• Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

l TEXAS INSTRUMENTS

CSD97394Q4M

www.ti.com

SLPS542 –JANUARY 2015

10 Device and Documentation Support

10.1 Trademarks

NexFET is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

10.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

10.3 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

l TEXAS INSTRUMENTS w: / 53mm; mu: ﬁr mm m“ m J 12x

0.300

(x45°)

CSD97394Q4M

SLPS542 –JANUARY 2015

www.ti.com

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Mechanical Drawing

MILLIMETERS INCHES

DIM MIN NOM MAX MIN NOM MAX

A 0.800 0.900 1.000 0.031 0.035 0.039

a1 0.000 0.000 0.080 0.000 0.000 0.003

b 0.150 0.200 0.250 0.006 0.008 0.010

b1 2.000 2.200 2.400 0.079 0.087 0.095

b2 0.150 0.200 0.250 0.006 0.008 0.010

c1 0.150 0.200 0.250 0.006 0.008 0.010

D2 3.850 3.950 4.050 0.152 0.156 0.160

E 4.400 4.500 4.600 0.173 0.177 0.181

E1 3.400 3.500 3.600 0.134 0.138 0.142

E2 2.000 2.100 2.200 0.079 0.083 0.087

e 0.400 TYP 0.016 TYP

K 0.300 TYP 0.012 TYP

L 0.300 0.400 0.500 0.012 0.016 0.020

L1 0.180 0.230 0.280 0.007 0.009 0.011

θ0.00 — — 0.00 — —

{L} TEXAS INSTRUMENTS *lﬂr *IH hi LUUUw 3— “mm“: L L7 44 A; v E?

0.225 ( x 2)

0.850 (x8)

0.300

0.200 0.200

0.390

0.350

0.225

2.200

0.115

0.738 (x 8)

(0.008) (0.008)

(0.029)

(0.015)

(0.012)

(0.014)

(0.009)

(0.087)

(0.004)

0.400

(0.016)

0.200

(0.008)

0.300

(0.012)

(0.033)

0.200

(0.008)

0.440 (0.017)

R0.100

0.250

(x18)

(0.010)

0.150

(0.006)

0.600 (x 2)

(0.024)

0.200

(x2)

2.250

0.225 ( x 2)

4.050

2.200

0.300

(0.008)

(0.087)

(0.012) (0.088)

(0.009)

(0.159)

0.150

(0.006)

0.400

(0.016)

R0.100

CSD97394Q4M

www.ti.com

SLPS542 –JANUARY 2015

11.2 Recommended PCB Land Pattern

11.3 Recommended Stencil Opening

NOTE: Dimensions are in mm (inches).

Stencil is 100 µm thick.

I TEXAS INSTRUMENTS Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

CSD97394Q4M ACTIVE VSON-CLIP DPC 8 2500 RoHS-Exempt

& Green NIPDAU Level-2-260C-1 YEAR -40 to 150 97394M

CSD97394Q4MT ACTIVE VSON-CLIP DPC 8 250 RoHS-Exempt

& Green NIPDAU Level-2-260C-1 YEAR -40 to 150 97394M

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CSD97394Q4M VSON-

CLIP DPC 8 2500 330.0 12.4 3.71 4.71 1.1 8.0 12.0 Q1

CSD97394Q4MT VSON-

CLIP DPC 8 250 180.0 12.4 3.71 4.71 1.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Feb-2018

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CSD97394Q4M VSON-CLIP DPC 8 2500 367.0 367.0 35.0

CSD97394Q4MT VSON-CLIP DPC 8 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Feb-2018

Pack Materials-Page 2

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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