设置
快速交货
免运费
国际贸易术语
支付类型
市场产品
With any FET the actual switching takes place at the threshold voltage. When turning off a device with a low threshold voltage there is now a smaller voltage across the sink impedance of the driver. So in order to keep the gate low during Miller transition, an ultra low sink impedance is required. Designing a driver with separate terminals for the source and sink paths into and out of the driver allows easy configuration to set the source resistance while still maintaining the ultra low sink resistance. The next slide will show the need for the source resistance. Another way to solve the low threshold challenge is the wafer level / chip-scale packages of the EPC eGaN FETs which have very little internal inductance. The footprint allows power and gate loops to be separated very close to the package where common inductance is minimized, and voltage drop associated with di/dt in this inductance is to be minimal.
