Furthermore, optimization graphs have also been included to provide a better understanding of how optimizing a design for efficiency or footprint can affect temperature rise, frequency, and discrete component sizes. The optimization factor on the x-axis correlates to the optimization dial. In the illustration, the dial is set at “3” so the optimization factor of 3 is highlighted. To optimize for efficiency, the dial can be set to 4 or 5 which yields a larger solution, as reflected on the footprint vs. efficiency chart mainly because the inductor size increases. The power dissipation chart shows that at higher efficiencies, the losses through the inductor are increased. This is because the increased number of windings result in a larger DCR which means an increase in conduction losses. However, M1 and M2, the high side and low side FETs respectively, are showing that at higher efficiencies the power dissipation is lower. This is expected because the FET is not switching as quickly, so switching losses are reduced. Finally, the IC temperature curve shows that at higher efficiencies, the frequency is lower and so is the overall IC temperature. This is expected because switching losses are reduced due to lower frequency. To optimize for footprint, the overall size needs to be reduced. Thus the inductor size needs to be smaller which results in an increased frequency. The tradeoff is that the increased frequency increases switching losses which lowers efficiency and increases junction temperature. These optimization graphs provide an easy and quick reference for making design tradeoffs to optimize a system appropriately.