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In summary, here is a review of a few design considerations when working with MSP430 JTAG. JTAG pins of the MSP430 are often multiplexed with other GPIO or peripheral functions. This should be considered up front in the design planning and system definition. It is a good practice to use these pins in application as a last resort when equivalent functions exist on other non-JTAG pins. In the case these pins must be used, consider the direction required for JTAG communication and connect accordingly to avoid any logic contention between the host programmer and the system circuitry. This is not a concern when using the SBW interface for MSP430 JTAG. Also keep in mind the capacitor on the RST pin to avoid overloading, especially during SBW activity.
It is a good practice to be conscious of routing placement of JTAG signals in any design. Not only can these signals generate noise during JTAG access that might interfere with the application, but it is also possible for the application environment to project noise onto the JTAG lines causing errant operation of the device. Most notably, one might see sporadic RST behavior triggered by noise coupling onto the RST pin if noise free PCB design is not considered for the RST line. This is generally only an issue if traces get long, if they are close to noisy circuitry or perhaps are susceptible to ESD strikes. When JTAG or any MSP430 pin is not used in a design, please consult the device-specific family user’s guide for recommendations & requirements for properly handling these connections. This is typically found in chapter 1 or 2 of the given users guide near the end of the chapter. And lastly, remember the tradeoffs for choosing four or two wire JTAG on the MSP430. The four wire approach requires more pins but is compatible with ALL MSP430 devices and is the fastest manner in which to program the memory. SBW will provide fewer physical connections but will be ~⅓ the interface speed vs four wire JTAG due to the multiplexing implemented to reduce the pin count.
It is a good practice to be conscious of routing placement of JTAG signals in any design. Not only can these signals generate noise during JTAG access that might interfere with the application, but it is also possible for the application environment to project noise onto the JTAG lines causing errant operation of the device. Most notably, one might see sporadic RST behavior triggered by noise coupling onto the RST pin if noise free PCB design is not considered for the RST line. This is generally only an issue if traces get long, if they are close to noisy circuitry or perhaps are susceptible to ESD strikes. When JTAG or any MSP430 pin is not used in a design, please consult the device-specific family user’s guide for recommendations & requirements for properly handling these connections. This is typically found in chapter 1 or 2 of the given users guide near the end of the chapter. And lastly, remember the tradeoffs for choosing four or two wire JTAG on the MSP430. The four wire approach requires more pins but is compatible with ALL MSP430 devices and is the fastest manner in which to program the memory. SBW will provide fewer physical connections but will be ~⅓ the interface speed vs four wire JTAG due to the multiplexing implemented to reduce the pin count.
PTM Published on: 2011-12-05
