设置
快速交货
免运费
国际贸易术语
支付类型
市场产品
Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Slide 28
Slide 29
Slide 30
Slide 31
Slide 32
Slide 33
Slide 34
Slide 35
Slide 36
Slide 37
Slide 38
Slide 39
Slide 40
Slide 41
Product List
Looking at the block diagram for the L6506 you see two fixed frequency PWM circuits plus the logic to combine the PWM signal with the phase information from the step generator and then feed that to the two power bridges. The peak motor current is regulated by sensing the voltage across the resistor on the Vsense inputs and comparing it to the reference input. When the voltage at the Vsense input reaches the reference voltage, the comparator will reset flip-flop that will cause the PWM to turn the bridge off. The oscillator sets the flip-flop at a fixed frequency and the cycle repeats. Generally the L6506 is connected to the phase inputs of the power bridge so it typically implements phase chopping or slow decay mode chopping in the bridge.
PTM Published on: 2011-12-14
