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The SPI module adds an eight word transmit receive FIFO buffer. This allows the CPU to send and receive messages in packets, reducing the overhead on the CPU. Remembering that the SPI protocol always does a transmit and receive at the same time, the FIFO is structured sharing the transmit and receive data. As a word or byte is transmitted out, a receive word or byte replaces it in the FIFO. The dsPIC SPI modules support some of the framed SPI protocols which use a framing pulse to synchronize the data transfer. In dsPIC33, there are more options for specifying the timing and polarity of the framing pulse.
PTM Published on: 2011-11-07
