HCSL Buffers
Low skew, differential-to-HCSL fanout buffers from Renesas
Renesas’ 85102I is a low-skew, 1-to-2 differential/LVCMOS-to-HCSL fanout buffer. The 85102I has two selectable clock inputs. The differential input supports LVPECL, LVDS, HSTL, SSTL and HCSL input levels. The single-ended input supports LVCMOS/LVTTL signal levels. The device is supplied by 3.3 V. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
The 85104I is a low skew, 1-to-4 differential/LVCMOS-to-HCSL fanout buffer. The 85104I has two selectable clock inputs, the differential input supports LVPECL, LVDS, HSTL, SSTL and HCSL input levels. The single-ended input supports LVCMOS/LVTTL signal levels. The device is supplied by 3.3 V. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
The ICS85108I is a low skew, high performance 1-to-8 differential-to-0.7 V HCSL clock distribution chip and a member of the HiPerClockS™ family of high performance clock solutions from Renesas. The ICS85108I CLK, nCLK pair can accept most differential input levels and translates them to 3.3 V HCSL output levels. The ICS85108I provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals. Guaranteed output and part-to-part skew specifications make the ICS85108I ideal for those applications demanding well defined performance and repeatability.
HCSL Buffers
图片 | 制造商零件编号 | 描述 | 比率 - 输入:输出 | 差分 - 输入:输出 | 可供货数量 | ||
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85102AGILF | IC CLK BUFFER 1:2 500MHZ 16TSSOP | 1:2 | 是/是 | 0 - 立即发货 | 查看详情 | ||
85104AGILF | IC CLK BUFFER 2:4 500MHZ 20TSSOP | 2:4 | 是/是 | 493 - 立即发货 | 查看详情 | ||
85108AGILF | IC CLK BUFFER 1:8 500MHZ 24TSSOP | 1:8 | 是/是 | 0 - 立即发货 | 查看详情 |