STMicroelectronics 的 M41T0 规格书

June 2011 Doc ID 9105 Rev 7 1/23
1
M41T0
Serial real-time clock
Features
■Counters for seconds, minutes, hours, day,
date, month, years, and century
■32 KHz crystal oscillator integrating load
capacitance (12.5 pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■Oscillator stop detection monitors clock
operation
■Serial interface supports I2C bus
(400 kHz protocol)
■Low standby current 0.9 µA (typ at 3 V)
■2.0 to 5.5 V clock operating voltage
■Special software programmable output
■Operating temperature of –40 to 85 °C
8
1
SO8
www.st.com
Contents M41T0
2/23 Doc ID 9105 Rev 7
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M41T0 List of tables
Doc ID 9105 Rev 7 3/23
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . 18
Table 10. Carrier tape dimensions for SO8 package (150 mils body width). . . . . . . . . . . . . . . . . . . . 19
Table 11. Reel dimensions for 12 mm carrier tape - SO8 package (150 mils body width) . . . . . . . . . 20
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
List of figures M41T0
4/23 Doc ID 9105 Rev 7
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. AC testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical drawing. . . 18
Figure 13. Carrier tape for SO8 package (150 mils body width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OSCl M41T0 Figure 2. SOIC connections I'II'IHI'I LILILJLI 1. NF pm must be men lo v55. Table 1. Signal names OSCI Oscillator inpul OCSO Oscillator oulpul OUT Oulpul driver (open drain) SDA Sevial dale address inpul / ou SCL Sevial clock NFW No funclion Vcc Supply voltage V35 Gvound 1. NF pm must be men lo v55. Doc ID 9105 Flev 7
M41T0 Description
Doc ID 9105 Rev 7 5/23
1 Description
The M41T0 real-time clock is a low power serial real-time clock with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight registers are used for the clock/calendar
function and are configured in binary coded decimal (BCD) format. Addresses and data are
transferred serially via a two-line bidirectional bus. The built-in address register is
incremented automatically after each WRITE or READ data byte.
The M41T0 is supplied in 8-lead plastic small outline package.
Figure 1. Logic diagram
Figure 2. SOIC connections
1. NF pin must be tied to VSS.
Table 1. Signal names
OSCI Oscillator input
OCSO Oscillator output
OUT Output driver (open drain)
SDA Serial data address input / output
SCL Serial clock
NF(1)
1. NF pin must be tied to VSS.
No function
VCC Supply voltage
VSS Ground
AI07028
OSCI
VCC
M41T0
VSS
SCL
OSCO
SDA
OUT
1
SDAVSS
SCL
OUTOSCO
OSCI VCC
NF(1)
AI07029
M41T0
2
3
4
8
7
6
5
6/23 SER‘AL BUS \NTERFACE ‘ T f? Doc ‘0 9105 Rev 7
Description M41T0
6/23 Doc ID 9105 Rev 7
Figure 3. Block diagram
AI07030
SECONDS
OSCILLATOR
32.768 kHz
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
MINUTES
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
OSCI
OSCO
OUT
VCC
VSS
SCL
SDA
1 Hz
M41T0 Operation
Doc ID 9105 Rev 7 7/23
2 Operation
The M41T0 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1. Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Years register
8. Control register
2.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●Data transfer may be initiated only when the bus is not busy.
●During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Operation M41T0
8/23 Doc ID 9105 Rev 7
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level
put on the bus by the receiver, whereas the master generates an extra acknowledge related
clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 4. Serial bus data transfer sequence
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
_\_/\_/\_..J\_/\_
M41T0 Operation
Doc ID 9105 Rev 7 9/23
Figure 5. Acknowledgement sequence
Figure 6. Bus timing requirements sequence
1. P = STOP and S = START
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCLK FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB
AI00589
SDA
P
tSU:S
T
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STAtBUF
SP
Operation M41T0
10/23 Doc ID 9105 Rev 7
2.2 READ mode
In this mode, the master reads the M41T0 slave after setting the slave address (see
Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only incremented on reception of an acknowledge bit.
The M41T0 slave transmitter will now place the data byte at address An+1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is
incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T0
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 9 on page 12).
Table 2. AC characteristics
Symbol Parameter(1)
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted).
Min Typ Max Unit
fSCL SCL clock frequency 0 400 kHz
tLOW Clock low period 1.3 µs
tHIGH Clock high period 600 ns
tRSDA and SCL rise time 300 ns
tFSDA and SCL fall time 300 ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated) 600 ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition) 600 ns
tSU:DAT Data setup time 100 ns
tHD:DAT(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
edge of SCL.
Data hold time 0 µs
tSU:STO STOP condition setup time 600 ns
tBUF
Time the bus must be free before a new transmission
can start 1.3 µs
|| | |\ D mode sequence \ \ I IIIIIII IIIIIII IIIHII 5 HI] lllllll || lllllll [[111]] 1 ix x1 1 BUSACTIVITV ‘ ‘ u o ‘ ‘ I 1“ (I I ESLAVEE 3 3 ‘ADDRESS‘ ‘ ‘ n. O F u; Hlllll ——— DATAmx F \llllll x o < o="" z="" ‘7]="" docl="">
M41T0 Operation
Doc ID 9105 Rev 7 11/23
2.3 WRITE mode
In this mode the master transmitter transmits to the M41T0 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T0
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
Figure 7).
Figure 7. Slave address location
Figure 8. READ mode sequence
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
Him HIIIHII IIHIH \IIIHI ll llHlll IHIIH HlHll BUSACTWITV: 1 if; 1 1“ Amuass gure 10. WRITE mode sequence \ ||||||| ||||||| ||||H\ ""IIIIII |||| ||||||| ||||||| ||||H\ ___|||||| BUSACTMTV‘ § 1 I A‘DUSB‘ 12/23 Doc ‘0 9105 Rev 7
Operation M41T0
12/23 Doc ID 9105 Rev 7
Figure 9. Alternate READ mode sequence
Figure 10. WRITE mode sequence
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
M41T0 Clock operation
Doc ID 9105 Rev 7 13/23
3 Clock operation
The M41T0 is driven by a quartz controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC. The M41T0 is tested to meet ± 35 ppm
with nominal crystal. The eight-byte clock register (see Table 3 on page 14) is used to both
set the clock and to read the date and time from the clock, in a binary coded decimal format.
Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of
clock register 2 (hours register) contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from
'1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB
will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5
and 6 contain the date (day of month), month and years. The final register is the control
register. Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. If the device is expected to spend a significant amount of time on the shelf,
the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator
restarts within four seconds (typically one second).
The seven clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 7) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the seven clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
delayed by 250 ms to allow the READ to be completed before the update occurs. This will
prevent a transition of data during the READ.
Note: This 250 ms delay affects only the clock register update and does not alter the actual clock
time.
3.1 Output driver pin
The OUT pin is an output driver that reflects the contents of D7 of the control register. In
other words, when D7 of location 7 is a '0' then the OUT pin will be driven low.
Note: The OUT pin is open drain which requires an external pull-up resistor.
3.2 Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops. The following
conditions can cause the OF bit to be set:
●The first time power is applied (defaults to a '1' on power-up).
●The voltage present on VCC is insufficient to support oscillation.
●The ST bit is set to '1.'
●External interference or removal of the crystal.
This bit will remain set to '1' until written to logic '0.'
The oscillator must start and have run for at least 4 seconds before attempting to reset the
OF bit to '0.' This function operates both under normal power and in battery backup.
Clock operation M41T0
14/23 Doc ID 9105 Rev 7
3.3 Initial power-on defaults
Upon initial application of power to the device, the OUT bit and OF bit will be set to a '1,'
while the ST bit will be set to '0.' All other register bits will initially power-on in a random
state.
Table 3. Register map(1)
1. Keys:
ST = STOP bit
OUT = Output level
X = Don’t care
0 = Must be set to '0.'
CEB = Century enable bit
CB = Century bit
OF = Oscillator fail bit
Address
Data Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
0 ST 10 seconds Seconds Seconds 00-59
1 OF 10 minutes Minutes Minutes 00-59
2CEB
(2)
2. When CEB is set to '1', CB toggles from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon
the initial value set). When CEB is set to '0', CB does not toggle.
CB 10 hours Hours Century/hours 0-1/00-23
3 X X X X X Day Day 01-07
4 X X 10 date Date Date 01-31
5 X X X 10 M. Month Month 01-12
6 10 years Years Year 00-99
7 OUT 0 X X X X X X Control
M41T0 Maximum ratings
Doc ID 9105 Rev 7 15/23
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
TSTG Storage temperature (VCC off, oscillator off) –55 to 125 °C
VCC Supply voltage –0.3 to 7 V
TSLD(1)
1. Reflow at peak temperature of 260 °C (total thermal budget not to exceed 245 °C for greater than 30 seconds).
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltages –0.3 to VCC + 0.3 V
IOOutput current 20 mA
PDPower dissipation 1 W
DC and AC parameters M41T0
16/23 Doc ID 9105 Rev 7
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Figure 11. AC testing input/output waveform
Table 5. Operating and AC measurement conditions(1)
1. Output Hi-Z is defined as the point where data is no longer driven.
Parameter M41T0 Unit
Supply voltage (VCC) 2.0 to 5.5 V
Ambient operating temperature (TA) –40 to 85 °C
Load capacitance (CL) 100 pF
Input rise and fall times ≤ 5ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input and output timing ref. voltages 0.3VCC to 0.7VCC V
Table 6. Capacitance
Symbol Parameter(1)(2)
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested
2. At 25 °C, f = 1 MHz.
Min Max Unit
CIN Input capacitance (SCL) 7 pF
COUT(3)
3. Outputs deselected.
Output capacitance (SDA, OUT) 10 pF
tLP Low-pass filter input time constant (SDA and SCL) 50 ns
AI02568
0.8VCC
0.2VCC
0.7VCC
0.3VCC
M41T0 DC and AC parameters
Doc ID 9105 Rev 7 17/23
Table 7. DC characteristics
Sym Parameter Test condition(1) Min Typ Max Unit
ILI Input leakage current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output leakage current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1 Supply current Frequency (SCL) = 400 kHz 3.0 V 35 55 µA
5.5 V 130 200 µA
ICC2(2) Supply current (standby) All inputs = VCC – 0.2 V
Frequency (SCL) = 0 Hz
3.0 V 0.9 1.2 µA
5.5 V 31 µA
VIL Input low voltage –0.3 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC + 0.3 V
VOL
Output low voltage IOL = 3 mA 0.4 V
Output low voltage
(open drain) IOL = 10 mA 0.4 V
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted).
2. At 25 °C.
Table 8. Crystal electrical characteristics
Symbol Parameter(1)(2) Min Typ Max Unit
fOResonant frequency 32.768 kHz
RSSeries resistance 60(3) kΩ
CLLoad capacitance 12.5 pF
1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can
be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T0. Circuit board layout considerations for the 32.768 kHz crystal of minimum
trace lengths and isolation from RF generating signals should be taken into account.
3. RS = 40 kΩ when VCC ≤ 2.5 V.
Package mechanical information M41T0
18/23 Doc ID 9105 Rev 7
6 Package mechanical information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 12. SO8 – 8-lead plastic small outline, 150 mils body width, package
mechanical drawing
1. Drawing is not to scale.
Table 9. SO8 – 8-lead plastic small outline, 150 mils body width, package
mechanical data
Symbol
millimeters inches
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k 0°8° 0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45°
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
W '47 7 i flf ‘f $$¢¢$¢¢¢ gfi 2g
M41T0 Package mechanical information
Doc ID 9105 Rev 7 19/23
Figure 13. Carrier tape for SO8 package (150 mils body width)
T
K0
P1
A0
B0
P2
P0
CENTER LINES
OF CAVITY
W
E
F
D
TOP COVER
TAPE
USER DIRECTION OF FEED
AM03073v1
Table 10. Carrier tape dimensions for SO8 package (150 mils body width)
Package W D E P0P2FA
0B0K0P1TUnit
Bulk
Qty
SO8 12.00
±0.30
1.50
+0.10/
–0.00
1.75
±0.10
4.00
±0.10
2.00
±0.10
5.50
±0.05
6.50
±0.10
5.30
±0.10
2.20
±0.10
8.00
±0.10
0.30
±0.05 mm 2500
Package mechanical information M41T0
20/23 Doc ID 9105 Rev 7
Figure 14. Reel schematic
Note: The dimensions given in Ta bl e 1 1 incorporate tolerances that cover all variations on critical
parameters.
A
D
B
Full radius
Tape slot
In core for
Tape start
2.5mm min.width
G measured
At hub
C
N
40mm min.
Access hole
At slot location
T
AM04928v1
Table 11. Reel dimensions for 12 mm carrier tape - SO8 package (150 mils body width)
A
(max)
B
(min) CD
(min)
N
(min) GT
(max)
330 mm
(13-inch) 1.5 mm 13 mm
± 0.2 mm 20.2 mm 60 mm 12.4 mm
+ 2/–0 mm 18.4 mm
M41T0 Part numbering
Doc ID 9105 Rev 7 21/23
7 Part numbering
For a list of additional options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest to you.
Table 12. Ordering information scheme
Example: M41T 0 M 6 F
Device type
M41T
Supply voltage and write protect voltage
0: VCC = 2.0 to 5.5 V
Package
M = SO8 (150 mils width)
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package , tape & reel
Revision history M41T0
22/23 Doc ID 9105 Rev 7
8 Revision history
Table 13. Document revision history
Date Revision Changes
Feb-2003 1.0 First issue
18-Feb-2003 1.1 Add Pb-free information (Ta b l e 4 , Ta b l e 1 2 ); update package
information (Features, Figure 12; Ta b l e 1 2 )
01-Apr-2003 1.2 Fix package outline and data (Features, Figure 12, Ta bl e 1 2 )
10-Apr-2003 1.3 Revert to previous package (Features, Figure 12, Ta bl e 1 2 )
30-Oct-2003 1.4 Remove footnote (Ta b l e 4 )
30-Jun-2004 2.0 Shipping method options updated and Note 1 removed from Table 12:
Ordering information scheme. Datasheet put in new template.
23-Jul-2004 3.0 Content corrected from M41T80 to M41T0.
22-Aug-2006 4
Changed document to new template; amalgamated diagrams in
Features; updated Package mechanical data in Section 6: Package
mechanical information; Ta b l e 1 2 ecopack compliant; small text
changes for entire document
04-Apr-2007 5 Updated packaging information that only SO8 package available (cover
page and Table 12: Ordering information scheme).
13-May-2008 6 Updated Figure 12, Ta b le 4 .
09-Jun-2011 7 Updated Features, ECOPACK® text in Section 6: Package mechanical
information; added Figure 13, 14, Tab le 10 , 11.
M41T0
Doc ID 9105 23/23
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