Microchip Technology 的 SY58606U 规格书
‘ MICRQICHIP SY58606 U
D
SY58606U
Features
Applications
Markets
General Description
Package Type
SY58606U
13141516
12
11
10
9
1
2
3
4
8765
IN
VT
VREF-AC
/IN
Q0
/Q0
Q1
/Q1
VCC
GND
GND
VCC
VCC
GND
GND
VCC
4.25 Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and
Fail Safe Input
SY58606U
Functional Block Diagram
Q1
/Q1
IN
/IN
VT
50Ω
50Ω
Q0
/Q0
VREF-AC
SY58606U
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Operating Ratings ††
†Notice:
††Notice:
Note 1:
2:
VREFVAC
TIN
DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics:
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1:
2:
3:
CML OUTPUTS DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics:
Parameter Symbol Min. Typ. Max. Units Condition
Note 1:
SY58606U
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
Parameter Symbol Min. Typ. Max. Units Condition
Note 1:
2:
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Package Thermal Resistances (Note 1)
Note 1:
SY58606U
700 250
3650 3
>600 )225
5550 a
8500 o
5450 rrrrrrrr gm
5400 I;
935° / 3175
§ 30° v‘N = mom 3 v“ = soomv
lzsu l
“ %‘
a o o a a
E 3 s g g g a 3 s g g g
INPUT RISE/FALL TIME (ps) INPUT RISE/FALL TIME (p5)
400
3
>350
S
w
o
z
9300
Z
3250
§ / vm=2oomv
‘L I I
200C: n D o o o o
a 2 s 2 g g
INPUT RISE/FALL TIME (p5)
300
3
>275
S
w
c
z
9250
F
< (j="" gzzs="" g="" vm="4aomv" ‘="" i="" i="" 200="" '="3" 8="" 8="" 8="" 8="" 8="" n="" v="" m="" m="" 9="" 9="" input="" rise/fall="" time="" (ps)="">
SY58606U
2.0 TYPICAL PERFORMANCE CURVES
Note:
FIGURE 2-1: Propagation Delay vs. Input
Rise/Fall Time.
FIGURE 2-2: Propagation Delay vs. Input
Rise/Fall Time.
FIGURE 2-3: Propagation Delay vs. Input
Rise/Fall Time.
FIGURE 2-4: Propagation Delay vs. Input
Rise/Fall Time.
SY58606U
TIME (200ps/div.)
FIGURE 2-5: 1.25 Gbps Data.
TIME (100ps/div.)
FIGURE 2-6: 2.5 Gbps Data.
TIME (80ps/div.)
FIGURE 2-7: 3.2 Gbps Data.
TIME (60ps/div.)
FIGURE 2-8: 4.25 Gbps Data.
TIME (200ps/div.)
OUTPUT SWING
(100mV/div.)
FIGURE 2-9: 625 MHz Clock.
TIME (200ps/div.)
OUTPUT SWING
(100mV/div.)
FIGURE 2-10: 1.25 Ghz Clock.
TIME (70ps/div.)
OUTPUT SWING
(100mV/div.)
SY58606U
FIGURE 2-11: 2 GHz Clock.
TIME (50ps/div.)
OUTPUT SWING
(100mV/div.)
FIGURE 2-12: 3 GHz Clock.
TYPICAL ADDITIVE PHASE JITrER [622MHz CARRIER]
12km? lDMHz RANGE
100 5...,
doom
711mm
120 30
130m
33!: “m6: #1:; “2:22
71mm
no on
7130130
mu
m
Dom
orrszr rnEnuzucv (Mm)
SY58606U
3.0 ADDITIVE PHASE NOISE PLOT
FIGURE 3-1: Additive Noise Plot.
SY58606U
4.0 PIN DESCRIPTIONS
TABLE 4-1: PIN FUNCTION TABLE
Pin Number Symbol Description
VIN
(IN
IN
‘vn
/O
V
' ouT
SY58606U
5.0 FUNCTIONAL DESCRIPTION
5.1 Fail-Safe Input (FSI)
5.2 Input Clock Failure Case
Timing Diagrams
FIGURE 5-1: Propagation Delay.
IN
Q
/Q
FSI activated once input amplitude
goes significantly below 100mV (typically 30mV)
Decaying input signal
FIGURE 5-2: Fail Safe Feature.
SY58606U
Input and Output Stage
ȍ
/IN
VCC
ȍ
IN
VT
GND
FIGURE 5-3: Simplified Differential Input
Buffer.
ȍ ȍ
/Q
Q
V
CC
GND
FIGURE 5-4: Simplified CML Output
Buffer.
Single-Ended and Differential Swings
VIN, VOUT
400mV
(typical)
FIGURE 5-5: Single-Ended Swing.
VDIFF_IN, VDIFF_OUT
800mV (typical)
FIGURE 5-6: Differential Swing.
SY58606U
6.0 INPUT INTERFACE APPLICATIONS
IN
/IN
VT
SY58606U
VCC
NC
GND
VREF-ACNC
CML
FIGURE 6-1: CML Interface
(DC-Coupled) May connect VT to VCC.
SY58606U
VCC
GND
CML
IN
/IN
VT
VREF-AC
0.1μF
VCC
FIGURE 6-2: CML Interface
(AC-Coupled).
GND
IN
/IN
VREF-AC
0.1μF
SY58606U
VCC
VCC
RP
Note:
For 3.3V, RP ȍ
For 2.5V, RP ȍ
LVPECL
NC
VT
FIGURE 6-3: LVPECL Interface
(DC-Coupled).
GND
IN
/IN
VREF-AC
0.1μF
SY58606U
VCC
VCC
LVPECL
VT
GND
RPRP
Note:
For 3.3V, RP ȍ
For 2.5V, RP ȍ
FIGURE 6-4: LVPECL Interface
(AC-Coupled).
IN
/IN
VT
SY58606U
VCC
NC
GND
VREF-ACNC
LVDS
FIGURE 6-5: LVDS Interface
(DC-Coupled).
% ii:
SY58606U
7.0 CML OUTPUT TERMINATION
ȍȍ
VCC
GND
ȍ
/Q
Q
Z0 ȍ
Z0 ȍ
FIGURE 7-1: CML DC-Coupled
Termination.
ȍȍ
VCC
GND
ȍ
/Q
Q
Z0 ȍ
Z0 ȍ ȍ
VCC
FIGURE 7-2: CML DC-Coupled
Termination.
ȍȍ
VCC
GND
ȍ
/Q
Q
Z0 ȍ
Z0 ȍ ȍ
VBIAS
FIGURE 7-3: CML AC-Coupled
Termination.
NNN
SY58606U
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
Example
WNNN
XXXX
16-Lead QFN*
–
7288
606U
–
Legend:
*
Note
3
e
3
e
TITLE
16 LEAD QFN 3x3mm PACKAGE OUTLINE s. RECOMMENDED LAND PATTERN
DRAWING « | QFN33’16LD’PLRL UNIT | MM
PIN M mwmcmuu
FIN 1 DDT ‘73OODD100504— SSUUtUTUS CHAMFER HIGH X 45‘
12v MARKING W -—-Exp mm: L
x j U U H nAuuuqusn
1
5 j T '
2 UTSDDU ESE: C 2
1 5500:0350
Ennnotfl asn f Exp MP
:1 C
i I
j
na3unzunsn] H U U m
LISUDU
REF
M w
m I, a g ,, a, ,
7 a saw nsn
T i
W
M
NEITET
1 MAX PACKAGE WARRAGE [S 005 MM
2 MAX ALLDwAELE BURN [S 0076 MM [N ALL IIIREETIDNS
3‘ PIN «I [S EIN TD? WILL BE LASER MARKED
4 RED CIRCLE [N LAND PATTERN INDICATE THERMAL VIA SIZE SHEIULD BE 0307035 MM
IN DIAMETER AND SHEIULD BE EDNNECTED TD 6ND FDR MAM THERMAL PEREDRMANCE
5T GREEN RECTANGLES (SHADED AREA) moficote SDLDER STENCIL EIPENING EIN [XPEISED
PAD AREA SIZE SHEIULD BE asexueu MM IN SEZE. LL20 MM SPACINGT
Note:
SY58606U
POD-Land Panem drawmg # QFN33—l GLD-PL— 1
RECDMMEJDED LAND PATTERN
EEEE
EQEE
BEES
BEBE
mamw
3‘U4t0‘02
0801002 070:002
0481002 040:002 T [1101002
’ r77
,iCI l_lg g g a g
3 CI 4,} Eli, 33 g 221 7’ 22 5‘,
‘3 CI |:|$ E m g E] Q] m a
m — m m m q m
a; CI ’—‘ N [Z] E2] ‘3‘
o a
g j E D [ E a E 3 2
D 1‘60t0‘02 1‘4010‘02
2 2241002 2241002
SEUtU‘UE 304:0 DE
Note:
SY58606U
SY58606U
NOTES:
SY58606U
APPENDIX A: REVISION HISTORY
Revision A (May 2019)
SY58606U
NOTES:
41x
41x
—I>< 4x="" mm="" 16-lead="" mm="" 16-lead="">
SY58606U
PRODUCT IDENTIFICATION SYSTEM
Examples:
PART NO. X
X
Package Temperature
Range
Device
Device:
Supply Voltage:
Package:
Temperature
Range:
Special
Processing:
Note 1:
X
Supply
Voltage
XX
Tape
and Reel
SY58606U
NOTES:
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
= ISO/TS 16949 =
.
Trademarks
Note the following details of the code protection feature on Microchip devices:
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
6‘
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