Analog Devices Inc. 的 LTC1666-68 规格书

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LTC1666/LTC1667/LTC1668
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATION
U
12-Bit, 14-Bit, 16-Bit,
50Msps DACs
■
50Msps Update Rate
■
Pin Compatible 12-Bit, 14-Bit and 16-Bit Devices
■
High Spectral Purity: 87dB SFDR at 1MHz f
OUT
■
5pV-s Glitch Impulse
■
Differential Current Outputs
■
20ns Settling Time
■
Low Power: 180mW from ±5V Supplies
■
TTL/CMOS (3.3V or 5V) Inputs
■
Small Package: 28-Pin SSOP
The LTC
®
1666/LTC1667/LTC1668 are 12-/14-/16-bit,
50Msps differential current output DACs implemented on
a high performance BiCMOS process with laser trimmed,
thin-film resistors. The combination of a novel current-
steering architecture and a high performance process
produces DACs with exceptional AC and DC performance.
The LTC1668 is the first 16-bit DAC in the marketplace to
exhibit an SFDR (spurious free dynamic range) of 87dB
for an output signal frequency of 1MHz.
Operating from ±5V supplies, the
LTC1666/LTC1667/
LTC1668
can be configured to provide full-scale output
currents up to 10mA. The differential current outputs of
the DACs allow single-ended or true differential operation.
The –1V to 1V output compliance of the
LTC1666/
LTC1667/LTC1668
allows the outputs to be connected
directly to external resistors to produce a differential out-
put voltage without degrading the converter’s linearity. Al-
ternatively, the outputs can be connected to the summing
junction of a high speed operational amplifier, or to a
transformer.
The LTC1666/LTC1667/LTC1668 are pin compatible and
are available in a 28-pin SSOP and are fully specified over
the industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Cellular Base Stations
■
Multicarrier Base Stations
■
Wireless Communication
■
Direct Digital Synthesis (DDS)
■
xDSL Modems
■
Arbitrary Waveform Generation
■
Automated Test Equipment
■
Instrumentation
LTC1668, 16-Bit, 50Msps DAC
–
+
V
SS
V
DD
–5V
CLOCK
INPUT 16-BIT DATA
INPUT
LADCOM
AGND DGND CLK DB15 DB0
1666/7/8 TA01
I
OUT A
0.1µF
LTC1668
5V
52.3Ω
I
REFIN
REFOUT
COMP1
COMP2
C2
0.1µF
0.1µF
C1
0.1µF
R
SET
2k
I
OUT B
52.3ΩV
OUT
1V
P-P
DIFFERENTIAL
+
–
0.1µF
16-BIT
HIGH SPEED
DAC
2.5V
REFERENCE
LTC1668 SFDR vs fOUT and fCLOCK
fOUT (MHz)
0.1
SFDR (dB)
100
90
80
70
60
50 1.0 10 100
1666/7/8 G05
5MSPS
25MSPS
50MSPS
DIGITAL AMPLITUDE = 0dBFS
33333333333333 33333333333333 EEEEEEEEEEEEEE CCCCCCCCEEEEEE 33333333333333 EEEEEEEEEEEEEE L7 LJUW
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LTC1666/LTC1667/LTC1668
LTC1666CG
LTC1666IG
TJMAX = 110°C, θJA = 100°C/W
ORDER PART
NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DB14
DB15 (MSB)
CLK
V
DD
DGND
V
SS
COMP2
COMP1
I
OUT A
I
OUT B
LADCOM
AGND
I
REFIN
REFOUT
Supply Voltage (V
DD
)................................................ 6V
Negative Supply Voltage (V
SS
) ............................... –6V
Total Supply Voltage (V
DD
to V
SS
) .......................... 12V
Digital Input Voltage ....................–0.3V to (V
DD
+ 0.3V)
Analog Output Voltage
(I
OUT A
and I
OUT B
) ........ (V
SS
– 0.3V) to (V
DD
+ 0.3V)
PACKAGE/ORDER I FOR ATIO
UU
W
ABSOLUTE AXI U RATI GS
WWWU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
NC
NC
NC
NC
DB10
DB11 (MSB)
CLK
V
DD
DGND
V
SS
COMP2
COMP1
I
OUT A
I
OUT B
LADCOM
AGND
I
REFIN
REFOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
NC
NC
DB12
DB13 (MSB)
CLK
V
DD
DGND
V
SS
COMP2
COMP1
I
OUT A
I
OUT B
LADCOM
AGND
I
REFIN
REFOUT
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1666C/LTC1667C/LTC1668C ........... 0°C to 70°C
LTC1666I/LTC1667I/LTC1668I.......... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
(Note 1)
TJMAX = 110°C, θJA = 100°C/W TJMAX = 110°C, θJA = 100°C/W
LTC1668CG
LTC1668IG
ORDER PART
NUMBER
LTC1667CG
LTC1667IG
ORDER PART
NUMBER
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LTC1666/LTC1667/LTC1668
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.
ELECTRICAL CHARACTERISTICS
LTC1666 LTC1667 LTC1668
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Accuracy (Measured at I
OUT A
, Driving a Virtual Ground)
Resolution ●12 14 16 Bits
Monotonicity 12 14 14 Bits
INL Integral Nonlinearity (Note 2) ±1±2±8 LSB
DNL Differential Nonlinearity (Note 2) ±1±1±1±4 LSB
Offset Error 0.1 ±0.2 0.1 ±0.2 0.1 ±0.2 % FSR
Offset Error Drift 5 5 5 ppm/°C
GE Gain Error Internal Reference, R
IREFIN
= 2k 2 2 2 % FSR
External Reference, 1 1 1 % FSR
V
REF
= 2.5V, R
IREFIN
= 2k
Gain Error Drift Internal Reference 50 50 50 ppm/°C
External Reference 30 30 30 ppm/°C
PSRR Power Supply V
DD
= 5V ±5% ±0.1 ±0.1 ±0.1 % FSR/V
Rejection Ratio V
SS
= –5V ±5% ±0.2 ±0.2 ±0.2 % FSR/V
AC Linearity
SFDR Spurious Free Dynamic f
CLK
= 25Msps, f
OUT
= 1MHz
Range to Nyquist 0dB FS Output 76 78 78 87 dB
–6dB FS Output 87 dB
–12dB FS Output 83 dB
f
CLK
= 50Msps, f
OUT
= 1MHz 85 dB
f
CLK
= 50Msps, f
OUT
= 2.5MHz 81 dB
f
CLK
= 50Msps, f
OUT
= 5MHz 79 dB
f
CLK
= 50Msps, f
OUT
= 20MHz 70 dB
Spurious Free Dynamic f
CLK
= 25Msps, 85 86 86 96 dB
Range Within a Window f
OUT
= 1MHz, 2MHz Span
f
CLK
= 50Msps, 88 dB
f
OUT
= 5MHz, 4MHz Span
THD Total Harmonic Distortion f
CLK
= 25Msps, f
OUT
= 1MHz –75 –77 –84 –77 dB
f
CLK
= 50Msps, f
OUT
= 5MHz –78 dB
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LTC1666/LTC1667/LTC1668
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.
ELECTRICAL CHARACTERISTICS
LTC1666/LTC1667/LTC1668
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Output
I
OUTFS
Full-Scale Output Current ●110mA
Output Compliance Range I
FS
= 10mA ●–1 1 V
Output Resistance; R
IOUT A
, R
IOUT B
I
OUT A, B
to LADCOM ●0.7 1.1 1.5 kΩ
Output Capacitance 5pF
Reference Output
Reference Voltage REFOUT Tied to I
REFIN
Through 2kΩ2.475 2.5 2.525 V
Reference Output Drift 25 ppm/°C
Reference Output Load Regulation I
LOAD
= 0mA to 5mA 6 mV/mA
Reference Input
Reference Small-Signal Bandwidth I
FS
= 10mA, C
COMP1
= 0.1µF 20 kHz
Power Supply
V
DD
Positive Supply Voltage ●4.75 5 5.25 V
V
SS
Negative Supply Voltage ●–4.75 –5 –5.25 V
I
DD
Positive Supply Current I
FS
= 10mA, f
CLK
= 25Msps, f
OUT
= 1MHz ●35mA
I
SS
Negative Supply Current I
FS
= 10mA, f
CLK
= 25Msps, f
OUT
= 1MHz ●33 40 mA
P
DIS
Power Dissipation I
FS
= 10mA, f
CLK
= 25Msps, f
OUT
= 1MHz 180 mW
I
FS
= 1mA, f
CLK
= 25Msps, f
OUT
= 1MHz 85 mW
Dynamic Performance (Differential Transformer Coupled Output, 50Ω Double Terminated, Unless Otherwise Noted)
f
CLOCK
Maximum Update Rate ●50 75 Msps
t
S
Output Settling Time To 0.1% FSR 20 ns
t
PD
Output Propagation Delay 8ns
Glitch Impulse Single Ended 15 pV-s
Differential 5 pV-s
t
r
Output Rise Time 4ns
t
f
Output Fall Time 4ns
i
NO
Output Noise 50 pA/√Hz
Digital Inputs
V
IH
Digital High Input Voltage ●2.4 V
V
IL
Digital Low Input Voltage ●0.8 V
I
IN
Digital Input Current ●±10 µA
C
IN
Digital Input Capacitance 5pF
t
DS
Input Setup Time ●8ns
t
DH
Input Hold Time ●4ns
t
CLKH
Clock High Time ●5ns
t
CLKL
Clock Low Time ●8ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired. Note 2: For the LTC1666, ±1LSB = ±0.024% of full scale;
for the LTC1667, ±1LSB = ±0.006% of full scale = ±61ppm of full scale;
for the LTC1668, ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.
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LTC1666/LTC1667/LTC1668
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SIGNAL AMPLITUDE (dBFS)
1666/7/8 G01
05
10 15 20 25
SFDR = 87dB
f
CLOCK
= 50MSPS
f
OUT
= 1.002MHz
AMPL = 0dBFS
= –8.25dBm
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Single Tone SFDR at 50MSPS 2-Tone SFDR
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SIGNAL AMPLITUDE (dBFS)
1666/7/8 G02
4.5 5.0 5.5
SFDR > 86dB
f
CLOCK
= 50MSPS
f
OUT1
= 4.9MHz
f
OUT2
= 5.09MHz
AMPL = 0dBFS
4-Tone SFDR, fCLOCK = 50MSPS
4-Tone SFDR, fCLOCK = 5MSPS SFDR vs fOUT and Digital Amplitude
(dBFS) at fCLOCK = 5MSPS
SFDR vs fOUT and fCLOCK
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SIGNAL AMPLITUDE (dBFS)
1666/7/8 G03
1 4.6 8.2 11.8 15.4 19
SFDR > 74dB
f
CLOCK
= 50MSPS
f
OUT1
= 5.02MHz
f
OUT2
= 6.51MHz
f
OUT3
= 11.02MHz
f
OUT4
= 12.51MHz
AMPL = 0dBFS
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SIGNAL AMPLITUDE (dBFS)
1666/7/8 G04
0.1 0.46 0.82 1.18 1.54 1.9
SFDR > 82dB
f
CLOCK
= 5MSPS
f
OUT1
= 0.5MHz
f
OUT2
= 0.65MHz
f
OUT3
= 1.10MHz
f
OUT4
= 1.25MHz
AMPL = 0dBFS
f
OUT
(MHz)
0.1
SFDR (dB)
100
90
80
70
60
50 1.0 10 100
1666/7/8 G05
5MSPS
25MSPS
50MSPS
DIGITAL AMPLITUDE = 0dBFS
f
OUT
(MHz)
100
95
90
85
80
75
70
65
60
55
50
SFDR (dB)
1666/7/8 G06
0 0.4 0.8 1.2 1.6 2.0
–12dBFS
–6dBFS
0dBFS
(LTC1668)
f
OUT
(MHz)
0
SFDR (dB)
4810
95
90
85
80
75
70
65
60
55
50
1666/7/8 G07
26
–12dBFS
–6dBFS
0dBFS
f
OUT
(MHz)
0
SFDR (dB)
10 20
90
85
80
75
70
65
60
55
50
1666/7/8 G08
515
–12dBFS –6dBFS
0dBFS
f
OUT
(MHz)
0
SFDR (dB)
10
95
90
85
80
75
70
65
60
55
50
1666/7/8 G09
2.5 5 7.5
DIGITAL AMPLITUDE = 0dBFS
I
OUTFS
= 2.5mA
I
OUTFS
= 5mA
I
OUTFS
= 10mA
SFDR vs fOUT and Digital Amplitude
(dBFS) at fCLOCK = 25MSPS SFDR vs fOUT and Digital Amplitude
(dBFS) at fCLOCK = 50MSPS SFDR vs fOUT and I
OUTFS
at
fCLOCK = 25MSPS
AT SMSPS SMHzAT 25MSPS L7 LJDW
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LTC1666/LTC1667/LTC1668
Integral Nonlinearity
DIGITAL INPUT CODE
–5
INTEGRAL NONLINEARITY (LSB)
–4
–2
–1
0
5
2
16384 32768
1666/7/8 G18
–3
3
4
1
49152 65535
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SFDR vs Digital Amplitude (dBFS)
and fCLOCK at fOUT = fCLOCK/11 Single-Ended Outputs
Full-Scale Transition
Differential Output
Full-Scale Transition Single-Ended Output
Full-Scale Transition Differential Output
Full-Scale Transition
Differential Midscale
Glitch Impulse
Single-Ended Midscale
Glitch Impulse
DIGITAL AMPLITUDE (dBFS)
100
95
90
85
80
75
70
65
60
55
50
SFDR (dB)
1666/7/8 G10
–20 –15 –10 –5 0
455kHz AT 5MSPS
4.55MHz AT 50MSPS
2.277MHz AT 25MSPS
DIGITAL AMPLITUDE (dBFS)
100
95
90
85
80
75
70
65
60
55
50
SFDR (dB)
1666/7/8 G11
–20 –15 –10 –5 0
1MHz AT 5MSPS
10MHz AT 50MSPS
5MHz AT 25MSPS
100mV
/DIV
CLK IN
5V/DIV
1666/7/8 G12
5ns/DIV
V(I
OUTB
)
V(I
OUTA
)
FFFF
0000
CLOCK INPUT
SFDR vs Digital Amplitude (dBFS)
and fCLOCK at fOUT = fCLOCK/5
100mV
/DIV
CLK IN
5V/DIV
1666/7/8 G13
5ns/DIV
V(I
OUTA
) – V(I
OUTB
)
FFFF
0000
100mV
/DIV
CLK IN
5V/DIV
1666/7/8 G14
5ns/DIV
V(I
OUTA
)
V(I
OUTB
)
FFFF 0000
CLOCK INPUT
100mV
/DIV
CLK IN
5V/DIV
1666/7/8 G15
5ns/DIV
V(I
OUTA
) – V(I
OUTB
)
FFFF 0000
1mV/DIV
CLK IN
5V/DIV
1666/7/8 G16
5ns/DIV
V(I
OUTA
), V(I
OUTB
)
7FFF 8000
1mV/DIV
CLK IN
5V/DIV
1666/7/8 G17
5ns/DIV
V(I
OUTA
) – V(I
OUTB
)
7FFF 8000
(LTC1668)
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LTC1666/LTC1667/LTC1668
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Differential Nonlinearity
DIGITAL INPUT CODE
0
DIFFERENTIAL NONLINEARITY (LSB)
0
1.0
65535
1666/7/8 G19
–1.0
–2.0 16384 32768 49152
2.0
–0.5
0.5
–1.5
1.5
(LTC1668)
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LTC1666
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
I
REFIN
(Pin 16): Reference Input Current. Nominal value is
1.25mA for I
FS
= 10mA. I
FS
= I
REFIN
• 8.
AGND (Pin 17): Analog Ground.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
I
OUT B
(Pin 19): Complementary DAC Output Current. Full-
scale output current occurs when all data bits are 0s.
I
OUT A
(Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V
SS
with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to V
SS
with 0.1µF.
V
SS
(Pin 23): Negative Supply Voltage. Nominal value is
–5V.
DGND (Pin 24): Digital Ground.
V
DD
(Pin 25): Positive Supply Voltage. Nominal value is 5V.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
DB11 to DB0 (Pins 27, 28, 1 to 10 ): Digital Input Data Bits.
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LTC1666/LTC1667/LTC1668
LTC1667
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
I
REFIN
(Pin 16): Reference Input Current. Nominal value is
1.25mA for I
FS
= 10mA. I
FS
= I
REFIN
• 8.
AGND (Pin 17): Analog Ground.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
I
OUT B
(Pin 19): Complementary DAC Output Current. Full-
scale output current occurs when all data bits are 0s.
I
OUT A
(Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V
SS
with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to V
SS
with 0.1µF.
V
SS
(Pin 23): Negative Supply Voltage. Nominal value is
–5V.
DGND (Pin 24): Digital Ground.
V
DD
(Pin 25): Positive Supply Voltage. Nominal value is 5V.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
DB13 to DB0 (Pins 27, 28, 1 to 12 ): Digital Input Data Bits.
LTC1668
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
I
REFIN
(Pin 16): Reference Input Current. Nominal value is
1.25mA for I
FS
= 10mA. I
FS
= I
REFIN
• 8.
AGND (Pin 17): Analog Ground.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
I
OUT B
(Pin 19): Complementary DAC Output Current. Full-
scale output current occurs when all data bits are 0s.
I
OUT A
(Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V
SS
with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to V
SS
with 0.1µF.
V
SS
(Pin 23): Negative Supply Voltage. Nominal value is
–5V.
DGND (Pin 24): Digital Ground.
V
DD
(Pin 25): Positive Supply Voltage. Nominal value is 5V.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
DB15 to DB0 (Pins 27, 28, 1 to 14 ): Digital Input Data Bits.
UU
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LTC1666/LTC1667/LTC1668
BLOCK DIAGRA
W
–
+
I
FS
/8
I
REFIN
I
INT
R
SET
2k
0.1µF
0.1µF
0.1µF
–5V
0.1µF
REFOUT
V
DD
V
REF
15
16
COMP121
COMP2
V
SS
22
23
2.5V
REFERENCE ATTENUATOR
LADDER
LSB SWITCHES
INPUT LATCHES
CLOCK
INPUT 12-BIT
DATA INPUT
SEGMENTED SWITCHES
FOR DB15–DB12
CURRENT SOURCE ARRAY
AGND
17
DGND
24
CLK DB0DB11 • • •
• • •
• • • • • •
26 27 10
1666 BD
18
LADCOM
20
I
OUT A
19
I
OUT B
52.3Ω52.3Ω
V
OUT
1V
P-P
DIFFERENTIAL
+
–
0.1µF
25
5V
–
+
I
FS
/8
I
REFIN
I
INT
R
SET
2k
0.1µF
0.1µF
0.1µF
–5V
0.1µF
REFOUT
V
REF
15
16
COMP121
COMP2
V
SS
22
23
2.5V
REFERENCE ATTENUATOR
LADDER
LSB SWITCHES
INPUT LATCHES
CLOCK
INPUT 14-BIT
DATA INPUT
SEGMENTED SWITCHES
FOR DB15–DB12
CURRENT SOURCE ARRAY
AGND
17
DGND
24
CLK DB0DB13 • • •
• • •
• • • • • •
26 27 12
1667 BD
18
LADCOM
20
I
OUT A
19
I
OUT B
52.3Ω52.3Ω
V
OUT
1V
P-P
DIFFERENTIAL
+
–
0.1µF
25
5V
V
DD
LTC1666
LTC1667
égé T g + |||||| T L7 LJUW
10
LTC1666/LTC1667/LTC1668
BLOCK DIAGRA
W
TI I G DIAGRA
UWW
1666/7/8 TD
tDS tDH
CLK
N – 1
N – 1 N
N N + 1
DATA
INPUT
IOUT A/IOUT B
tCLKL tCLKH
tPD
0.1%
tST
–
+
I
FS
/8
I
REFIN
I
INT
R
SET
2k
0.1µF
0.1µF
0.1µF
–5V
0.1µF
REFOUT
V
REF
15
16
COMP121
COMP2
V
SS
22
23
2.5V
REFERENCE ATTENUATOR
LADDER
LSB SWITCHES
INPUT LATCHES
CLOCK
INPUT 16-BIT
DATA INPUT
SEGMENTED SWITCHES
FOR DB15–DB12
CURRENT SOURCE ARRAY
AGND
17
DGND
24
CLK DB0DB15 • • •
• • •
• • • • • •
26 27 14
1668 BD
18
LADCOM
20
I
OUT A
19
I
OUT B
52.3Ω52.3Ω
V
OUT
1V
P-P
DIFFERENTIAL
+
–
0.1µF
25
5V
V
DD
LTC1668
9% u”— .||— L7LJIJWW
11
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Theory of Operation
The
LTC1666/LTC1667/LTC1668
are high speed current
steering 12-/14-/16-bit DACs made on an advanced
BiCMOS process. Precision thin film resistors and well
matched bipolar transistors result in excellent DC linearity
and stability. A low glitch current switching design gives
excellent AC performance at sample rates up to 50Msps.
The devices are complete with a 2.5V internal bandgap
reference and edge triggered latches, and set a new
standard for DAC applications requiring very high dy-
namic range at output frequencies up to several mega-
hertz.
Referring to the Block Diagrams, the DACs contain an
array of current sources that are steered to I
OUTA
or I
OUTB
with NMOS differential current switches. The four most
significant bits are made up of 15 current segments of
equal weight. The remaining lower bits are binary weighted,
using a combination of current scaling and a differential
resistive attenuator ladder. All bits and segments are
precisely matched, both in current weight for DC linearity,
and in switch timing for low glitch impulse and low
spurious tone AC performance.
Setting the Full-Scale Current, I
OUTFS
The full-scale DAC output current, I
OUTFS
, is nominally
10mA, and can be adjusted down to 1mA. Placing a
resistor, R
SET
, between the REFOUT pin, and the I
REFIN
pin
sets I
OUTFS
as follows.
The internal reference control loop amplifier maintains a
virtual ground at I
REFIN
by servoing the internal current
source, I
INT
, to sink the exact current flowing into I
REFIN
.
I
INT
is a scaled replica of the DAC current sources and
I
OUTFS
= 8 • (I
INT
), therefore:
I
OUTFS
= 8 • (I
REFIN
) = 8 • (V
REF
/R
SET
) (1)
For example, if R
SET
= 2k and is tied to V
REF
= REFOUT =
2.5V, I
REFIN
= 2.5/2k = 1.25mA and I
OUTFS
= 8 • (1.25mA)
= 10mA.
The reference control loop requires a capacitor on the
COMP1 pin for compensation. For optimal AC perfor-
mance, C
COMP1
should be connected to V
SS
and be placed
very close to the package (less than 0.1").
For fixed reference voltage applications, CCOMP1 should
be 0.1µF or more. The reference control loop small-signal
bandwidth is approximately 1/(2π) • CCOMP1 • 80 or 20kHz
for CCOMP1 = 0.1µF.
Reference Operation
The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to I
REFIN
, corresponding to a
1.25mA load (I
OUTFS
= 10mA). REFOUT has nominal
output impedance of 6Ω, or 0.24% per mA, so it must be
buffered to drive any additional external load. A 0.1µF
capacitor is required on the REFOUT pin for compensa-
tion. Note that this capacitor is required for stability, even
if the internal reference is not being used.
External Reference Operation
Figure 1, shows how to use an external reference to control
the LTC1666/LTC1667/LTC1668 full-scale current.
Figure 1. Using the LTC1666/LTC1667/LTC1668
with an External Reference
REFOUT
+
–
I
REFIN
2.5V
REFERENCE
R
SET
0.1µF
5V
1666/7/8 F02
EXTERNAL
REFERENCE
LTC1666/
LTC1667/
LTC1668
L7 LJUW
12
LTC1666/LTC1667/LTC1668
Adjusting the Full-Scale Output
In Figure 2, a serial interfaced DAC is used to set I
OUTFS
.
The LTC1661 is a dual 10-bit V
OUT
DAC with a buffered
voltage output that swings from 0V to V
REF
.
DAC Transfer Function
The LTC1666/LTC1667/LTC1668 use straight binary digital
coding. The complementary current outputs, I
OUT A
and I
OUT
B
, sink current from 0 to I
OUTFS
. For I
OUTFS
= 10mA (nomi-
nal), I
OUT A
swings from 0mA when all bits are low (e.g.,
Code␣ = 0) to 10mA when all bits are high (e.g., Code = 65535
for LTC1668) (decimal representation). I
OUT B
is comple-
mentary to I
OUT A
. I
OUT A
and I
OUT B
are given by the following
formulas:
LTC1666:
I
OUT A
= I
OUTFS
• (DAC Code/4096) (2)
I
OUT B
= I
OUTFS
• (4095 – DAC Code)/4096 (3)
LTC1667:
I
OUT A
= I
OUTFS
• (DAC Code/16384) (4)
I
OUT B
= I
OUTFS
• (16383 – DAC Code)/16384 (5)
LTC1668:
I
OUT A
= I
OUTFS
• (DAC Code/65536) (6)
I
OUT B
= I
OUTFS
• (65535 – DAC Code)/65536 (7)
In typical applications, the LTC1666/LTC1667/LTC1668
differential output currents either drive a resistive load
directly or drive an equivalent resistive load through a
transformer, or as the feedback resistor of an I-to-V
converter. The voltage outputs generated by the I
OUT A
and
I
OUT B
output currents are then:
Figure 2. Adjusting the Full-Scale Current of
the LTC1666/LTC1667/LTC1668 with a DAC
APPLICATIO S I FOR ATIO
WUUU
V
OUT A
= I
OUT A
• R
LOAD
(8)
V
OUT B
= I
OUT B
• R
LOAD
(9)
The differential voltage is:
V
DIFF
= V
OUT A
– V
OUT B
(10)
= (I
OUT A
– I
OUT B
) • (R
LOAD
)
Substituting the values found earlier for I
OUT A
, I
OUT B
and
I
OUTFS
(LTC1668):
V
DIFF
= {2 • DAC Code – 65535)/65536} • 8 •
(R
LOAD
/R
SET
) • (V
REF
) (11)
From these equations some of the advantages of differen-
tial mode operation can be seen. First, any common mode
noise or error on I
OUT A
and I
OUT B
is cancelled. Second, the
signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times I
OUT A
and
I
OUT B
, such as reference or I
OUTFS
noise, cancel near
midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.
Note that the term (R
LOAD
/R
SET
) appears in both the
differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
R
LOAD
to R
SET
, and the Gain Error tempco is affected by the
temperature tracking of R
LOAD
with R
SET
. Note also that
the absolute tempco of R
LOAD
is very critical for DC
nonlinearity. As the DAC output changes from 0mA to
10mA the R
LOAD
resistor will heat up slightly, and even a
very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.
Analog Outputs
The LTC1666/LTC1667/LTC1668 have two complemen-
tary current outputs, I
OUT A
and I
OUT B
(see DAC Transfer
Function). The output impedance of I
OUT A
and I
OUT B
(R
IOUT A
and R
IOUT B
) is typically 1.1kΩ to LADCOM. (See
Figure 3.)
+
–
I
REFIN
2.5V
REFERENCE
R
SET
1.9k
REF 0.1µF
1/2 LTC1661
5V
1666/7/8 F03
LTC1666/
LTC1667/
LTC1668
«Hr I’M/v1 fl III-NW— .||—w ."J Kw L7 LINEN?
13
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
LADCOM
The LADCOM pin is the common connection for the
internal DAC attenuator ladder. It usually is tied to analog
ground, but more generally it should connect to the same
potential as the load resistors on I
OUT A
and I
OUT B
. The
LADCOM pin carries a constant current to V
SS
of approxi-
mately 0.32 • (I
OUTFS
), plus any current that flows from
I
OUT A
and I
OUT B
through the R
IOUT A
and R
IOUT B
resistors.
Output Compliance
The specified output compliance voltage range is ±1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I
OUT A
into the virtual ground of an
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below –1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than ±0.5V
P-P
on I
OUT A
and
I
OUT B
due to nonlinear capacitance and other large-signal
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
Figure 4. AC Characterization Setup (LTC1668)
–
+
16-BIT
HIGH SPEED
DAC
HP1663EA
LOGIC ANALYZER WITH
PATTERN GENERATOR
V
SS
V
DD
–5V
LADCOM
AGND DGND CLK DB15 DB0
16
DIGITAL
DATA
CLK
IN
1666/7/8 F05
I
OUT A
0.1µF
LTC1668
5V
I
REFIN
REFOUT
COMP1
COMP2
C2
0.1µF
0.1µF
OUT 1 OUT 2
C1
0.1µF
R
SET
2k
I
OUT B
HP8110A DUAL
PULSE GENERATOR
LOW JITTER
CLOCK SOURCE
CLK
IN
50Ω
0.1µF
50Ω
TO HP3589A
SPECTRUM
ANALYZER
50Ω INPUT
110Ω
MINI-CIRCUITS
T1–1T
2.5V
REFERENCE
Figure 3. Equivalent Analog Output Circuit
20
19
23
18
R
IOUT B
1.1k
5pF 5pF
–5V
1666/7/8 F04
R
IOUT A
1.1k
LADCOM
I
OUT A
I
OUT B
V
SS
52.3Ω
52.3Ω
LTC1666/LTC1667/LTC1668
ban: % % ; L7 LJUW
14
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Operating with Reduced Output Currents
The LTC1666/LTC1667/LTC1668 are specified to operate
with full-scale output current, I
OUTFS
, from the nominal
10mA down to 1mA. This can be useful to reduce power
dissipation or to adjust full-scale value. However, the DC
and AC accuracy is specified only at I
OUTFS
= 10mA, and
DC and AC accuracy will fall off significantly at lower I
OUTFS
values. At I
OUTFS
= 1mA, the LTC1668 INL and DNL
typically degrade to the 14-bit to 13-bit level, compared to
16-bit to 15-bit typical accuracy at 10mA I
OUTFS
. Increas-
ing I
OUTFS
from 1mA, the accuracy improves rapidly,
roughly in proportion to 1/I
OUTFS
. Note that the AC perfor-
mance (SFDR) is affected much more by reduced I
OUTFS
than it is by reduced digital amplitude (see Typical Perfor-
mance Characteristics). Therefore it is usually better to
make large gain adjustments digitally, keeping I
OUTFS
equal to 10mA.
Output Configurations
Based on the specific application requirements, the
LTC1666/LTC1667/LTC1668 allow a choice of the best of
several output configurations. Voltage outputs can be
generated by external load resistors, transformer coupling
or with an op amp I-to-V converter. Single-ended DAC
output configurations use only one of the outputs, prefer-
ably I
OUT A
, to produce a single-ended voltage output.
Differential mode configurations use the difference be-
tween I
OUT A
and I
OUT B
to generate an output voltage,
V
DIFF
, as shown in equation 11. Differential mode gives
much better accuracy in most AC applications. Because
the DAC chip is the point of interface between the digital
input signals and the analog output, some small amount
of noise coupling to I
OUT A
and I
OUT B
is unavoidable. Most
of that digital noise is common mode and is canceled by
the differential mode circuit. Other significant digital noise
components can be modeled as V
REF
or I
OUTFS
noise. In
single-ended mode, I
OUTFS
noise is gone at zero scale and
is fully present at full scale. In differential mode, I
OUTFS
noise is cancelled at midscale input, corresponding to zero
analog output. Many AC signals, including broadband and
multitone communications signals with high peak to aver-
age ratios, stay mostly near midscale.
Differential Transformer-Coupled Outputs
Differential transformer-coupled output configurations
usually give the best AC performance. An example is
shown in Figure 5. The advantages of transformer cou-
pling include excellent rejection of common mode distor-
tion and noise over a broad frequency range and conve-
nient differential-to-single-ended conversion with isola-
tion or level shifting. Also, as much as twice the power can
be delivered to the load, and impedance matching can be
accomplished by selecting the appropriate transformer
turns ratio. The center tap on the primary side of the
transformer is tied to ground to provide the DC current
path for I
OUT A
and I
OUT B
. For low distortion, the DC
average of the I
OUT A
and I
OUT B
currents must be exactly
equal to avoid biasing the core. This is especially impor-
tant for compact RF transformers with small cores. The
circuit in Figure 5 uses a Mini-Circuits T1-1T RF trans-
former with a 1:1 turns ratio. The load
resistance on
IOUT A and IOUT B is equivalent to a single differential
resistor of 50Ω, and the 1:1 turns ratio means the output
impedance from the transformer is 50Ω. Note that the
load resistors are optional, and they dissipate half of the
output power. However, in lab environments or when
driving long transmission lines it is very desirable to have
a 50Ω output impedance. This could also be done with a
50Ω resistor at the transformer secondary, but putting
the load resistors on IOUT A and IOUT B is preferred since
it reduces the current through the transformer. At signal
frequencies lower than about 1MHz, the transformer core
size required to maintain low distortion gets larger, and at
some lower frequencies this becomes impractical.
Figure 5. Differential Transformer-Coupled Outputs
IOUT B
IOUT A
50Ω
50Ω
110Ω
MINI-CIRCUITS
T1-1T
RLOAD
1666/7/8 F06
LTC1666/
LTC1667/
LTC1668
L7LJIJWW
15
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Resistor Loaded Outputs
A differential resistor loaded output configuration is shown
in Figure 6. It is simple and economical, but it can drive
only differential loads with impedance levels and ampli-
tudes appropriate for the DAC outputs.
The recommended single-ended resistor loaded configu-
ration is essentially the same circuit as the differential
resistor loaded, case—simply use the I
OUT A
output,
referred to ground. Rather than tying the unused I
OUT B
output to ground, it is preferred to load it with the equiva-
lent R
LOAD
of I
OUT A
. Then I
OUT B
will still swing with a
waveform complementary to I
OUT A
.
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings
±1V around ground.
Figure 8 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1’s slewing capabilities.
Digital Interface
The LTC1666/LTC1667/LTC1668 have parallel inputs that
are latched on the rising edge of the clock input. They
accept CMOS levels from either 5V or 3.3V logic and can
accept clock rates of up to 50MHz.
Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, V
IH
=
2.4V min, V
IL
= 0.8V max, work with 3.3V or 5V CMOS
levels over temperature. The guaranteed setup time, t
DS
,
is 8ns minimum and the hold time, t
DH
, is 4ns minimum.
The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1666/LTC1667/LTC1668 to be clocked at up to 50Msps
minimum.
For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is impor-
tant. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually in-
Op Amp I to V Converter Outputs
Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 7.
This circuit complements the capabilities of the trans-
former-coupled application at lower frequencies, since
available op amps can deliver good AC distortion perfor-
mance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
Figure 6. Differential Resistor-Loaded Output
IOUT B
IOUT A
52.3Ω52.3Ω
1666/7/8 F07
LTC1666/
LTC1667/
LTC1668
Figure 8. Single-Ended Op Amp I to V Converter
200Ω
1666/7/8 F09
I
OUT A
I
OUT B
LADCOM
R
FB
200Ω
V
OUT
0V TO 2V
I
OUTFS
10mA
C
OUT
–
+
U1
LT
®
1812
LTC1666/
LTC1667/
LTC1668
I
OUT B
I
OUT A
52.3Ω500Ω52.3Ω
1666/7/8 F08
–
+
200Ω
500Ω
200Ω
60pF LT1809 ±1V
10dBm
V
OUT
LTC1666/
LTC1667/
LTC1668
Figure 7. Differential to Single-Ended Op Amp I-V Converter
Amy-HF «4 I— L7 LJUW
16
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
cluding the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.
Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will
cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled imped-
ance and should be well terminated near the LTC1666/
LTC1667/LTC1668.
Printed Circuit Board Layout Considerations—
Grounding, Bypassing and Output Signal Routing
The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute
necessity. Figures 11 to 15 are the printed circuit board
layers for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1µF or larger with low ESR.
Bypass capacitors are required on V
SS
, V
DD
and REFOUT,
and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1µF bypass capacitor. It should be bypassed
to V
SS
along with COMP1. The AGND and DGND pins
should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The I
OUT A
and
I
OUT B
traces should be close together, short, and well
matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.
Suggested Evaluation Circuit
Figure 10 is the schematic and Figures 11 to 15 are the
circuit board layouts for a suggested evaluation circuit,
DC245A. The circuit can be programmed with component
selection and jumpers for a variety of differentially coupled
transformer output and differential and single-ended re-
sistor loaded output configurations.
REFOUT LADCOM
I
OUT A
V
OUT
I
OUT B
I
REFIN
CLK
LTC1668
U2
Q-CHANNEL
REFOUT LADCOM
I
OUT A
I
OUT B
I
REFIN
CLK
LTC1668
U1
I-CHANNEL
52.3Ω
52.3Ω52.3Ω
52.3Ω
LOW-PASS
FILTER
LOW-PASS
FILTER
CLOCK
INPUT
REF
1/2 LTC1661
U3
SERIAL
INPUT
2k
2.1k
21k
0.1µF
0.1µF
90°
∑
LOCAL
OSCILLATOR QAM
OUTPUT
QUADRATURE
MODULATOR
±5%
RELATIVE GAIN
ADJUSTMENT RANGE
1666/7/8 F10
Figure 9. QAM Modulation Using LTC1668 with
Digitally Controlled I vs Q Channel Gain Adjustment
EEK" +- T T LL;— 444 4+ L7LJIJWW
17
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Figure 10. Suggested Evaluation Circuit
J4
V
OUT
J5
I
OUT B
J6
EXTCLK
JP9
123
1516
R3
1.91k
0.1%
R2
200Ω
JP1
C17
0.1µF
LTC1668
20
19
21
22
23
18
C7
0.1µF
5V –5V
TP5
TESTPOINT WHT
C3
0.1µFC18
0.1µF
25
17
24
C10
0.1µFC11
0.1µF
R9
50Ω
0.1%
R12
49.9Ω
1%
JP6
R10
50Ω
0.1%
C12
22pF C12
22pF
C9
0.1µF
C8
0.1µF
C8
0.1µF
JP5
TP3
TESTPOINT
WHT
JP7
JP3
R5 R6
R7
110Ω
JP4
JP2
5V
REFOUTREFIN
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
26
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
CLK
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
I
OUT A
I
OUT B
COMP1
COMP2
V
SS
LADCOM
V
DD
AGND
DGND
R4
J2
I
OUT A
C4
R8
3
2
1
4
T1
MINI-
CIRCUITS
T1–1T
6
C5
JP8
TP4
TESTPOINT
WHT
2
4
6
1
3
5
RN5
+5VD
22Ω
+5VD
J7
J10
TP6
TESTPOINT RED
4
2
5V
6
LT1460DCS8-2.5
AMP
102159-9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RN6
22Ω
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
TP2
TESTPOINT WHT
2.5V
REF
TP10
TESTPOINT BLK
TP1
V
IN
V
OUT
GND
C2
0.1µF
C1
0.1µF
J1
EXTREF
R1
10Ω
+
C19
0.1µF
C14
10µF
25V
–5V
AGND DGND
J9
TP8
TESTPOINT RED
GROUND PLANE
TIE POINT
+
C20
0.1µF
C16
10µF
25V
1666/7/8 F11
C22
0.1µF
+5VA
J8
J11
TP7
TESTPOINT RED
TP9
TESTPOINT BLK
+
C23
0.1µF
C15
10µF
25V
C21
0.1µF
OPTIONAL
SIP
PULL-UP/
PULL-DOWN
RESISTORS
(NOT
INSTALLED)
OPTIONAL
SIP
PULL-UP/
PULL-DOWN
RESISTORS
(NOT
INSTALLED)
+5VD
R16
0Ω
R15
0Ω
R14
0Ω
R13
0Ω
+5vD n (aoum) +AUX noun m 0 Cu m C I m m m m mu m :3 a“ aux m m +5VA AGND 75M 0 O 0 WC 1WC 1w, 7 m m 59‘ ‘u U 7 mm mtg mm H m w. Om calm?" w “ “ , NH, 7 Hafinuafi «2“ WW ($51;ng we m QAEDELYH u “ m “1 Somme, m m ”Duuucm , g m HE‘S mmmn «5‘ \ U Ugo: 0" “‘ "Inum EL; Q B u - a g; M g -: 5.92"" Own) 7 ‘ u - m a a \ \a U ~ - m, 7 :2: an g g E] EX|R¢I [j [j 3, 5 BNDAUX m Dema mm ZASAAA L7 LJUW
18
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Figure 11. Suggested Evaluation Circuit Board—Silkscreen
L7LJIJWW
19
LTC1666/LTC1667/LTC1668
Figure 12. Suggested Evaluation Circuit Board—Component Side
APPLICATIO S I FOR ATIO
WUUU
a o H E 9 9 9 9 0 00000 000000000 CGCOOOOOOL 0000000 00000000 uggvuuuuo L7 LJUW
20
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Figure 13. Suggested Evaluation Circuit Board—GND Plane
UUUOOCQQC‘ CWOVOOCO a 9 J o o o a a 0 0000000 L7LJIJWW
21
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WUUU
Figure 14. Suggested Evaluation Circuit Board—Power Plane
II a. .- L7 LJUW
22
LTC1666/LTC1667/LTC1668
Figure 15. Suggested Evaluation Circuit Board—Solder Side
APPLICATIO S I FOR ATIO
WUUU
‘0074033‘ HHHHHHHHHHHHHH’ ‘ 7557790 0 \ HHHHHHHHHHHHHHAAA, w ”3499 i—‘ ; W+ n57 2‘ 257 as L7LJIJWW
23
LTC1666/LTC1667/LTC1668
U
PACKAGE DESCRIPTIO
G28 SSOP 0501
.13 – .22
(.005 – .009)
0° – 8°
.55 – .95
(.022 – .037)
5.20 – 5.38**
(.205 – .212)
7.65 – 7.90
(.301 – .311)
12345678 9 10 11 12 1413
10.07 – 10.33*
(.397 – .407)
2526 22 21 20 19 18 17 16 1523242728
1.73 – 1.99
(.068 – .078)
.05 – .21
(.002 – .008)
.65
(.0256)
BSC .25 – .38
(.010 – .015)
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
L7 LJUW
24
LTC1666/LTC1667/LTC1668
LINEAR TECHNOLOGY CORPORATION 2000
166678f LT/TP 0701 2K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
RELATED PARTS
TYPICAL APPLICATIO
U
Figure 16. Arbitrary Waveform Generator Has ±10V Output Swing, 50Msps DAC Update Rate
REFOUT LADCOM
IOUT A
IOUT B
IREFIN LTC1668
52.3Ω52.3Ω
RSET
2k –
+
VSS AGND DGND CLK DB15-DB0
COMP1
COMP2
0.1µF
0.1µF
0.1µF
–5V
5V
CLOCK
INPUT 18-BIT
DATA
INPUT
VDD
100pF LT1227
1k
VOUT
±10V
1666/7/8 F17
1k
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC1406 8-Bit, 20Msps ADC Undersampling Capability Up to 70MHz Input
LTC1411 14-Bit, 2.5Msps ADC
LTC1420 12-Bit, 10Msps ADC 72dB SINAD at 5MHz f
IN
LTC1604/LTC1608 16-Bit, 333ksps/500ksps ADCs 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
DACs
LTC1591/LTC1597 Parallel 14/16-Bit Current Output DACs On-Chip 4-Quadrant Resistors
LTC1595/LTC1596 Serial 16-Bit Current Output DACs Low Glitch, ±1LSB Maximum INL, DNL
LTC1650 Serial 16-Bit Voltage Output DAC Low Power, Deglitched, 4-Quadrant Multiplying V
OUT
DAC,
±4.5V Output Swing, 4µs Settling Time
LTC1655(L) Single 16-Bit V
OUT
DAC with Serial Interface in SO-8 5V (3V) Single Supply, Rail-to-Rail Output Swing
LTC1657(L) 16-Bit Parallel Voltage Output DAC 5V (3V) Low Power, 16-Bit Monotonic Over Temp., Multiplying Capability
AMPLIFIERs
LT1809/LT1810 Single/Dual 180MHz, 350V/µs Op Amp Rail-to-Rail Input and Output, Low Distortion
LT1812/LT1813 Single/Dual 100MHz, 750V/µs Op Amp 3.6mA Supply Current, 8nV/√Hz Input Noise Voltage