Texas Instruments 的 SN65EPT23 规格书

I TEXAS INSTRUMENTS C‘ EVE; \_H_l\_l\_l
18
27
36
45
D0
Q0
Q1
VCC
D0
D1
GND
D1
LVPECL LVTTL
+
+
+
+
+
SN65EPT23
www.ti.com
SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
Check for Samples: SN65EPT23
1FEATURES PINOUT ASSIGNMENT
•Dual 3.3 V Differential LVPECL/LVDS to
LVTTL/LVCMOS Buffer Translator
•24 mA LVTTL Ouputs
•Operating Range
–VCC = 3.0 V to 3.6 V
–GND = 0 V
•Support for Clock Frequencies >300 MHz
•2.0 ns Typical Propagation Delay
•Built-in Temperature Compensation
•Drop in Compatible to MC100EPT23
APPLICATIONS
•Data and Clock Transmission Over Backplane Table 1. Pin Description
•Signaling Level Conversion for Clock or Data PIN FUNCTION
Q0, Q1LVTTL/LVCMOS Outputs
DESCRIPTION
D0, D 0, D1, D 1Differential LVPECL/LVDS/CML Inputs
The SN65EPT23 is a low power dual LVPECL/LVDS VCC Positive Supply
to LVTTL/LVCMOS translator device. The device
includes circuitry to maintain inputs at Vcc/2 when left GND Ground
open. The SN65EPT23 is housed in an industry
standard SOIC-8 package and is also available in
TSSOP-8 option.
spacer
ORDERING INFORMATION(1)
PART NUMBER PART MARKING PACKAGE LEAD FINISH
SN65EPT23D/DR EPT23 SOIC NiPdAu
SN65EPT23DGK/DGKR SSTI MSOP NiPdAu
(1) Leaded device option not initially available; contact TI sales representative for further information.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. ©2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS
SN65EPT23
SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
PARAMETER CONDITION VALUE UNIT
Absolute supply voltage, VCC GND = 0V 3.8 V
Absolute input voltage, VIGND = 0 and Vi ≤VCC 0 to 3.8 V
Continuous 50
Output current mA
Surge 100
Operating temperature range –40 to 85 °C
Storage temperature range –65 to 150 °C
POWER DISSIPATION RATINGS
POWER RATING THERMAL RESISTANCE, DERATING FACTOR POWER RATING
CIRCUIT BOARD JUNCTION TO AMBIENT
PACKAGE TA<25°C TA>25°C TA= 85°C
MODEL NO AIRFLOW
(mW) (mW/°C) (mW)
SOIC Low-K 719 139 7 288
High-K 840 119 8 336
MSOP Low-K 469 213 5 188
High-K 527 189 5 211
THERMAL CHARACTERISTICS
PARAMETER PACKAGE VALUE UNIT
qJB Junction-to Board Thermal Resistance SOIC 79 °C/W
MSOP 120
qJC Junction-to Case Thermal Resistance SOIC 98 °C/W
MSOP 74
KEY ATTRIBUTES
CHARACTERISTICS VALUE
Moisture sensitivity level Level 1
Flammability rating (Oxygen Index: 28 to 34) UL 94 V-0 at 0.125 in
ESD-HBM 2 kV
ESD-machine model 200 V
ESD-charge device model 2 kV
Internal pull down resistor 50 kΩ
Internal pull up resistor 50 kΩ
Meets or exceeds JEDEC Spec EIA/JESD78 latchup test
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SN65EPT23
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SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
LVTTL OUTPUT DC CHARACTERISTICS(1) (VCC = 3.3 V; GND = 0 V, TA = -40C to 85C)(2)
–40°C 25°C 85°C
PARAMETER CONDITION UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
IOS Output short circuit current –180 –140 –50 -180 –144 –50 –180 –148 –50 mA
VOH Output high voltage(3) IOH =–3.0 mA 2.4 2.4 2.4 V
VOL Output low voltage IOL = 24 mA 0.5 0.5 0.5 V
(1) Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
(2) All values vary 1:1 with Vcc; Vcc can vary ±0.3V
(3) LVTTL output RL= 500 Ωto GND
LVPECL INPUT DC CHARACTERISTICS(1) (VCC = 3.3 V; GND = 0.0 V)(2)
–40°C 25°C 85°C
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
ICCH Power supply current (Outputs set to high) 15 25 15 25 15 25 mA
ICCL Power supply current (Outputs set to low) 15 25 15 25 15 25 mA
VIH Input high voltage 2075 2420 2075 2420 2075 2420 mV
VIL Input low voltage 1355 1675 1355 1675 1355 1675 mV
VIHCM Input high voltage common mode range (Differential) (3) 1.2 3.3 1.2 3.3 1.2 3.3 V
R
IIH Input high current 150 150 150 mA
IIL Input low current D mA
–150 –150 –150 0.5
D
(1) Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
(2) Input and output parameters vary 1:1 with VCC. VCC can vary ±0.3 V.
(3) VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. VIHCMR is referenced to most positive side of differential signal
AC CHARACTERISTICS(1) (VCC = 3.0 V to 3.6 V; GND = 0.0 V)(2) (3)
–40°C 25°C 85°C
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
fMAX Max switching frequency(4) 300 300 300 MHz
(Figure 1–Figure 3)
tPLH / Propagation delay low to high; output at 1.5V 1.1 1.3 1.9 1.1 1.3 1.9 1.1 1.3 1.9 ns
tPHL
TSK++ Output to output skew++ 110 110 110 ps
TSK- - Output to output skew- - 110 110 110 ps
TSKPP Part to part skew (5) 400 400 400 ps
tJITTER Random clock jitter (RMS)(6) 10 10 10 ps
VPP Input voltage swing (7) 150 1200 150 1200 150 1200 mV
tr/tfOutput rise/fall times (0.8 V –2.0 V) 250 560 800 250 580 800 250 600 800 ps
(1) Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
(2) Input parameters vary 1:1 with VCC. VCC can vary ±0.3V .
(3) TTL output RL= 500 Ωto GND and CL= 20 pF to GND see Figure 4.
(4) Fmax assures for functionality only; VOL and VOH levels are assured at DC only
(5) Skews are measured between outputs under identical conditions.
(6) Measured with VID = 1.5 VPP at VCM = 2.0 V and 1.2 V
(7) 200 mV input assured full logic swing at the output.
©2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65EPT23
l TEXAS INSTRUMENTS AWE ”7/
0
1
2
3
4
5
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
V @25°C
OH
V @85°C
OH
V @-40°C
OH
V @25°C
OL
V @85°C
OL
V @-40°C
OL
V =3°C
CC
Voltage-V
0
1
2
3
4
5
Voltage-V
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
V @25°C
OH
V @85°C
OH
V @-40°C
OH
V @25°C
OL
V @85°C
OL
V @-40°C
OL
V =3.3°C
CC
SN65EPT23
SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
www.ti.com
Figure 1. Maximum Switching Frequency VCC = 3.0 V
Figure 2. Maximum Switching Frequency VCC = 3.3 V
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Product Folder Link(s): SN65EPT23
‘5‘ TEXAS INSTRUMENTS OH 40°C 25°C 5’6 6ND
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
0
1
2
3
4
5
Voltage-V
V @25°C
OH
V @85°C
OH
V @-40°C
OH
V @25°C
OL
V @85°C
OL
V @-40°C
OL
V =3.6°C
CC
GND
Application
TTL Receiver
CharacteristicTest
ACTESTLOAD
RL
*CL
*CL IncludesFixture
Capacitance
2.0V
0.8V
trtf
SN65EPT23
www.ti.com
SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
Figure 3. Maximum Switching Frequency VCC = 3.6 V
Typical Output Loading Used for Device Evaluation
Figure 4. TTL Output Loading Used for Device Evaluation
Figure 5. Output Rise and Fall Times
©2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65EPT23
‘5‘ TEXAS INSTRUMENTS
IN
tPLH tPHL
OUT
IN
1.5V 1.5V
D
D
VPP(min) VPP(max)
SN65EPT23
SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
www.ti.com
Figure 6. Output Propagation Delay
Figure 7. Input Voltage Swing
6Submit Documentation Feedback ©2009–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65EPT23
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SN65EPT23
www.ti.com
SLLS969A –NOVEMBER 2009–REVISED JANUARY 2011
REVISION HISTORY
Changes from Original (November 2009) to Revision A Page
•Deleted last row from the Pin Description Table (EP) .......................................................................................................... 1
©2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65EPT23
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 6-May-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65EPT23D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EPT23 Samples
SN65EPT23DGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAUAG Level-1-260C-UNLIM -40 to 85 SSTI Samples
SN65EPT23DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 SSTI Samples
SN65EPT23DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 EPT23 Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 6-May-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65EPT23DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65EPT23DR SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65EPT23D D SOIC 8 75 506.6 8 3940 4.32
SN65EPT23DGK DGK VSSOP 8 80 330.2 6.6 3005 1.88
Pack Materials-Page 3
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
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