Texas Instruments 的 SN54/74ALVTH16244 规格书

o ESD Protection Exceeds 2000 V Per MlL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 0 Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package NOTE. For tape and reei order entry. The DGGR package is abbreviated to GR and the DGVR package is abbreviated to VR, ] ] ] o 5-V l/O Compatible GND[ 4 45] 0 High Drive Capability (—32 mA/64 mA) 1Y3[ 5 44] 0 Support Mixed-Mode Signal Operation (5-V 1Y4[ 6 43] Input and Output Voltages With 3.3-V Vcc) VCCI: 7 42] 0 Support Unregulated Battery Operation 2” E a M % Down to 2.3 V 2V2 9 40 . GND[ 10 39 ] 0 Typical VOLP (Output Ground Bounce) 2Y3[ H as] <0.8vathc=3.3v,ta=25°c 2v4[t2="" 37]="" o="" autos-state="" eliminates="" bus="" current="" 3y1="" [="" 13="" 36="" ]="" loading="" when="" voltage="" at="" the="" output="" 3y2[="" i4="" 35]="" exceeds="" vcc="" gnd[="" is="" 34]="" 0="" lo"="" and="" power-up="" 3-state="" support="" hot="" 3y3[="" 16="" 33="" ]="" insertion="" 3v4[="" i7="" 32]="" 0="" bus="" hold="" on="" data="" inputs="" eliminates="" the="" vcci:="" ‘3="" 3‘="" 1="" need="" for="" external="" pullup/pulldown="" 4y1="" i:="" 19="" 30]="" resistors="" 4v2[="" 2o="" 29="" ]="" o="" latch-up="" performance="" exceeds="" 250="" ma="" per="" gnde="" 2‘="" 28]="" jesd="" 17="" 4v3[="" 22="" 27]="" ayae="" 23="" 26="" 1="" 1="" 4e[="" 24="" 25="" description="" the="" ‘alvth16244="" devices="" are="" 167bit="" buffers/line="" drivers="" designed="" for="" 2.57v="" or="" 3.3v="" v="" the="" capability="" to="" provide="" a="" ttl="" interface="" to="" a="" 57v="" system="" environment.="" these="" devices="" ca="" buffers,="" two="" 87bit="" buffers,="" or="" one="" 167bitbul1er.="" active="" busnhoid="" circuitry="" is="" provided="" to="" hoid="" unused="" or="" floating="" data="" inputs="" at="" a="" valid="" log="" piease="" be="" aware="" that="" an="" important="" notice="" concerning="" avaiiabiiity,="" standard="" warranty="" and="" use="" texas="" instruments="" semiconductor="" products="" and="" disciairners="" thereto="" appears="" at="" the="" end="" at="" this="" data="" sh="" w="" ebus="" is="" a="" trademark="" at="" texas="" instruments="" incur="" orated="" “mess="" o‘rttznwisz="" noted="" nus="" document="" tannin:="" pionttc‘lialt="" cdpwqn="" i993="" an.="" mm...“="" w.="" .t="" at="" miami="" in.="" pmttucu="" am="" a="" ,="" .eenaim="" re="" m="" m="" a.="" ram="" ram“;="" ma="" .="" pattern="" was.“="" m="" m,.="" mean,="" nan.="" ms="" at="" ..="" exas="" ”ww,="" i="" nstruments="" post="" office="" aox="" $55303="" -="" dallas.="" texas="" 752s5="">
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
5-V I/O Compatible
High Drive Capability (–32 mA/64 mA)
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Auto3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds VCC
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
The ’ALVTH16244 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit
buffers, two 8-bit buffers, or one 16-bit buffer.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54ALVTH16244 . . . WD PACKAGE
SN74ALVTH16244 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
1E Ci—E IA1 47 2 1 V1 3A1 36 IA2 46 : 3 1 V2 3A2 35 : IA! M C 5 1 V3 3A3 33 : IA4 ‘3 g 1 v4 3;“ 32 p 2% ‘3 4E 2A1 41 a 2V1 4M 7 2A2 40 : 9 2V2 4A2 : 2A3 38 : 11 2V: 4A3 : 2A4 37 g 2w 4;“ p i? TEXAS INSTRUMENTS p057 OFFICE aox $553133 - DALLAS IEXAS 752s5
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54ALVTH16244 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE AY
L H H
LLL
HXZ
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
*5 TEXAS INSTRUMENTS
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) –0.5 V to VCC to 7V. . . . . . . . . . . . . .
Output current in the low state, IO: SN54ALVTH16244 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH16244 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the high state, IO: SN54ALVTH16244 –48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH16244 –64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16244 SN74ALVTH16244
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.3 2.7 2.3 2.7 V
VIH High-level input voltage 1.7 1.7 V
VIL Low-level input voltage 0.7 0.7 V
VIInput voltage 0 5.5 0 5.5 V
IOH High-level output current –6 –8 mA
IOL
Low-level output current 6 8
mA
I
OL Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
*9 TEXAS INSTRUMENTS
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH16244 SN74ALVTH16244
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 3 3.6 3 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 5.5 0 5.5 V
IOH High-level output current –24 –32 mA
IOL
Low-level output current 24 32
mA
I
OL Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 48 64
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PARAMETER TEST CONDITIONS VIK Comm mpms Da1a mp1: {P TEXAS INSTRUMENTS
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALVTH16244 SN74ALVTH16244
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 2.3 V, II = –18 mA –1.2 –1.2 V
VCC = 2.3 V to 2.7 V, IOH = –100 µA VCC–0.2 VCC–0.2
VOH
VCC =23V
IOH = –6 mA 1.8 V
V
CC =
2
.
3
V
IOH = –8 mA 1.8
VCC = 2.3 V to 2.7 V, IOL = 100 µA 0.2 0.2
IOL = 6 mA 0.4
VOL
VCC =23V
IOL = 8 mA 0.4 V
V
CC =
2
.
3
V
IOL = 18 mA 0.5
IOL = 24 mA 0.5
p
VCC = 2.7 V, VI = VCC or GND ±1±1
II
u
VCC = 0 or 2.7 V, VI = 5.5 V 10 10
µA
I
I
p
VCC =27V
VI = VCC 1 1 µ
A
u
V
CC =
2
.
7
V
VI = 0 –5 –5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VCC =23V
VI = 0.7 V 115 115
II
(
hold
)
Data inputs
V
CC =
2
.
3
V
VI = 1.7 V –10 –10 µA
I(hold)
VCC = 2.7 V‡, VI = 0 to 2.7 V ±300 ±300
IEX§VCC = 2.3 V, VO = 5.5 V 125 125 µA
IOZ(PU/PD)VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care ±100 ±100 µA
IOZH VCC = 2.7 V VO = 2.3 V,
VI = 0.7 V or 1.7 V 5 5 µA
IOZL VCC = 2.7 V VO = 0.5 V,
VI = 0.7 V or 1.7 V –5 –5 µA
VCC
=
2.7 V,
Outputs high 0.04 0.1 0.04 0.1
ICC
VCC
=
2
.
7
V
,
IO = 0, Outputs low 2.3 4.5 2.3 4.5 mA
VI = VCC or GND Outputs disabled 0.04 0.1 0.04 0.1
CiVCC = 2.5 V, VI = 2.5 V or 0 3 3 pF
CoVCC = 2.5 V, VO = 2.5 V or 0 6 6 pF
†All typical values are at VCC = 2.5 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§Current into an output in the high state when VO > VCC
High-impedance state during power up/power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PARAMETER TEST CONDITIONS VM Cnntmt mpmS *9 TEXAS INSTRUMENTS
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALVTH16244 SN74ALVTH16244
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 3 V, II = –18 mA –1.2 –1.2 V
VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VOH
VCC =3V
IOH = –24 mA 2 V
V
CC =
3
V
IOH = –32 mA 2
VCC = 3 V to 3.6 V, IOL = 100 µA 0.2 0.2
IOL = 16 mA 0.4
VOL
IOL = 24 mA 0.5
V
V
OL VCC = 3 V IOL = 32 mA 0.5
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
p
VCC = 3.6 V, VI = VCC or GND ±1±1
u
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
IIVI = 5.5 V 20 20 µA
Data inputs VCC = 3.6 V VI = VCC 1 1
VI = 0 –5 –5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VCC =3V
VI = 0.8 V 75 75
II
(
hold
)
Data inputs
V
CC =
3
V
VI = 2 V –75 –75 µA
I(hold)
VCC = 3.6 V‡, VI = 0 to 3.6 V ±500 ±500
IEX§VCC = 3 V, VO = 5.5 V 125 125 µA
IOZ(PU/PD)VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care ±100 ±100 µA
IOZH VCC = 3.6 V VO = 3 V,
VI = 0.8 V or 2 V 5 5 µA
IOZL VCC = 3.6 V VO = 0.5 V,
VI = 0.8 V or 2 V –5 –5 µA
VCC
=
3.6 V,
Outputs high 0.07 0.1 0.07 0.1
ICC
VCC
=
3
.
6
V
,
IO = 0, Outputs low 3.2 5 3.2 5 mA
VI = VCC or GND Outputs disabled 0.07 0.1 0.07 0.1
∆ICC#VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND 0.4 0.4 mA
CiVCC = 3.3 V, VI = 3.3 V or 0 3 3 pF
CoVCC = 3.3 V, VO = 3.3 V or 0 6 6 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§Current into an output in the high state when VO > VCC
High-impedance state during power up/power down
#This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PARAMETER ‘PLH ‘PHL ‘PZH ‘PZL ‘PLZ PARAMETER ‘PLH ‘PHL ‘PZH ‘PZL ‘PLZ {P TEXAS INSTRUMENTS
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO SN54ALVTH16244 SN74ALVTH16244
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
tPLH
A
Y
13.1 1 3
ns
tPHL
A
Y
1 3.6 1 3.5
ns
tPZH
OE
Y
1.1 6 1.1 5.9
ns
tPZL
OE
Y
1.1 4.8 1.1 4.7
ns
tPHZ
OE
Y
1.5 4.5 1.5 4.4
ns
tPLZ
OE
Y
13.5 1 3.4
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM TO SN54ALVTH16244 SN74ALVTH16244
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
tPLH
A
Y
12.6 1 2.4
ns
tPHL
A
Y
1 2.6 1 2.5
ns
tPZH
OE
Y
13.9 1 3.8
ns
tPZL
OE
Y
1 3 1 2.9
ns
tPHZ
OE
Y
1.5 4.3 1.5 4.2
ns
tPLZ
OE
Y
1.5 3.7 1.5 3.6
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
LOAD CIRCUIT Va I -V w W *9 TEXAS INSTRUMENTS 8 posw oFFIc
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
I I LOAD CIRCUIT {'3 TEXAS INSTRUMENTS p057 om
SN54ALVTH16244, SN74ALVTH16244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES070G – JUNE 1996 – REVISED MAY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
tPLH tPHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈ 0 V
3 V
0 V
0 V
tw
Input
3 V 3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
0 V
3 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
Figure 2. Load Circuit and Voltage Waveforms
I TEXAS INSTRUMENTS Samples Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74ALVTH16244DLRG4 ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVTH16244
74ALVTH16244GRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVTH16244
74ALVTH16244VRE4 ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VT244
SN74ALVTH16244DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVTH16244
SN74ALVTH16244DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVTH16244
SN74ALVTH16244GR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVTH16244
SN74ALVTH16244VR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VT244
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pi» Reel Diameler AD Dimension designed to accommodate the componeni width ED Dimension deSigned to accommodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w OveraH Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALVTH16244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
SN74ALVTH16244GR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
SN74ALVTH16244VR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVTH16244DLR SSOP DL 48 1000 367.0 367.0 55.0
SN74ALVTH16244GR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74ALVTH16244VR TVSOP DGV 48 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
MPDSODSC 7 FEERUAHV1996 7 HE PLASTIC SM 0,16 NOM 17 i Gage Plane 0,15 7|,20MAX 0E PINS N 14 1s 20 24 as 43 56 DIM AMAX 3170 3.70 5110 5.10 7190 9,80 11,40 AMIN 350 3,50 490 4,90 7170 9,50 11,20 407325| /E 03/00 *5 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 75285
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
J ‘ .: 1:! E 4 T I-EIII :f f E l E 4 0° 5 X7 7 L7 ' TEXAS
www.ti.com
PACKAGE OUTLINE
C
8.3
7.9 TYP
1.2
1.0
46X 0.5
48X 0.27
0.17
2X
11.5
(0.15) TYP
0 - 8 0.15
0.05
0.25
GAGE PLANE
0.75
0.50
A
12.6
12.4
NOTE 3
B6.2
6.0
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
148
0.08 C A B
25
24
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.350
$E§$$fi§$fifim fl%%mgmififimgm r:r A
www.ti.com
EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
48X (1.5)
48X (0.3)
46X (0.5)
(R0.05)
TYP
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
24 25
48
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(7.5)
46X (0.5)
48X (0.3)
48X (1.5)
(R0.05) TYP
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
24 25
48
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
O i H1HHHHHHHHHHHHHHHHHHHHHHZHA % IIIIIIIIIIII 1,20MAX ii ED; ‘V' TEXAS INSTRUMENTS
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA DL (R7PDSO*G48) PLAST‘C SMALLiOUTLINE PACKAGE r WHW_ HHHHHHHH HHHHHHHH HHHHHZHS 0.420 0.395 0.299 (7.59) 0.291 (7,395 0.630 (i600) 0.520 ((5.75) / IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII'_+_ Sealing Piane LII-1 \,_/ 0.110 (2.79) MAX 0.008 (0.20) MIN E0004 (0.10) 404004573/r arm 3 A. AH iinear dimensions are in inches (mili'imelers), a, inis drawing 'is subject to change without notice. 0, Body dimensions do noi inciude maid flush or protrusion noi Io exceed 0005 (0.15), 0. FaHs within JEDEC Moriia NOTES: PaweIPAD is a trademalk 0! Texas insimmems. {I} TEXAS INSTRUMENTS www.ti .ccm
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