Texas Instruments 的 UCC2817A/18A, UCC3817A/18A 规格书

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V'.‘ ‘F. B X E I TEXAS INSTRUMENTS

VREF

DRVOUT

GND

CAI

VCC

OVP/EN

VAOUT

1.9 V

PKLMT

7.5 V

REFERENCE

UVLO

16 V/10 V (UCC3817A)

10.5 V/10 V (UCC3818A)

VCC

OSCILLATOR

S Q

PWM

LATCH

íPWM

CAOUT

VOLTAGE

ERROR AMP 8.0 V

11VSENSE

VFF 8

IAC 6

MOUT

MIRROR

2:1

7.5 V

ENABLE

OVP

XMULT

OSC

CLK

CURRENT

AMP

16 V (FOR UCC3817A ONLY)

0.33 V ZERO POWER

412

Product

Folder

Sample &

Buy

Technical

Documents

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

UCCx81xA BiCMOS Power Factor Preregulator

1 Features

1• Controls Boost Preregulator to Near-Unity Power

Factor

• Limits Line Distortion

• World Wide Line Operation

• Overvoltage Protection

• Accurate Power Limiting

• Average Current Mode Control

• Improved Noise Immunity

• Improved Feed-Forward Line Regulation

• Leading Edge Modulation

• 150-µA Typical Start-Up Current

• Low-Power BiCMOS Operation

• 12-V to 17-V Operation

• Frequency Range of 6 kHz to 220 kHz

2 Applications

• PC Power

• Consumer Electronics

• Lighting

• Industrial Power Supplies

• IEC6100-3-2 Compliant Supplies Less Than

300 W

3 Description

The UCC3817A and the UCC3818A family provides

all the functions necessary for active power factor

corrected preregulators. The controller achieves near

unity power factor by shaping the ac input line current

waveform to correspond to that of the ac input line

voltage. Average current mode control maintains

stable, low distortion sinusoidal line current.

Designed in Texas Instrument's BiCMOS process, the

UCC3817A/UCC3818A offers new features such as

lower start-up current, lower power dissipation,

overvoltage protection, a shunt UVLO detect circuitry,

a leading-edge modulation technique to reduce ripple

current in the bulk capacitor and an improved, low-

offset (±2 mV) current amplifier to reduce distortion at

light load conditions.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

UCCx81xA

SOIC (16) 4.90 mm × 3.91 mm

PDIP (16) 19.30 mm × 6.35 mm

TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Block Diagram

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision.................................................................. 2

5 Description (Continued)........................................ 3

6 Device Comparison Tables................................... 3

7 Pin Configuration and Functions......................... 4

8 Specifications......................................................... 5

8.1 Absolute Maximum Ratings ...................................... 5

8.2 ESD Ratings.............................................................. 5

8.3 Recommended Operating Conditions....................... 5

8.4 Thermal Information.................................................. 6

8.5 Electrical Characteristics........................................... 6

8.6 Typical Characteristics.............................................. 8

9 Detailed Description.............................................. 9

9.1 Overview ................................................................... 9

9.2 Functional Block Diagram......................................... 9

9.3 Feature Description................................................... 9

9.4 Device Functional Modes........................................ 12

10 Application and Implementation........................ 14

10.1 Application Information.......................................... 14

10.2 Typical Application ................................................ 15

11 Power Supply Recommendations ..................... 25

12 Layout................................................................... 25

12.1 Layout Guidelines ................................................. 25

12.2 Layout Example .................................................... 25

13 Device and Documentation Support ................. 26

13.1 Documentation Support ........................................ 26

13.2 Related Links ........................................................ 26

13.3 Receiving Notification of Documentation Updates 26

13.4 Community Resource............................................ 26

13.5 Trademarks........................................................... 26

13.6 Electrostatic Discharge Caution............................ 26

13.7 Glossary................................................................ 26

14 Mechanical, Packaging, and Orderable

Information ........................................................... 27

4 Revision

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (November 2011) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Changed the RθJA and RθJC(top) thermal values for all packages............................................................................................. 6

• Combined the Electrical Characteristics tables ...................................................................................................................... 6

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

5 Description (Continued)

The UCC3817A/18A family of PFC Controllers is directly pin for pin compatible with the UCC3817/18 family of

devices. Only the output stage of UCC3817A family has been modified to allow use of a smaller external gate

drive resistor values. For some power supply designs where an adequately high enough gate drive resistor can

not be used, the UCC3817A/18A family offers a more robust output stage at the cost of increasing the internal

gate resistances. The gate drive of the UC3817A/18A family however remains strong at ±1.2 A of peak current

capability.

UCC3817A offers an on-chip shunt regulator with low start-up current, suitable for applications utilizing a

bootstrap supply. UCC3818A is intended for applications with a fixed supply (VCC). Both devices are available in

the 16-pin D, N and PW packages.

(1) The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g. UCC3817ADR) to order quantities of

2,500 devices per reel (D package) and 2,000 devices per reel (for PW package). Bulk quantities are 40 units (D package) and 90 units

(PW package) per tube.

6 Device Comparison Tables

Table 1. Available Options

TA= TJ

PACKAGE DEVICES

SOIC (D) PACKAGE(1) PDIP (N) PACKAGE TSSOP (PW) PACKAGE(1)

TURNON

THRESHOLD

16 V

TURNON

THRESHOLD

10.2 V

TURNON

THRESHOLD

16 V

TURNON

THRESHOLD

10.2 V

TURNON

THRESHOLD

16 V

TURNON

THRESHOLD

10.2 V

–40°C to 85°C UCC2817AD UCC2818AD UCC2817AN UCC2818AN UCC2817APW UCC2818APW

0°C to 70°C UCC3817AD UCC3818AD UCC3817AN UCC3818AN UCC3817APW UCC3818APW

(1) Average current mode

(2) Critical conduction mode

Table 2. Related Products

DEVICE DESCRIPTION CONTROL METHOD TYPICAL POWER LEVEL

UC3854 PFC controller ACM(1) 200 W to 2 kW+

UC3854A/B Improved PFC controller ACM(1) 200 W to 2 kW+

UC3855A/B High performance soft switching PFC controller ACM(1) 400 W to 2 kW+

UCC38050/1 Transition mode PFC controller CRM(2) 50 W to 400 W

UCC3819 Tracking boost PFC controller ACM(1) 75 W to 2 kW+

UCC28510/11/12/13 Advanced PFC+PWM combo controller ACM(1) 75 W to 1kW+

UCC28514/15/16/17 Advanced PFC+PWM combo controller ACM(1) 75 W to 1kW+

‘5‘ TEXAS INSTRUMENTS

1GND 16 DRVOUT

2PKLMT 15 VCC

3CAOUT 14 CT

4CAI 13 SS

5MOUT 12 RT

6IAC 11 SSENSE

7VAOUT 10 OVP/EN

8VFF 9 VREF

Not to scale

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

7 Pin Configuration and Functions

D, N, and PW Packages

16-Pin SOIC, PDIP, and TSSOP

Top View

Pin Functions

PIN I/O DESCRIPTION

NO. NAME

4 CAI I Current amplifier noninverting input

3 CAOUT O Current amplifier output

14 CT I Oscillator timing capacitor

16 DRVOUT O Gate drive

1 GND — Ground

6 IAC I Current proportional to input voltage

5 MOUT I/O Multiplier output and current amplifier inverting input

10 OVP/EN I Overvoltage/enable

2 PKLMT I PFC peak current limit

12 RT I Oscillator charging current

13 SS I Soft-start

7 VAOUT O Voltage amplifier output

15 VCC I Positive supply voltage

8 VFF I Feed-forward voltage

11 SSENSE I Voltage amplifier inverting input

9 VREF O Voltage reference output

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Supply voltage VCC 18 V

Supply current ICC 20 mA

Gate drive current, continuous 0.2 A

Gate drive current 1.2 A

Input voltage, CAI, MOUT, SS 8 V

Input voltage, PKLMT 5 V

Input voltage, VSENSE, OVP/EN 10 V

Input current, RT, IAC, PKLMT 10 mA

Input current, VCC (no switching) 20 mA

Maximum negative voltage, DRVOUT, PKLMT, MOUT –0.5 V

Power dissipation 1 W

Lead temperature, Tsol (soldering, 10 seconds) 300 °C

Power dissipation 1 W

Junction temperature, TJ–55 150 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±1500

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCC Input voltage 12 18 V

VSENSE Input sense voltage 7.5 10 V

Input current for oscillator 1.36 10 mA

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.4 Thermal Information

THERMAL METRIC(1)

UCCx81xA

UNITD (SOIC) N (PDIP) PW (TSSOP)

16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 73.9 49.3 98.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 33.5 38.9 30.2 °C/W

RθJB Junction-to-board thermal resistance 31.4 29.4 44.8 °C/W

ψJT Junction-to-top characterization parameter 5.8 18.9 1.9 °C/W

ψJB Junction-to-board characterization parameter 31.1 29.2 44.1 °C/W

(1) Ensured by design, not production tested.

8.5 Electrical Characteristics

TA= 0°C to 70°C for the UCC3817A and TA= –40°C to 85°C for the UCC2817A, TA= TJ, VCC = 12 V, RT= 22 kΩ, CT= 270

pF, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT SECTION

Supply current, OFF VCC = (VCC turnon threshold –0.3 V) 150 300 µA

Supply current, ON VCC = 12 V, No load on DRVOUT 2 4 6 mA

UVLO SECTION

VCC turnon threshold (UCCx817) 15.4 16 16.6 V

VCC turnoff threshold (UCCx817) 9.4 9.7 V

UVLO hysteresis (UCCx817) 5.8 6.3 V

Maximum shunt voltage (UCCx817) IVCC = 10 mA 15.4 17 17.5 V

VCC turnon threshold (UCCx818) 9.7 10.2 10.8 V

VCC turnoff threshold (UCCx818) 9.4 9.7 V

UVLO hysteresis (UCCx818) 0.3 0.5 V

VOLTAGE AMPLIFIER SECTION

Input voltage TA= 0°C to 70°C 7.387 7.5 7.613 V

TA= -–40°C to 85°C 7.369 7.5 7.631

VSENSE bias current VSENSE = VREF, VAOUT = 2.5 V 50 200 nA

Open-loop gain VAOUT = 2 V to 5 V 50 90 dB

High-level output voltage IL= –150 µA 5.3 5.5 5.6 V

Low-level output voltage IL= 150 µA 0 50 150 mV

OVER VOLTAGE PROTECTION AND ENABLE SECTION

Over voltage reference VREF

+0.48 VREF

+0.50 VREF

+0.52 V

Hysteresis 300 500 600 mV

Enable threshold 1.7 1.9 2.1 V

Enable hysteresis 0.1 0. 0.3 V

CURRENT AMPLIFIER SECTION

Input offset voltage VCM = 0 V, VCAOUT = 3 V –3.5 0 2.5 mV

Input bias current VCM = 0 V, VCAOUT = 3 V –50 –100 nA

Input offset current VCM = 0 V, VCAOUT = 3 V 25 100 nA

Open loop gain VCM = 0 V, VCAOUT = 2 V to 5 V 90 dB

Common-mode output voltage VCM = 0 V to 1.5 V, VCAOUT = 3 V 60 80 dB

High-level output voltage IL= –120 mA 5.6 6.5 6.8 VV

Low-level output voltage IL= 1 mA 0.1 0.2 0.5 MHz

Gain bandwidth product See (1) 2.5

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

Electrical Characteristics (continued)

TA= 0°C to 70°C for the UCC3817A and TA= –40°C to 85°C for the UCC2817A, TA= TJ, VCC = 12 V, RT= 22 kΩ, CT= 270

pF, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) Reference variation for VCC < 10.8 V is shown in Figure 12.

VOLTAGE REFERENCE SECTION

Input voltage TA= 0°C to 70°C 7.387 7.5 7.613 V

TA= -–40°C to 85°C 7.369 7.5 7.631

Load regulation IREF = 1 mA to 2 mA 0 10 mV

Line regulation VCC = 10.8 to 15 V(2) 0 10 mV

Short-circuit current VREF = 0 V –20 –25 –50 mA

OSCILLATOR SECTION

Initial accuracy TA= 25°C 85 100 115 kHz

Voltage stability VCC = 10.8 to 15 V –1% 1%

Total variation Line, temp 80 120 kHz

Ramp peak voltage 4.5 5 5.5 V

Ramp amplitude voltage (peak to peak) 3.5 4 4.5 V

PEAK CURRENT LIMIT SECTION

PKLMT reference voltage –15 15 mV

PKLMT propagation delay 150 350 500 ns

MULTIPLIER SECTION

IMOUT, high line, low power output

current, (0°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 –6 –20

µA

IMOUT, high line, low power output

current, (–40°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 –6 –23

IMOUT, high line, low power output

current IAC = 500 µA, VFF = 4.7 V, VAOUT = 5 V –70 –90 –105

IMOUT, low line, low power output current IAC = 150 µA, VFF = 1.4 V, VAOUT = 1.25 V –10 –19 –50

IMOUT, low line, high power output

current IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V –268 –300 –345

IMOUT, IAC limited output current IAC = 150 µA, VFF = 1.3 V, VAOUT = 5 V –250 –300 –400

Gain constant (K) IAC = 150 µA, VFF = 1.3 V, VAOUT = 2.5 V 0.5 1 1.5 1/V

IMOUT, zero current IAC = 150 µA, VFF = 1.4 V, VAOUT = 0.25 V 0 –2 µA

IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.25 V 0 –2

IMOUT, zero current, (0°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.5 V 0 –3 µA

IMOUT, zero current, (–40°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.5 V 0 –3.5

Power limit (IMOUT x VFF) IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V –375 –420 –485 µW

FEED-FORWARD SECTION

VFF output current IAC = 300 µA –140 –150 –160 µA

SOFT START SECTION

SS charge current –6 –10 –16 µA

GATE DRIVER SECTION

Pullup resistance IO= –100 mA to –200 mA 9 12 Ω

Pulldown resistance IO= 100 mA 4 10

Output rise time CL= 1 nF, RL= 10 Ω, VDRVOUT = 0.7 V to 9 V 25 50 ns

Output fall time CL= 1 nF, RL= 10 Ω, VDRVOUT = 9 V to 0.7 V 10 50

Maximum duty cycle 93% 95% 99%

Minimum controlled duty cycle At 100 kHz 2%

ZERO POWER SECTION

Zero power comparator threshold Measured on VAOUT 0.2 0.33 0.5 V

l TEXAS INSTRUMENTS um

Output Power

Efficiency (%)

25 50 75 100 125 150 175 200 225 250

100

D001

VIN = 85 V

VIN = 175 V

VIN = 265 V

Output Power (W)

Power Factor

25 50 75 100 125 150 175 200 225 250 275

0.4

0.48

0.56

0.64

0.72

0.8

0.88

0.96

1.04

1.12

1.2

D001

VIN = 85 V

VIN = 175 V

VIN = 265 V

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

8.6 Typical Characteristics

Figure 1. Efficiency vs Output Power Figure 2. Power Factor vs Output Power

l TEXAS INSTRUMENTS

VREF

DRVOUT

GND

CAI

VCC

OVP/EN

VAOUT

1.9 V

PKLMT

7.5 V

REFERENCE

UVLO

16 V/10 V (UCC3817A)

10.5 V/10 V (UCC3818A)

VCC

OSCILLATOR

S Q

PWM

LATCH

íPWM

CAOUT

VOLTAGE

ERROR AMP 8.0 V

11VSENSE

VFF 8

IAC 6

MOUT

MIRROR

2:1

7.5 V

ENABLE

OVP

XMULT

OSC

CLK

CURRENT

AMP

16 V (FOR UCC3817A ONLY)

0.33 V ZERO POWER

412

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

9 Detailed Description

9.1 Overview

The UCC3817A and the UCC3818A family of products provides PFC controllers all the necessary functions for

achieving near unity PFC.

The UCC3817A and UCC3818A, while being pin-compatible with other industry controllers providing similar

functionality, offer many feature enhancements and tighter specifications, leading to an overall reduction in

system implementation cost.

The system performance is enhanced by incorporating many innovative features such as average current-mode

control which maintains stable noise immune low distortion sinusoidal current. Also, the IC features a leading

edge modulation which when synchronized properly with a second stage DC-DC converter can reduce the ripple

current on the output capacitor thereby increasing the overall lifetime of the power supply.

In addition to these features, the key difference between the UCC281xA and the UCC381xA is that the

UCC2817A can work over the extended temperature range of –40 to 85°C as opposed to 0 to 70°C in the case

of the UCC3817A.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Reference Section and Error Amplifier

The reference is a highly accurate 7-V reference with an accuracy of the reference is 1.5%.

The error amplifier is a classic voltage error amplifier and has a short circuit current capability of 20 mA.

9.3.2 Zero Power Block

When the output of the zero power comparator goes below 2.3 V, the zero power comparator latches the gate

drive signal low.

l TEXAS INSTRUMENTS

 

MAX pulldown

GATE MAX

VCC I R

 u

0.6

fRT CT

§ ·

|¨ ¸

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

Feature Description (continued)

9.3.3 Multiplier

The multiplier has 3 inputs. The inputs to the multiplier are VAOUT, the voltage amplifier error signal, IIAC, a

representation of the input rectified AC line voltage, and an input voltage feedforward signal, VVFF.

The multiplier performs the calculation in Equation 1.

IMOUNT = IAC × (VVAOUT – 1) / (K × VVff2)

where

• K = 1/V (1)

As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a

differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation

operation.

9.3.4 Output Overvoltage Protection

When the output voltage exceeds the OVP threshold, the IC stops switching. The OVP reference is at 1.07%.

There is also a 500 mV of hysteresis at the pin.

9.3.5 Pin Descriptions

9.3.5.1 CAI

Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting input

(MOUT) remain functional down to and below GND.

9.3.5.2 CAOUT

This is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC

pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed between

CAOUT and MOUT.

9.3.5.3 CT

A capacitor from CT to GND sets the PWM oscillator frequency according to Equation 2:

(2)

The lead from the oscillator timing capacitor to GND should be as short and direct as possible.

9.3.5.4 DRVOUT

The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. To avoid the excessive

overshoot of the DRVOUT while driving a capacitive load, a series gate current-limiting/damping resistor is

recommended to prevent interaction between the gate impedance and the output driver. The value of the series

gate resistor is based on the pulldown resistance (Rpulldown which is 4 Ωtypical), the maximum VCC voltage

(VCC), and the required maximum gate drive current (IMAX). Using Equation 3, a series gate resistance of

resistance 11 Ωwould be required for a maximum VCC voltage of 18 V and for 1.2 A of maximum sink current.

The source current will be limited to approximately 900 mA (based on the Rpullup of 9-Ωtypical).

(3)

9.3.5.5 GND

All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with a 0.1-µF

or larger ceramic capacitor.

l TEXAS INSTRUMENTS

IAC VAOUT

MOUT 2

VFF

I (V 1)

IV K

u 

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

Feature Description (continued)

9.3.5.6 IAC

This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored

for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum IIAC is

500 µA.

9.3.5.7 MOUT

The output of the analog multiplier and the inverting input of the current amplifier are connected together at

MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as

a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation

operation. The multiplier output current is limited to (2 × IIAC). The multiplier output current is given by Equation 4:

(4)

where is the multiplier gain constant.

9.3.5.8 OVP/EN

A window comparator input that disables the output driver if the boost output voltage is a programmed level

above the nominal or disables both the PFC output driver and resets SS if pulled below 1.9 V (typical).

9.3.5.9 PKLMT

The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense resistor to

VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the peak current

limit. Peak current limit is reached when PKLMT voltage falls below 0 V.

9.3.5.10 RT

A resistor from RT to GND is used to program oscillator charging current. TI recommends a resistor between

10 kΩand 100 kΩ. Nominal voltage on this pin is 3 V.

9.3.5.11 SS

VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a current

source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase

slowly. In the event of a VVCC dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable

the PWM.

NOTE

In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. See the

application section for details.

9.3.5.12 VAOUT

This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output is

internally limited to approximately 5.5 V to prevent overshoot.

9.3.5.13 VCC

Connect to a stable source of at least 20 mA from 10 V to 17 V for normal operation. Bypass VCC directly to

GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent

inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds the upper undervoltage

lockout voltage threshold and remains above the lower threshold.

‘5‘ TEXAS INSTRUMENTS ﬁ—J—L

UDG−02124

Load

RIAC

MULT

S Q

Gate Driver

Logic

VAC

IAC

ZCD

IMO VEA

VREF

UCC2817A

UCC2818A

UCC3817A

UCC3818A

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Feature Description (continued)

9.3.5.14 VFF

The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single pole external filter. At low

line, the VFF voltage should be 1.4 V.

9.3.5.15 VSENSE

This is normally connected to a compensation network and to the boost converter output through a divider

network.

9.3.5.16 VREF

VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA to

peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when VVCC

is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best stability.

See Figure 12 and Figure 13 for VREF line and load regulation characteristics.

9.4 Device Functional Modes

9.4.1 Transition Mode Control

The boost converter, the most common topology used for power factor correction, can operate in two modes:

continuous conduction code (CCM) and discontinuous conduction mode (DCM). Transition mode control, also

referred to as critical conduction mode (CRM) or boundary conduction mode, maintains the converter at the

boundary between CCM and DCM by adjusting the switching frequency.

The CRM converter typically uses a variation of hysteretic control, with the lower boundary equal to zero current.

It is a variable frequency control technique that has inherently stable input current control while eliminating

reverse recovery rectifier losses. As shown in Figure 3, the switch current is compared to the reference signal

(output of the multiplier) directly. This control method has the advantage of simple implementation and good

power factor correction.

Figure 3. Basic Block Diagram of CRM Boost PFC

l TEXAS INSTRUMENTS

UDG−02123

IAVERAGE

(b) DCM

(a) CCM

IPEAK

IAVERAGE

IPEAK

IAVERAGE

Note: Operating Frequency >> 120 Hz

UCC2817A

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Device Functional Modes (continued)

The power stage equations and the transfer functions of the CRM are the same as the CCM. However,

implementations of the control functions are different. Transition mode forces the inductor current to operate just

at the border of CCM and DCM. The current profile is also different, and affects the component power loss and

filtering requirements. The peak current in the CRM boost is twice the amplitude of CCM, leading to higher

conduction losses. The peak-to-peak ripple is twice the average current, which affects MOSFET switching losses

and magnetics ac losses.

Figure 4. PFC Inductor Current Profiles

For low to medium power applications up to approximately 300 W, the CRM boost has an advantage in losses.

The filtering requirement is not severe, and therefore is not a disadvantage. For medium to higher power

applications, where the input filter requirements dominate the size of the magnetics, the CCM boost is a good

choice due to lower peak currents (which reduces conduction losses) and lower ripple current (which reduces

filter requirements). The main tradeoff in using CRM boost is lower losses due to no reverse recovery in the

boost diode vs higher ripple and peak currents.

l TEXAS INSTRUMENTS

PF cos 4

UCC2817A

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The UCC3817A is a BiCMOS average current mode boost controller for high power factor, high efficiency

preregulator power supplies. Figure 5 shows the UCC3817A in a 250-W PFC preregulator circuit. Off-line

switching power converters normally have an input current that is not sinusoidal. The input current waveform has

a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform. An

active power factor correction circuit programs the input current to follow the line voltage, forcing the converter to

look like a resistive load to the line. A resistive load has 05 phase displacement between the current and voltage

waveforms. Power factor can be defined in terms of the phase angle between two sinusoidal waveforms of the

same frequency:

(5)

Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with THD

(total harmonic distortion) of less than 3% are possible with a well-designed circuit. See the following guidelines

for designing PFC boost converters using the UCC3817A.

NOTE

Schottky diodes, D5 and D6, are required to protect the PFC controller from electrical over

stress during system power up.

arm Ea: rrlt, 1

16GND DRVOUT

R17

20 Ÿ

1µF CER

VCC

100 µF AI EI

560 pF

13 C4 0.01 µF

12 R1 12 k

R3 20 k

499 k

249 k

10 k

C5 1 µF

VREF

VCC

VSENSE

OVP/EN

VREF

VAOUT

VFF

C6 2.2 µF

C7 150 nF

100 k

4.02 k

C8 270 pF

R8 12 k

R10

4.02 k

R11

10 k

R12

2 k

R14

0.25 Ÿ

C13

0.47µF

600V

C14

1.5 µF

400V

R13

383 k

IAC

R18

24 k

R15

24 k

R16

100 Ÿ

VCC

C10

1µF C11

1µF

D7 D8

1mH

6A, 600V

8A, 600V

C12

220µF

450V

VOUT

385VíDC

PKLIMIT

CAOUT

CAI

MOUT

IAC

UCC3817A

VLINE

85í270 V

VREF

C9 1.2 nF

R6 30 k

6A 600V

D3 Q1

R19

499 k

R20

274 k

R21

383 k

AC2

AC1

C15 2.2 µF

IRFP450

UCC2817A

UCC2818A

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10.2 Typical Application

Figure 5. Typical Application Circuit

10.2.1 Design Requirements

Table 3 lists the parameters for this application.

Table 3. Design Parameters

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN Input RMS voltage 85 270 V

Input frequency 50/60 Hz

VOUT Output Voltage 385 420 V

POUT Output Power 250 W

Holdup Time All line and load conditions 16 ms

Efficiency Efficiency at 85 Vrms, 100% Load 91%

THD at Low Line 85 Vrms = 100% Load 5%

THD at High Line 265 Vrms, 100% Load 15%

l TEXAS INSTRUMENTS Pout = QM” X Vom X A E N \

( )

ON OFF OFF L ON OFF S

P P V I t t f+ = ´ ´ + ´

COSS OSS OFF S

P C V f= ´ ´ ´

GATE GATE GATE S

P Q V f= ´ ´

 

2 2

OUT

OUT OUT OUT(min)

2 P t

CV V

u u '



 

IN(min)

BOOST V D

LI fs

' u

UCC2817A

UCC2818A

UCC3817A

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10.2.2 Detailed Design Procedure

10.2.2.1 Power Stage

10.2.2.1.1 LBOOST

The boost inductor value is determined by Equation 6:

(6)

where D is the duty cycle, DI is the inductor ripple current and fS is the switching frequency. For the example

circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688 and a

minimum input voltage of 85 VRMS gives us a boost inductor value of about 1 mH. The values used in this

equation are at the peak of low line, where the inductor current and its ripple are at a maximum.

10.2.2.1.2 COUT

Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value

of capacitance is determined by the holdup time required for supporting the load after input ac voltage is

removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For

this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output

power, output voltage, and holdup time gives Equation 7:

(7)

In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage

specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often

necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR

allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple current.

In this design holdup time was the dominant determining factor and a 220-µF, 450-V capacitor was chosen for

the output voltage level of 385 VDC at 250 W.

10.2.2.1.3 Power Switch Selection

As in any power supply design, tradeoffs between performance, cost and size have to be made. When selecting

a power switch, it can be useful to calculate the total power dissipation in the switch for several different devices

at the switching frequencies being considered for the converter. Total power dissipation in the switch is the sum

of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, COSS loss

and turnon and turnoff losses, as shown in Equation 8,Equation 9, and Equation 10.

(8)

(9)

where

• QGATE is the total gate charge

• VGATE is the gate drive voltage

• fSis the clock frequency

• COSS is the drain source capacitance of the MOSFET

• ILis the peak inductor current

• tON and tOFF are the switching times (estimated using device parameters RGATE

• QGD and VTH) and VOFF is the voltage across the switch during the off time, in this case VOFF = VOUT (10)

Conduction loss is calculated with Equation 11 as the product of the RDS(on) of the switch (at the worst case

junction temperature) and the square of RMS current:

l TEXAS INSTRUMENTS

 

VAOUT

MOUT IAC 2

VFF

V 1

I I K V



DELAY

SS 10 A t

C7.5V

P u

( )COND DS on RMS

P R K I= ´ ´

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where

• K is the temperature factor found in the manufacturer's RDS(on) vs. junction temperature curves (11)

Calculating these losses and plotting against frequency gives a curve that enables the designer to determine

either which manufacturer's device has the best performance at the desired switching frequency, or which

switching frequency has the least total loss for a particular power switch. For this design example an IRFP450

HEXFET from International Rectifier was chosen because of its low RDS(on) and its VDSS rating. The IRFP450's

RDS(on) of 0.4 Ωand the maximum VDSS of 500 V made it an ideal choice. An excellent review of this procedure

can be found in the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W, [Multiple

Output High Density DC/DC Converter].

10.2.2.2 Soft Start

The soft-start circuitry is used to prevent overshoot of the output voltage during start-up. This is accomplished by

bringing up the voltage amplifier's output (VVAOUT) slowly which allows for the PWM duty cycle to increase slowly.

Use the following equation to select a capacitor for the soft-start pin.

In this example tDELAY is equal to 7.5 ms, which would yield a CSS of 10 nF.

(12)

In an open-loop test circuit, shorting the soft-start pin to ground does not ensure 0% duty cycle. This is due to the

current amplifiers input offset voltage, which could force the current amplifier output high or low depending on the

polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and bias

current to overcome the current amplifier's offset voltage.

10.2.2.3 Multiplier

The output of the multiplier of the UCC3817A is a signal representing the desired input line current. It is an input

to the current amplifier, which programs the current loop to control the input current to give high power factor

operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the

multiplier are VAOUT, the voltage amplifier error signal, IIAC, a representation of the input rectified ac line

voltage, and an input voltage feedforward signal, VVFF. The output of the multiplier, IMOUT, can be expressed as

shown in Equation 13.

where

• K is a constant typically equal to 1 / V. (13)

The Electrical Characteristics table covers all the required operating conditions for designing with the multiplier.

Additionally, curves in Figure 14,Figure 15, and Figure 16 provide typical multiplier characteristics over its entire

operating range.

The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin

of the UCC3817A and UCC3818A. This resistor (RIAC) is sized to give the maximum IIAC current at high line. For

the UCC3817A and UCC3818A the maximum IIAC current is about 500 mA. A higher current than this can drive

the multiplier out of its linear range. A smaller current level is functional, but noise can become an issue,

especially at low input line. Assuming a universal line operation of 85 VRMS to 265 VRMS gives a RIAC value of 750

kΩ. Because of voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors

connected in series to give the required resistance and distribute the high voltage amongst the resistors. For this

design example two 383-kΩresistors were used in series.

l TEXAS INSTRUMENTS

RSENSE

MOUT MOUT(max)

 

IAC IN(min) VAOUT(max)

MOUT(max) VFF (min)

I @V V 1 V

IK V

u 

VFF VFF P

C 2.2 F

2 R f

| P

u S u u

Pf 120 Hz 0.022 2.6 Hz u |

1.5% 0.022

66%

VFF IN(min)

IAC

1.4V

R 30 k

V 0.9

2 R

| :

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The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed

forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant; and

to provide input power limiting. See Texas Instruments application note Unitrode - UC3854A/B and UC3855A/B

Provide Power Limiting With Sinusoidal Input Current for PFC Front Ends (SLUA196) for a detailed explanation

on how the VFF pin provides power limiting. Equation 14 can be used to size the VFF resistor (RVFF) to provide

power limiting where VIN(min) is the minimum RMS input voltage and RIAC is the total resistance connected

between the IAC pin and the rectified line voltage.

(14)

Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total

harmonic distortion caused by the 120 Hz rectified line voltage. Refer to the Unitrode Power Supply Design

Seminar, SEM-700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter was

adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed,

and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by

this filter is:

(15)

With a ripple frequency (fR) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (fP) be placed

at:

(16)

Equation 17 can be used to select the filter capacitor (CVFF) required to produce the desired low pass filter.

(17)

The RMOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier

current. The maximum multiplier current, or IMOUT(max), can be determined by Equation 18:

(18)

IMOUT(max) for this design is approximately 315 mA. The RMOUT resistor can then be determined by Equation 19:

(19)

In this example VRSENSE was selected to give a dynamic operating range of 1.25 V, which gives an RMOUT of

roughly 3.91 kΩ.

10.2.2.4 Voltage Loop

The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of

the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple at the

input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate the

contribution of this ripple to the total harmonic distortion of the system (see Figure 6).

l TEXAS INSTRUMENTS 4H7 WN—{H ‘H—Wvﬂ/W—I

 

fVI f

R2 f C

S u u

 

VI 2VAOUT OUT IN OUT f

f2 V V R C C

S u ' u u u u

fR VA IN

C(2 f G R )

S u u u

 

VAOUT

VA OPK

( V ) 0.015

G2 V

 

OPK R OUT OUT

V2 f C Vu

Su u

VOUT

RIN

VREF

UCC2817A

UCC2818A

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Figure 6. Voltage Amplifier Configuration

The gain of the voltage amplifier, GVA, can be determined by first calculating the amount of ripple present on the

output capacitor. The peak value of the second harmonic voltage is given by Equation 20.

(20)

In this example VOPK is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from

the voltage loop to the total harmonic distortion budget we set the gain equal to Equation 21.

where

•ΔVVAOUT is the effective output voltage range of the error amplifier (5 V for the UCC3817A). (21)

The network needed to realize this filter is comprised of an input resistor, RIN, and feedback components Cf, CZ,

and Rf. The value of RIN is already determined because of its function as one half of a resistor divider from VOUT

feeding back to the voltage amplifier for output voltage regulation. In this case the value was chosen to be 1 MΩ.

This high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be

realized by the use of two 500-kΩresistors in series because of the voltage rating constraints of most standard

1/4-W resistors. The value of Cfis determined by Equation 22.

(22)

In this example Cfequals 150 nF. Resistor Rfsets the dc gain of the error amplifier and thus determines the

frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop

equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power, can

be calculated by Equation 23.

(23)

fVI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design

Seminar SEM1000, Topic 1, [A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage

Transitions].

Solving for Rfbecomes Equation 24.

(24)

or Rf equals 100 kΩ.

l TEXAS INSTRUMENTS 0.383

CAOUT

2 R u

u S u

Zf C

C2 R f

u S u

EA ID

1 1

G 2.611

G 0.383

 

OUT SENSE

ID BOOST P

V R

G (s) s L Vu

ZVI f

2 R

u S u u

UCC2817A

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Due to the low output impedance of the voltage amplifier, capacitor CZwas added in series with RFto reduce

loading on the voltage divider. To ensure the voltage loop crossed over at fVI, CZwas selected to add a zero at a

10th of fVI. For this design, a 2.2-µF capacitor was chosen for CZ.Equation 25 can be used to calculate CZ.

(25)

10.2.2.5 Current Loop

The gain of the power stage is calculated by Equation 26.

(26)

RSENSE has been chosen to give the desired differential voltage for the current sense amplifier at the desired

current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amp

of 1 V gives a RSENSE value of 0.25 Ω.VPinEquation 26 is the voltage swing of the oscillator ramp, 4 V for the

UCC3817A. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz,

requires a power stage gain at that frequency of 0.383. For the system to have a gain of 1 at the crossover

frequency, the current amplifier needs to have a gain of 1/GID at that frequency. GEA, the current amplifier gain is

then:

(27)

RIis the RMOUT resistor, previously calculated to be 3.9 kΩ. (see Figure 7). The gain of the current amplifier is

Rf/RI, so multiplying RIby GEA gives the value of Rf, in this case approximately 12 kΩ. Setting a zero at the

crossover frequency and a pole at half the switching frequency completes the current loop compensation.

(28)

(29)

Figure 7. Current Loop Compensation

The UCC3817A current amplifier has the input from the multiplier applied to the inverting input. This change in

architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier. It

also adds a phase inversion into the control loop. The UCC3817A takes advantage of this phase inversion to

implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc

controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and cost

and reducing EMI. This is explained in greater detail in the following section. The UCC3817A current amplifier

configuration is shown in Figure 8.

l TEXAS INSTRUMENTS

RMS

V (0.9)

I C t

RSENSE +

MULT

ZfPWM

COMPARATOR

QBOOST

LBOOST

VOUT

UCC2817A

UCC2818A

UCC3817A

UCC3818A

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Figure 8. UCC3817A Current Amplifier Configuration

10.2.2.6 Start-Up

The UCC3818A version of the device is intended to have VCC connected to a 12-V supply voltage. The

UCC3817A has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown

in the typical application circuit of Figure 5. The current drawn by the UCC3817A during undervoltage lockout, or

start-up current, is typically 150 µA. Once VCC is above the UVLO threshold, the device is enabled and draws 4

mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the

shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides

the VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system

design.

(30)

where

• ICis the charge current

• C is the total capacitance at the VCC pin

•ΔV is the UVLO threshold and Δt is the allowed start-up time (31)

Assuming a 1 second allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 µF, a

resistor value of 51 kΩis required at a low line input voltage of 85 VRMS. The IC start-up current is sufficiently

small as to be ignored in sizing the start-up resistor.

10.2.2.7 Capacitor Ripple Reduction

For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits

to synchronizing the two converters. In addition to the usual advantages such as noise reduction and stability,

proper synchronization can significantly reduce the ripple currents in the boost circuit's output capacitor. Figure 9

helps illustrate the impact of proper synchronization by showing a PFC boost converter together with the

simplified input stage of a forward converter. The capacitor current during a single switching cycle depends on

the status of the switches Q1 and Q2 and is shown in Figure 10. It can be seen that with a synchronization

scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple is

highest. The greatest ripple current cancellation is attained when the overlap of Q1 off-time and Q2 on-time is

maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon of

l TEXAS INSTRUMENTS

iCB = iDi - iQ2

iCB

iQ2

iDi

ON OFF ON OFF

ON OFF OFF ON

LOAD

iQ2

VBST

iD1

LIN

IIN

Q1 CBST

iCB

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Q2. This approach implies that the boost converter's leading edge is pulse width modulated while the forward

converter is modulated with traditional trailing edge PWM. The UCC3817A is designed as a leading edge

modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 4 compares

the ICB(rms) for D1/Q2 synchronization as offered by UCC3817A vs the ICB(rms) for the other extreme of

synchronizing the turnon of Q1 and Q2 for a 200-W power system with a VBST of 385 V.

Figure 9. Simplified Representation of a 2-Stage PFC Power Supply

Figure 10. Timing Waveforms for Synchronization Scheme

Table 4 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about

30% at high line with the synchronization scheme facilitated by the UCC3817A. Figure 11 shows the suggested

technique for synchronizing the UCC3817A to the downstream converter. With this technique, maximum ripple

reduction as shown in Figure 10 is achievable. The output capacitance value can be significantly reduced if its

choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs

where holdup time is not critical, this is a significant advantage.

Table 4. Effects of Synchronization on Boost Capacitor Current

VIN = 85 V VIN = 120 V VIN = 240 V

D(Q2) Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 Q1/Q2 D1/Q2

0.35 1.491 A 0.835 A 1.341 A 0.663 A 1.024 A 0.731 A

0.45 1.432A 0.93 A 1.276 A 0.664 A 0.897 A 0.614 A

‘5‘ TEXAS INSTRUMENTS IIIIIIIIIIII

0 5 10 15 20 25

7.495

7.500

7.505

7.510

7.490

IVREF ± Reference Current - mA

VREF ± Reference Voltage - V

141210

7.45

7.50

7.55

7.60

7.40

13119

VCC ± Supply Voltage - V

VREF ± Reference Voltage - V

Gate Drive

From Down

Stream PWM

UCC3817A

UCC2817A

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An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the

turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and

maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and

the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.

Figure 11. Synchronizing the UCC3817A to a Down-Stream Converter

10.2.3 Application Curves

Figure 12. Reference Voltage vs Supply Voltage Figure 13. Reference Voltage vs Reference Voltage

l TEXAS INSTRUMENTS / / / I / A\ // ”AA LLAN

1.0 2.0 3.0 4.0 5.0

100

300

400

500

200

VAOUT = 3 V

VAOUT = 2 V

VAOUT = 4 V

VAOUT = 5 V

0.0

VFF ± Feedforward Voltage - V

(VFF x IMOUT) - W

1.0 2.0 3.0 4.0 5.0

0.7

1.1

1.3

1.5

0.5

0.9 IAC = 300 µA

IAC = 500 µA

IAC = 150 µA

Multiplier Gain - K

VAOUT ± Voltage Error Amplifier Output - V

0.0 1.0 2.0 3.0 4.0 5.0

200

250

350

100

300

150

IAC = 150 Aµ

VFF = 1.4 V

IAC = 300 Aµ

VFF = 3.0 V

IAC = 500 Aµ

VFF = 4.7 V

VAOUT ± Voltage Error Amplifier Output - V

IMOUT ± Multiplier Output Current - A

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

Figure 14. Multiplier Output Current vs Voltage Error

Amplifier Output Figure 15. Multiplier Gain vs Voltage Error Amplifier

Output

Figure 16. Multiplier Constant Power Performance

l TEXAS INSTRUMENTS EE

R16 R10

R11

C10

C11

R21

R13

R19

R20

SYNC

VCC

R22

C14

C15

D5 D6

R12

FA1

UCC3817 EVALUATION BOARD

AC1

XC12

AC2

C13

D8 L1

XL1

D7 R18

R15

HS1

GND

C12

GND

R17

R14

HIGH TEMPERATURE - SEE

EVM WARNINGS AND

RESTRICTIONS

HIGH VOLTAGE -

SEE EVM WARNINGS AND

RESTRICTIONS

HIGH VOLTAGE -

SEE EVM WARNINGS AND

RESTRICTIONS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

11 Power Supply Recommendations

The supply voltage for the device comes from VCC pin. This pin must be bypassed with a high-frequency

capacitor (greater than 1 µF) and tied to GND. The UCC3817A and UCC2817A has a wide UVLO hysteresis of

approximately 6.3 V that allows use of a lower value supply capacitor on this pin for quicker and easier start-up.

12 Layout

12.1 Layout Guidelines

12.1.1 Bias Current

The bias voltage is supplied either by an external dedicated DC-DC converter or by an auxiliary winding from the

PFC inductor or the 2nd stage DC-DC converter.

The bias capacitor should be large enough to maintain sufficient voltage with AC line variations. Connect a 1-µF

capacitor between VCC and GND as close to the IC as possible. For wide line voltages, an additional 18-V Zener

clamp can also be used.

12.1.2 VREF

Connect a capacitor >=0.1 µF between VREF and GND for stability.

12.2 Layout Example

Figure 17. UCC3817EVM Evaluation Board Layout Assembly

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

www.ti.com

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following:

1. Differences Between UCC3817A/18A/19A and UCC3817/18/19 (SLUA294)

2. UCC3817 BiCMOS Power Factor Preregulator Evaluation Board (SLUU077)

3. Synchronizing a PFC Controller from a Down Stream Controller Gate Drive (SLUA245)

4. Seminar topic, High Power Factor Switching Preregulator Design Optimization, L.H. Dixon, SEM-700,1990.

5. Seminar topic, High Power Factor Preregulator for Off-line Supplies, L.H. Dixon, SEM-600, 1988.

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 5. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

UCC2817A Click here Click here Click here Click here Click here

UCC2818A Click here Click here Click here Click here Click here

UCC3817A Click here Click here Click here Click here Click here

UCC3818A Click here Click here Click here Click here Click here

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.4 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

l TEXAS INSTRUMENTS

UCC2817A

UCC2818A

UCC3817A

UCC3818A

www.ti.com

SLUS577D –NOVEMBER 2011–REVISED AUGUST 2016

Product Folder Links: UCC2817A UCC2818A UCC3817A UCC3818A

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UCC2817AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2817AD

UCC2817ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2817AD

UCC2817AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 UCC2817AN

UCC2817APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2817A

UCC2817APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2817A

UCC2818AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2818AD

UCC2818ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2818AD

UCC2818AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 UCC2818AN

UCC2818APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2818A

UCC2818APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2818A

UCC2818APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 2818A

UCC3817AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3817AD

UCC3817ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3817AD

UCC3817AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UCC3817AN

UCC3818AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3818AD

UCC3818ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3818AD

UCC3818AN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UCC3818AN

UCC3818APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 3818A

UCC3818APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 3818A

(1) The marketing status values are defined as follows:

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 2

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC2818A :

•Automotive : UCC2818A-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width Bo Dimension deSigned to accommodate the component iengtn K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UCC2817ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC2817APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

UCC2818ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC2818APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

UCC3817ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC3818ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC3818APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Mar-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC2817ADR SOIC D 16 2500 340.5 336.1 32.0

UCC2817APWR TSSOP PW 16 2000 853.0 449.0 35.0

UCC2818ADR SOIC D 16 2500 340.5 336.1 32.0

UCC2818APWR TSSOP PW 16 2000 853.0 449.0 35.0

UCC3817ADR SOIC D 16 2500 340.5 336.1 32.0

UCC3818ADR SOIC D 16 2500 340.5 336.1 32.0

UCC3818APWR TSSOP PW 16 2000 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Mar-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

UCC2817AD D SOIC 16 40 507 8 3940 4.32

UCC2817AN N PDIP 16 25 506 13.97 11230 4.32

UCC2817APW PW TSSOP 16 90 530 10.2 3600 3.5

UCC2818AD D SOIC 16 40 507 8 3940 4.32

UCC2818AN N PDIP 16 25 506 13.97 11230 4.32

UCC2818APW PW TSSOP 16 90 508 8.5 3250 2.8

UCC3817AD D SOIC 16 40 507 8 3940 4.32

UCC3817AN N PDIP 16 25 506 13.97 11230 4.32

UCC3818AD D SOIC 16 40 507 8 3940 4.32

UCC3818AN N PDIP 16 25 506 13.97 11230 4.32

UCC3818APW PW TSSOP 16 90 530 10.2 3600 3.5

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Mar-2022

Pack Materials-Page 3

MECHANICAL DATA D ( *"iﬁ O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eiﬂ{iEr-Hﬂ-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com

www.ti.com

PACKAGE OUTLINE

14X 0.65

4.55

16X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

NOTE 4

4.5

4.3

NOTE 3

5.1

4.9

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.500

v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

YL““‘+““‘ ﬁmmamﬂ J

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘ﬁ: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): noﬁce /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmﬂder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkﬂh INSI'RUMENTS www.1i.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments 的 UCC2817A/18A, UCC3817A/18A 规格书

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