Microchip Technology 的 ATF1500A(L) 规格书

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1
TQFP
Top View
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33
32
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I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
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I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
PLCC
Top View
7
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39
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I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
6
5
4
3
2
1
44
43
42
41
40
18
19
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I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
Pin Configurations
Pin
Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional
Buffers
GCLR Register Reset
(active low)
OE1,
OE2
Output Enable
(active low)
VCC +5V Supply
PD Power-down
(active high)
Features
•High-density, High-performance Electrically-erasable Complex
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation Up to 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware
•Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
•Advanced Power Management Features
– Automatic 3 mA Standby (ATF1500AL)
– Pin-controlled 10 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
•Available in Commercial and Industrial Temperature Ranges
•Available in 44-lead PLCC and TQFP Packages
•Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
•Supported by Popular third-arty Tools
•Security Fuse Feature
•Pin-compatible with the Most Commonly Used Devices
•Green (Pb/Halide-fee/RoHS Compliant) Package Options
Description
The ATF1500A is a high-performance, high-density complex PLD. Built on an
advanced Flash technology, it has maximum pin-to-pin delays of 7.5 ns and supports
sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up
to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs.
The ATF1500A’s global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.
High-
performance
EPLD
ATF1500A
ATF1500AL
Rev. 0759F–6/05
(continued)
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ATF1500A(L)
2
Functional Logic Diagram(1)
Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
The ATF1500A has 32 bi-directional I/O pins and four dedi-
cated input pins. Each dedicated input pin can also serve
as a global control signal: register clock, register reset or
output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 32 logic macrocells generates a buried feed-
back, which goes to the global bus. Each input and I/O pin
also feeds into the global bus. Because of this global bus-
ing, each of these signals is always available to all 32 mac-
rocells in the device.
A IIIEI.
ATF1500A(L)
3
Each macrocell also generates a foldback logic term, which
goes to a regional bus. All signals within a regional bus are
connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic functions. The
ATF1500A contains four such logic chains, each capable of
creating sum term logic with a fan-in of up to 40 product
terms.
Bus-friendly Pin-keeper Input and I/O’s
All Input and I/O pins on the ATF1500A have programma-
ble “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
This circuitry prevents unused Input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is con-
trolled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination procedures are required
for unused inputs and I/Os.
Speed/Power Management
The ATF1500A has several built-in speed and power man-
agement features. The ATF1500A contains circuitry that
automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only
reduces power consumption during inactive periods, but
also provides proportional power savings for most applica-
tions running at system speeds below 10 MHz.
All ATF1500As also have an optional pin-controlled power-
down mode. In this mode, current drops to below 10 mA.
When the power-down option is selected, the PD pin is
used to power-down the part. The power-down option is
selected in the design source file. When enabled, the
device goes into power-down when the PD pin is high. In
the power-down mode, all internal logic signals are latched
and held, as are any enabled outputs. All pin transitions are
ignored until the PD is brought low. When the power-down
feature is enabled, the PD cannot be used as a logic input
or output. However, the PD pin’s macrocell may still
be used to generate buried foldback and cascade
logic signals.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Design Software Support
ATF1500A designs are supported by several third-party
tools. Automated fitters allow logic synthesis using a variety
of high-level description languages and formats.
Input Diagram
I/O Diagram
100K
VCC
ESD
PROTECTION
CIRCUIT
INPUT
PROGRAMMABLE
OPTION
100K
V
CC
V
CC
DATA
OE
I/O
PROGRAMMABLE
OPTION
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ATF1500A(L)
4
ATF1500A(L) Macrocell
ATF1500A Macrocell
The ATF1500A macrocell is flexible enough to support
highly-complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod-
uct term select multiplexer, OR/XOR/CASCADE logic, a
flip-flop, output select and enable, and logic array inputs.
Product Terms and Select Mux
Each ATF1500A macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler that selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1500A macrocell’s OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be
routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with little small additional delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate T-type flip-flops.
Flip-flop
The ATF1500A’s flip-flop has very flexible data and control
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa-
rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.
41m
ATF1500A(L)
5
In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched
when the clock is low.
The clock itself can be either the global CLK pin or an indi-
vidual product term. The flip-flop changes state on the
clock’s rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. When the clock enable function is active and
the enable signal (product term) is low, all clock edges are
ignored.
The flip-flop’s asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic OR of GCLR with a product term.
The asynchronous preset (AP) can be a product term or
always off.
Output Select and Enable
The ATF1500A macrocell output can be selected as regis-
tered or combinatorial. When the output is registered, the
same registered signal is fed back internally to the global
bus. When the output is combinatorial, the buried feedback
can be either the same combinatorial signal or it can be the
register output if the separate product term is chosen as
the flip-flop input.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can also be selected
as either of the two OE pins or as an individual product
term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells.
Together with the complement of each signal, this provides
a 68-bit bus as input to every product term. Having the
entire global bus available to each macrocell eliminates
any potential routing problems. With this architecture
designs can be modified without requiring pinout changes.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus, and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with little additional delay.
Am
ATF1500A(L)
6
Note: 1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 5.25V for pulses of less
than 20 ns.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (ambient) 0°C - 70°C-40°C - 85°C
VCC Power Supply 5V ± 5% 5V ± 10%
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input or I/O
Low Leakage Current 0 ≤ VIN ≤ VIL (Max) -10 µA
IIH Input or I/O
High Leakage Current VIH, Min ≤ VIN ≤ VCC 10 µA
ICC1(1) Power Supply Current,
Standby
VCC = Max,
VIN = 0, VCC
ATF1500A Com. 70 mA
Ind. 100 mA
ATF1500AL Com. 3 mA
Ind. 5 mA
ICC2
Power Supply Current,
Pin-Controlled Power
Down Mode
VCC = Max,
VIN = 0, VCC
210mA
IOS
Output Short Circuit
Current VOUT = 0.5V -130 mA
VIL Input Low Voltage VCC, Min < VCC
< VCC, Max -0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 1 V
VOL Output Low Voltage VCC = Min IOL = 12 mA 0.45 V
VOH Output High Voltage VCC = Min IOH = -4 mA 2.4 V
IOH = -0.2 mA VCC - 0.2 V
INPUTS, V0 REG FEEDBACK CLK HEGTSTEPED OUTPUTS COMEWATOHIAL OUTPUTS us“ -km a «SP OUTPUT L T , H'GHZ OUTPUT VALTD VAL‘D . tER, - P ‘EA, ) «sz «sz OUTPUT ‘ H‘GHZ OUTPUT VAUD VALID A IIIEI.
ATF1500A(L)
7
AC Waveforms
Note: 1. For slow slew outputs, add tSSO .
Register AC Characteristics, Input Pin Clock
Symbol Parameter
-7 -10 -12 -15 -20 -25
UnitsMin Max Min Max Min Max Min Max Min Max Min Max
tCOS(1) Clock to Output 4.5 2 5 2 6 2 8 2 9 2 9 ns
tCFS Clock to Feedback 2 22222ns
tSIS I, I/O Setup Time 6 8 10 11 14 16 ns
tSFS Feedback Setup
Time 6 8 10 11 12 13 ns
tHS Input, I/O, Feedback
Hold Time 0 00000ns
tPS Clock Period6 8 9 101112 ns
tWS Clock Width 3 4 4.5 5 5.5 6 ns
fMAXS
External Feedback
1/(tSIS + tCOS)95 76.9 62.5 52.6 43 40 MHz
Internal Feedback
1/(tSFS + tCFS)125 100 83.3 76.9 71 66 MHz
No Feedback 1/(tPS) 166.7 125 111 100 91 83 MHz
tRPRS Reset Pin Recovery
Time 2 33455ns
tRTRS Reset Term
Recovery Time 6 9 10 12 13 14 ns
A IIIEI.
ATF1500A(L)
8
Note: 1. For slow slew outputs, add tSSO .
Register AC Characteristics, Product Term Clock
Symbol Parameter
-7 -10 -12 -15 -20 -25
UnitsMin Max Min Max Min Max Min Max Min Max Min Max
tCOA(1) Clock to Output 7.5 10 12 15 18 20 ns
tCFA Clock to Feedback 5 7 7 9 12 15 ns
tSIA I, I/O Setup Time 3 3 4 4 8 10 ns
tSFA Feedback Setup
Time 3 3 4 4 12 15 ns
tHA Input, I/O, Feedback
Hold Time 2 34455ns
tPA Clock Period 6 8 10 12 24 30 ns
tWA Clock Width 3 4 5 6 12 15 ns
fMAXA
External Feedback
1/(tSIA + tCOA)95.2 76.9 62.5 52.6 38 33.3 MHz
Internal Feedback
1/(tSFA + tCFA)125 100 90.9 76.9 41.7 33.3 MHz
No Feedback 1/(tPA) 166.7 125 100 83.3 41.7 33.3 MHz
tRPRA Reset Pin Recovery
Time 0 000 00ns
tRTRA Reset Term
Recovery Time 4 566 78ns
41m
ATF1500A(L)
9
Note: 1. For slow slew outputs, add tSSO .
AC Characteristics
Symbol Parameter
-7 -10 -12 -15 -20 -25
UnitsMin Max Min Max Min Max Min Max Min Max Min Max
tPD(1) I, I/O or FB to
Non-Registered
Output
27.5310312315320325 ns
tPD2 I, I/O to Feedback 5 7 8 9 12 14 ns
tPD3(1) Feedback to
Non-Registered
Output
27.5310312315320325 ns
tPD4 Feedback to
Feedback 5 7 8 9 12 14 ns
tEA(1) OE Term to Output
Enable 27.5310312315320325 ns
tER OE Term to Output
Disable 27.5210212215220225 ns
tPZX(1) OE Pin to Output
Enable 25.5272829210211ns
tPXZ OE Pin to Output
Disable 1.5 5.5 1..5 7 1.5 8 1.5 9 1.5 10 1.5 11 ns
tPF Preset to Feedback 6 9 9 12 18 20 ns
tPO(1) Preset to Registered
Output 8.51214202325ns
tRPF Reset Pin to
Feedback 34355.56ns
tRPO(1) Reset Pin to
Registered Output 5.5 7 8 11 13 15 ns
tRTF Reset Term to
Feedback 699121520ns
tRTO(1) Reset Term to
Registered Output 8.51214202325ns
tCAS Cascade Logic Delay 0.8 0.8 1 1 1.5 1.5 ns
tSSO Slow Slew Output
Adder 333444ns
tFLD Foldback Term Delay 4 5 7 8 10 12 ns
A IIIEI. H1:464 no PIN R2:250 CL=35 pF
ATF1500A(L)
10
Notes: 1. For slow slew outputs, add tSSO .
2. Pin or Product Term.
Input Test Waveforms and
Measurement Levels Output Test Load
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Down AC Characteristics
Symbol Parameter
-7 -10 -12 -15 -20 -25
UnitsMin Max Min Max Min Max Min Max Min Max Min Max
tIVDH Valid I, I/O Before
PD High 7 1012152025 ns
tGVDH Valid OE(2)
Before PD High 7 1012152025 ns
tCVDH Valid Clock(2)
Before PD High 7 1012152025 ns
tDHIX Input Don't Care
After PD High 15 20 22 25 30 35 ns
tDHGX OE Don't Care
After PD High 15 20 22 25 30 35 ns
tDHCX Clock Don't Care
After PD High 15 20 22 25 30 35 ns
tDLIV PD Low to Valid I,
I/O 111111µs
tDLGV PD Low to Valid
OE(2) 111111µs
tDLCV PD Low to Valid
Clock(2) 111111µs
tDLOV(1) PD Low to Valid
Output 111111µs
3.0V
0.0V
1.5V
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
tr, tf ≤ 1.5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ Max Units Conditions
CIN 4.5 5.5 pF VIN = 0V
COUT 3.5 4.5 pF VOUT = 0V
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ATF1500A(L)
11
Power-up Reset
The ATF1500A’s registers are designed to reset during
power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be low on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic, from below 0.7 volt,
2. After reset occurs, all input and feedback setup times
must be met before driving the clock signal high, and
3. Signals from which clocks are derived must remain sta-
ble during tPR.
Power-down Mode
The ATF1500A includes an optional pin-controlled power-
down feature. When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 10 mA. During
power-down, all output data and internal logic states are
latched and held. Therefore, all registered and combinato-
rial output data remain valid. Any outputs that were in a
high-Z state at the onset of power-down will remain at
high-Z. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indetermi-
nate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs
using the power-down pin may not use the PD pin logic
array input. However, all other PD pin macrocell resources
may still be used, including the buried feedback and fold-
back product term array inputs.
Register Preload
The ATF1500A’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with preload vectors is compiled. Once downloaded, the
JEDEC file preload sequence will be done automatically
when vectors are run by any approved programmers. The
preload mode is enabled by raising an input pin to a high
voltage level. Contact Atmel PLD Applications for PRE-
LOAD pin assignments, timing and voltage requirements.
Output Slew Rate Control
Each ATF1500A macrocell contains a configuration bit for
each I/O to control its output slew rate. This allows selected
data paths to operate at maximum throughput while reduc-
ing system noise from outputs that are not speed-critical.
Outputs default to slow edges, and may be individually set
to fast in the design file. Output transition times for outputs
configured as “slow” have a tSSO delay adder.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1500A fuse patterns. Once programmed, fuse
verify and preload are prohibited. However, the 160-bit
User Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Parameter Description Typ Max Units
tPR Power-up
Reset Time 210 µs
VRST
Power-up
Reset
Voltage
3.8 4.5 V
A IIIEI. T1 12 NORM ‘ ‘ mA I o s o m an an An so FREQUENCY (MHzp ° 2° 40 50 8° ‘00 FREouENCY (MHz) T 15 T 04 T T T 02 T 05 NORM ATFVSODA 1 1 Ice mA ATFTaonAL NORM 95 95 9 95 55 A s 4 75 s o s 25 s 5 .34 SUFF’LV VOLTAGE (V) D 25 75 AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. SUPPLY VOLTAGE (vDH : 2.4V. TA : 25 C) 720 ran 740 IDH mA -5u ran ,70 A5 475 so 525 55 as 475 so 525 55 SUPPLY VOLTAGE (V) SUPPLV VOLTAGE (v) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE (VOH = 2.4V, TA = 25'0) o '2 720 " 740 IDH mA s 760 ran "° 400 42 420 3 35 t 45 5 005‘152253354455 OUTPUT VOLTAGE {V} OUTPUT VOLTAGE (V)
ATF1500A(L)
12
NORMALIZED SUPPLY CURRENT
vs. INPUT FREQUENCY
ATF1500A (V
cc
= 5V, TA = 25˚C)
I
CC
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ATF1500 (TA = 25˚C)
I
CC
I
OH
OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25˚C)
IOH mA
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VOH = 2.4V, TA = 25˚C)
SUPPLY CURRENT
vs. FREQUENCY
ATF1500AL (V
CC
= 5V, TA = 25˚C)
I
CC
mA
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
ATF1500 (V
CC
= 5V)
I
CC
mA
OUTPUT SINK SURRENT
vs. SUPPLY VOLTAGE (TA = 25˚C, VOL = 0.45V)
IOL mA
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VCC = 5V, TA = 25˚C)
IOH mA
12 H NORM T 9 a 05 In I5 20 25 30 E OUTPUT VOLTAGE IV) D 25 75 AMBIENT TEMPERATURE (C) o 45 12 ran INPUT As “ CURRENT 60 "IA NORM I 775 750 9 rms 4o 42 VI rs re 74 72 o INPUTVOLTAGEIVI a 25 75 AMBIENT TEMPERATURE (CI mo 75 50 25 I2 INPUT CURRENT 0 M 725 1.1 NORM -so 775 we a 1 2 3 4 5 5 INPUT VOLTAGE (VI o 25 75 AMBIENT TEMPERATURE IC) Toe Tm NORM .95 92 .ss 45 475 5 525 55 SUPPLY VOLTAGE (V) A IIIEI.
ATF1500A(L)
13
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE (V
CC
= 5V, TA = 25˚C)
IOL mA
INPUT CLAMP CURRENT
vs. INPUT VOLTAGE
INPUT CURRENT vs. INPUT VOLTAGE
(V
CC
= 5V, TA = 25˚C)
NORMALIZED tCOS
vs. SUPPLY VOLTAGE (TA = 25˚C)
tCOS
t
PD
NORMALIZED t
PD
vs. AMBIENT TEMPERATURE (V
CC
= 5V)
t
COS
NORMALIZED t
COS
vs. AMBIENT TEMPERATURE (V
CC
= 5V)
tCOA
NORMALIZED t
COA
vs. AMBIENT TEMPERATURE (V
CC
= 5V)
1m 1.02 NORM 93 96 94 12 1 NORM A5 4.75 5 5 25 SUPRLV VOLTAGE (V) 5.5 1 475 5 525 SUPPLY VOLTAGE (V) 55 A IIIEI. NORM NORM 1.2 1.1 25 AMBTENT TEMPERATURE 1C) 75 25 AMBTENT TEMPERATURE (C) 75
ATF1500A(L)
14
t
SIS
NORMALIZED t
SIS
vs. SUPPLY VOLTAGE (TA = 25˚C)
t
SIA
NORMALIZED t
SIA
vs. SUPPLY VOLTAGE (TA = 25˚C)
t
SIS
NORMALIZED t
SIS
vs. AMBIENT TEMPERATURE (V
CC
= 5V)
t
SIA
NORMALIZED t
SIA
vs. AMBIENT TEMPERATURE (V
CC
= 5V)
41m
ATF1500A(L)
15
Ordering Information
Note: 1. The last time buy date is Sept. 30, 2005 for shaded parts. The replacements for fast-speed grade is the ATF1502AS (pin
compatible). For others, suggested replacements are available in Green packages.
2. The ATF1500AL-25AC, -25AI, -25JC and -25JI were obsoleted in August 1999. The replacement was the ATF1500AL-20.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Standard Package Options
tPD
(ns)
tCOS
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
7.5 4.5 95 ATF1500A-7AC
ATF1500A-7JC
44A
44J
Commercial
(0°C to 70°C)
10 5 76.9
ATF1500A-10AC
ATF1500A-10JC
44A
44J
Commercial
(0°C to 70°C)
ATF1500A-10AI 44A
44J
Industrial
(-40°C to 85°C)
ATF1500A-10JI
12 6 62.5
ATF1500A-12AC
ATF1500A-12JC
44A
44J
Commercial
(0°C to 70°C)
ATF1500A-12AI
ATF1500A-12JI
44A
44J
Industrial
(-40°C to 85°C)
15 8 52.6
ATF1500A-15AC 44A
44J
Commercial
(0°C to 70°C)
ATF1500A-15JC
ATF1500A-15AI
ATF1500A-15JI
44A
44J
Industrial
(-40°C to 85°C)
20 9 40
ATF1500AL-20AC
ATF1500AL-20JC
44A
44J
Commercial
(0°C to 70°C)
ATF1500AL-20AI
ATF1500AL-20JI
44A
44J
Industrial
(-40°C to 85°C)
Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCOS
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
10 5 76.9 ATF1500A-10AU
ATF1500A-10JU
44A
44J
Industrial
(-40°C to 85°C)
20 9 40 ATF1500AL-20AU
ATF1500AL-20JU
44A
44J
Industrial
(-40°C to 85°C)
Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
A IIIEI. HHHHHHHHHHH ‘HHHHHHHHHHH \ w“ 4% w i \ UUUUUUUUUUUL UUUUUUUUUUU i , T i j ii—VL 71*! "\ ATM—EL,
ATF1500A(L)
16
Packaging Information
44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
44A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
mm 41m
ATF1500A(L)
17
44J – PLCC
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B
44J
10/04/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
A IIIEI.
ATF1500A(L)
18
Revision History
Revision Comments
0759F Green package options added.
41m —@
Printed on recycled paper.
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